03ca106d0d8833cd19e80a4d4adff5be53266605
[openwrt/openwrt.git] / target / linux / ar71xx / patches-4.4 / 601-MIPS-ath79-add-more-register-defines.patch
1 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
2 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
3 @@ -20,6 +20,10 @@
4 #include <linux/bitops.h>
5
6 #define AR71XX_APB_BASE 0x18000000
7 +#define AR71XX_GE0_BASE 0x19000000
8 +#define AR71XX_GE0_SIZE 0x10000
9 +#define AR71XX_GE1_BASE 0x1a000000
10 +#define AR71XX_GE1_SIZE 0x10000
11 #define AR71XX_EHCI_BASE 0x1b000000
12 #define AR71XX_EHCI_SIZE 0x1000
13 #define AR71XX_OHCI_BASE 0x1c000000
14 @@ -39,6 +43,8 @@
15 #define AR71XX_PLL_SIZE 0x100
16 #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
17 #define AR71XX_RESET_SIZE 0x100
18 +#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000)
19 +#define AR71XX_MII_SIZE 0x100
20
21 #define AR71XX_PCI_MEM_BASE 0x10000000
22 #define AR71XX_PCI_MEM_SIZE 0x07000000
23 @@ -81,15 +87,21 @@
24
25 #define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
26 #define AR933X_UART_SIZE 0x14
27 +#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
28 +#define AR933X_GMAC_SIZE 0x04
29 #define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
30 #define AR933X_WMAC_SIZE 0x20000
31 #define AR933X_EHCI_BASE 0x1b000000
32 #define AR933X_EHCI_SIZE 0x1000
33
34 +#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
35 +#define AR934X_GMAC_SIZE 0x14
36 #define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
37 #define AR934X_WMAC_SIZE 0x20000
38 #define AR934X_EHCI_BASE 0x1b000000
39 #define AR934X_EHCI_SIZE 0x200
40 +#define AR934X_NFC_BASE 0x1b000200
41 +#define AR934X_NFC_SIZE 0xb8
42 #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
43 #define AR934X_SRIF_SIZE 0x1000
44
45 @@ -106,11 +118,15 @@
46 #define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
47 #define QCA955X_PCI_CTRL_SIZE 0x100
48
49 +#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
50 +#define QCA955X_GMAC_SIZE 0x40
51 #define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
52 #define QCA955X_WMAC_SIZE 0x20000
53 #define QCA955X_EHCI0_BASE 0x1b000000
54 #define QCA955X_EHCI1_BASE 0x1b400000
55 #define QCA955X_EHCI_SIZE 0x1000
56 +#define QCA955X_NFC_BASE 0x1b800200
57 +#define QCA955X_NFC_SIZE 0xb8
58
59 #define AR9300_OTP_BASE 0x14000
60 #define AR9300_OTP_STATUS 0x15f18
61 @@ -181,6 +197,9 @@
62 #define AR71XX_AHB_DIV_SHIFT 20
63 #define AR71XX_AHB_DIV_MASK 0x7
64
65 +#define AR71XX_ETH0_PLL_SHIFT 17
66 +#define AR71XX_ETH1_PLL_SHIFT 19
67 +
68 #define AR724X_PLL_REG_CPU_CONFIG 0x00
69 #define AR724X_PLL_REG_PCIE_CONFIG 0x18
70
71 @@ -193,6 +212,8 @@
72 #define AR724X_DDR_DIV_SHIFT 22
73 #define AR724X_DDR_DIV_MASK 0x3
74
75 +#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c
76 +
77 #define AR913X_PLL_REG_CPU_CONFIG 0x00
78 #define AR913X_PLL_REG_ETH_CONFIG 0x04
79 #define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
80 @@ -205,6 +226,9 @@
81 #define AR913X_AHB_DIV_SHIFT 19
82 #define AR913X_AHB_DIV_MASK 0x1
83
84 +#define AR913X_ETH0_PLL_SHIFT 20
85 +#define AR913X_ETH1_PLL_SHIFT 22
86 +
87 #define AR933X_PLL_CPU_CONFIG_REG 0x00
88 #define AR933X_PLL_CLOCK_CTRL_REG 0x08
89
90 @@ -226,6 +250,8 @@
91 #define AR934X_PLL_CPU_CONFIG_REG 0x00
92 #define AR934X_PLL_DDR_CONFIG_REG 0x04
93 #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
94 +#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24
95 +#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c
96
97 #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
98 #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
99 @@ -258,9 +284,13 @@
100 #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
101 #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
102
103 +#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6)
104 +
105 #define QCA955X_PLL_CPU_CONFIG_REG 0x00
106 #define QCA955X_PLL_DDR_CONFIG_REG 0x04
107 #define QCA955X_PLL_CLK_CTRL_REG 0x08
108 +#define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28
109 +#define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48
110
111 #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
112 #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
113 @@ -385,16 +415,83 @@
114 #define AR913X_RESET_USB_HOST BIT(5)
115 #define AR913X_RESET_USB_PHY BIT(4)
116
117 +#define AR933X_RESET_GE1_MDIO BIT(23)
118 +#define AR933X_RESET_GE0_MDIO BIT(22)
119 +#define AR933X_RESET_GE1_MAC BIT(13)
120 #define AR933X_RESET_WMAC BIT(11)
121 +#define AR933X_RESET_GE0_MAC BIT(9)
122 #define AR933X_RESET_USB_HOST BIT(5)
123 #define AR933X_RESET_USB_PHY BIT(4)
124 #define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
125
126 +#define AR934X_RESET_HOST BIT(31)
127 +#define AR934X_RESET_SLIC BIT(30)
128 +#define AR934X_RESET_HDMA BIT(29)
129 +#define AR934X_RESET_EXTERNAL BIT(28)
130 +#define AR934X_RESET_RTC BIT(27)
131 +#define AR934X_RESET_PCIE_EP_INT BIT(26)
132 +#define AR934X_RESET_CHKSUM_ACC BIT(25)
133 +#define AR934X_RESET_FULL_CHIP BIT(24)
134 +#define AR934X_RESET_GE1_MDIO BIT(23)
135 +#define AR934X_RESET_GE0_MDIO BIT(22)
136 +#define AR934X_RESET_CPU_NMI BIT(21)
137 +#define AR934X_RESET_CPU_COLD BIT(20)
138 +#define AR934X_RESET_HOST_RESET_INT BIT(19)
139 +#define AR934X_RESET_PCIE_EP BIT(18)
140 +#define AR934X_RESET_UART1 BIT(17)
141 +#define AR934X_RESET_DDR BIT(16)
142 +#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
143 +#define AR934X_RESET_NANDF BIT(14)
144 +#define AR934X_RESET_GE1_MAC BIT(13)
145 +#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12)
146 #define AR934X_RESET_USB_PHY_ANALOG BIT(11)
147 +#define AR934X_RESET_HOST_DMA_INT BIT(10)
148 +#define AR934X_RESET_GE0_MAC BIT(9)
149 +#define AR934X_RESET_ETH_SWITCH BIT(8)
150 +#define AR934X_RESET_PCIE_PHY BIT(7)
151 +#define AR934X_RESET_PCIE BIT(6)
152 #define AR934X_RESET_USB_HOST BIT(5)
153 #define AR934X_RESET_USB_PHY BIT(4)
154 #define AR934X_RESET_USBSUS_OVERRIDE BIT(3)
155 +#define AR934X_RESET_LUT BIT(2)
156 +#define AR934X_RESET_MBOX BIT(1)
157 +#define AR934X_RESET_I2S BIT(0)
158
159 +#define QCA955X_RESET_HOST BIT(31)
160 +#define QCA955X_RESET_SLIC BIT(30)
161 +#define QCA955X_RESET_HDMA BIT(29)
162 +#define QCA955X_RESET_EXTERNAL BIT(28)
163 +#define QCA955X_RESET_RTC BIT(27)
164 +#define QCA955X_RESET_PCIE_EP_INT BIT(26)
165 +#define QCA955X_RESET_CHKSUM_ACC BIT(25)
166 +#define QCA955X_RESET_FULL_CHIP BIT(24)
167 +#define QCA955X_RESET_GE1_MDIO BIT(23)
168 +#define QCA955X_RESET_GE0_MDIO BIT(22)
169 +#define QCA955X_RESET_CPU_NMI BIT(21)
170 +#define QCA955X_RESET_CPU_COLD BIT(20)
171 +#define QCA955X_RESET_HOST_RESET_INT BIT(19)
172 +#define QCA955X_RESET_PCIE_EP BIT(18)
173 +#define QCA955X_RESET_UART1 BIT(17)
174 +#define QCA955X_RESET_DDR BIT(16)
175 +#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
176 +#define QCA955X_RESET_NANDF BIT(14)
177 +#define QCA955X_RESET_GE1_MAC BIT(13)
178 +#define QCA955X_RESET_SGMII_ANALOG BIT(12)
179 +#define QCA955X_RESET_USB_PHY_ANALOG BIT(11)
180 +#define QCA955X_RESET_HOST_DMA_INT BIT(10)
181 +#define QCA955X_RESET_GE0_MAC BIT(9)
182 +#define QCA955X_RESET_SGMII BIT(8)
183 +#define QCA955X_RESET_PCIE_PHY BIT(7)
184 +#define QCA955X_RESET_PCIE BIT(6)
185 +#define QCA955X_RESET_USB_HOST BIT(5)
186 +#define QCA955X_RESET_USB_PHY BIT(4)
187 +#define QCA955X_RESET_USBSUS_OVERRIDE BIT(3)
188 +#define QCA955X_RESET_LUT BIT(2)
189 +#define QCA955X_RESET_MBOX BIT(1)
190 +#define QCA955X_RESET_I2S BIT(0)
191 +
192 +#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
193 +#define AR933X_BOOTSTRAP_EEPBUSY BIT(4)
194 #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
195
196 #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
197 @@ -536,8 +633,22 @@
198 #define AR71XX_GPIO_REG_INT_ENABLE 0x24
199 #define AR71XX_GPIO_REG_FUNC 0x28
200
201 +#define AR934X_GPIO_REG_OUT_FUNC0 0x2c
202 +#define AR934X_GPIO_REG_OUT_FUNC1 0x30
203 +#define AR934X_GPIO_REG_OUT_FUNC2 0x34
204 +#define AR934X_GPIO_REG_OUT_FUNC3 0x38
205 +#define AR934X_GPIO_REG_OUT_FUNC4 0x3c
206 +#define AR934X_GPIO_REG_OUT_FUNC5 0x40
207 #define AR934X_GPIO_REG_FUNC 0x6c
208
209 +#define QCA955X_GPIO_REG_OUT_FUNC0 0x2c
210 +#define QCA955X_GPIO_REG_OUT_FUNC1 0x30
211 +#define QCA955X_GPIO_REG_OUT_FUNC2 0x34
212 +#define QCA955X_GPIO_REG_OUT_FUNC3 0x38
213 +#define QCA955X_GPIO_REG_OUT_FUNC4 0x3c
214 +#define QCA955X_GPIO_REG_OUT_FUNC5 0x40
215 +#define QCA955X_GPIO_REG_FUNC 0x6c
216 +
217 #define AR71XX_GPIO_COUNT 16
218 #define AR7240_GPIO_COUNT 18
219 #define AR7241_GPIO_COUNT 20
220 @@ -567,4 +678,235 @@
221 #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
222 #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
223
224 +#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
225 +#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)
226 +#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13)
227 +#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12)
228 +#define AR71XX_GPIO_FUNC_UART_EN BIT(8)
229 +#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4)
230 +#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0)
231 +
232 +#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19)
233 +#define AR724X_GPIO_FUNC_SPI_EN BIT(18)
234 +#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
235 +#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
236 +#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12)
237 +#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11)
238 +#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10)
239 +#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9)
240 +#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8)
241 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
242 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
243 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
244 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
245 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
246 +#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
247 +#define AR724X_GPIO_FUNC_UART_EN BIT(1)
248 +#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0)
249 +
250 +#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22)
251 +#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21)
252 +#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20)
253 +#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19)
254 +#define AR913X_GPIO_FUNC_I2S1_EN BIT(18)
255 +#define AR913X_GPIO_FUNC_I2S0_EN BIT(17)
256 +#define AR913X_GPIO_FUNC_SLIC_EN BIT(16)
257 +#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9)
258 +#define AR913X_GPIO_FUNC_UART_EN BIT(8)
259 +#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4)
260 +
261 +#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31)
262 +#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30)
263 +#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29)
264 +#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27)
265 +#define AR933X_GPIO_FUNC_I2SO_EN BIT(26)
266 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25)
267 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24)
268 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23)
269 +#define AR933X_GPIO_FUNC_SPI_EN BIT(18)
270 +#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
271 +#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
272 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
273 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
274 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
275 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
276 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
277 +#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
278 +#define AR933X_GPIO_FUNC_UART_EN BIT(1)
279 +#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0)
280 +
281 +#define AR934X_GPIO_FUNC_CLK_OBS7_EN BIT(9)
282 +#define AR934X_GPIO_FUNC_CLK_OBS6_EN BIT(8)
283 +#define AR934X_GPIO_FUNC_CLK_OBS5_EN BIT(7)
284 +#define AR934X_GPIO_FUNC_CLK_OBS4_EN BIT(6)
285 +#define AR934X_GPIO_FUNC_CLK_OBS3_EN BIT(5)
286 +#define AR934X_GPIO_FUNC_CLK_OBS2_EN BIT(4)
287 +#define AR934X_GPIO_FUNC_CLK_OBS1_EN BIT(3)
288 +#define AR934X_GPIO_FUNC_CLK_OBS0_EN BIT(2)
289 +#define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1)
290 +
291 +#define AR934X_GPIO_OUT_GPIO 0
292 +#define AR934X_GPIO_OUT_SPI_CS1 7
293 +#define AR934X_GPIO_OUT_LED_LINK0 41
294 +#define AR934X_GPIO_OUT_LED_LINK1 42
295 +#define AR934X_GPIO_OUT_LED_LINK2 43
296 +#define AR934X_GPIO_OUT_LED_LINK3 44
297 +#define AR934X_GPIO_OUT_LED_LINK4 45
298 +#define AR934X_GPIO_OUT_EXT_LNA0 46
299 +#define AR934X_GPIO_OUT_EXT_LNA1 47
300 +
301 +#define QCA955X_GPIO_FUNC_CLK_OBS7_EN BIT(9)
302 +#define QCA955X_GPIO_FUNC_CLK_OBS6_EN BIT(8)
303 +#define QCA955X_GPIO_FUNC_CLK_OBS5_EN BIT(7)
304 +#define QCA955X_GPIO_FUNC_CLK_OBS4_EN BIT(6)
305 +#define QCA955X_GPIO_FUNC_CLK_OBS3_EN BIT(5)
306 +#define QCA955X_GPIO_FUNC_CLK_OBS2_EN BIT(4)
307 +#define QCA955X_GPIO_FUNC_CLK_OBS1_EN BIT(3)
308 +#define QCA955X_GPIO_FUNC_JTAG_DISABLE BIT(1)
309 +
310 +#define QCA955X_GPIO_OUT_GPIO 0
311 +#define QCA955X_MII_EXT_MDI 1
312 +#define QCA955X_SLIC_DATA_OUT 3
313 +#define QCA955X_SLIC_PCM_FS 4
314 +#define QCA955X_SLIC_PCM_CLK 5
315 +#define QCA955X_SPI_CLK 8
316 +#define QCA955X_SPI_CS_0 9
317 +#define QCA955X_SPI_CS_1 10
318 +#define QCA955X_SPI_CS_2 11
319 +#define QCA955X_SPI_MISO 12
320 +#define QCA955X_I2S_CLK 13
321 +#define QCA955X_I2S_WS 14
322 +#define QCA955X_I2S_SD 15
323 +#define QCA955X_I2S_MCK 16
324 +#define QCA955X_SPDIF_OUT 17
325 +#define QCA955X_UART1_TD 18
326 +#define QCA955X_UART1_RTS 19
327 +#define QCA955X_UART1_RD 20
328 +#define QCA955X_UART1_CTS 21
329 +#define QCA955X_UART0_SOUT 22
330 +#define QCA955X_SPDIF2_OUT 23
331 +#define QCA955X_LED_SGMII_SPEED0 24
332 +#define QCA955X_LED_SGMII_SPEED1 25
333 +#define QCA955X_LED_SGMII_DUPLEX 26
334 +#define QCA955X_LED_SGMII_LINK_UP 27
335 +#define QCA955X_SGMII_SPEED0_INVERT 28
336 +#define QCA955X_SGMII_SPEED1_INVERT 29
337 +#define QCA955X_SGMII_DUPLEX_INVERT 30
338 +#define QCA955X_SGMII_LINK_UP_INVERT 31
339 +#define QCA955X_GE1_MII_MDO 32
340 +#define QCA955X_GE1_MII_MDC 33
341 +#define QCA955X_SWCOM2 38
342 +#define QCA955X_SWCOM3 39
343 +#define QCA955X_MAC2_GPIO 40
344 +#define QCA955X_MAC3_GPIO 41
345 +#define QCA955X_ATT_LED 42
346 +#define QCA955X_PWR_LED 43
347 +#define QCA955X_TX_FRAME 44
348 +#define QCA955X_RX_CLEAR_EXTERNAL 45
349 +#define QCA955X_LED_NETWORK_EN 46
350 +#define QCA955X_LED_POWER_EN 47
351 +#define QCA955X_WMAC_GLUE_WOW 68
352 +#define QCA955X_RX_CLEAR_EXTENSION 70
353 +#define QCA955X_CP_NAND_CS1 73
354 +#define QCA955X_USB_SUSPEND 74
355 +#define QCA955X_ETH_TX_ERR 75
356 +#define QCA955X_DDR_DQ_OE 76
357 +#define QCA955X_CLKREQ_N_EP 77
358 +#define QCA955X_CLKREQ_N_RC 78
359 +#define QCA955X_CLK_OBS0 79
360 +#define QCA955X_CLK_OBS1 80
361 +#define QCA955X_CLK_OBS2 81
362 +#define QCA955X_CLK_OBS3 82
363 +#define QCA955X_CLK_OBS4 83
364 +#define QCA955X_CLK_OBS5 84
365 +
366 +/*
367 + * MII_CTRL block
368 + */
369 +#define AR71XX_MII_REG_MII0_CTRL 0x00
370 +#define AR71XX_MII_REG_MII1_CTRL 0x04
371 +
372 +#define AR71XX_MII_CTRL_IF_MASK 3
373 +#define AR71XX_MII_CTRL_SPEED_SHIFT 4
374 +#define AR71XX_MII_CTRL_SPEED_MASK 3
375 +#define AR71XX_MII_CTRL_SPEED_10 0
376 +#define AR71XX_MII_CTRL_SPEED_100 1
377 +#define AR71XX_MII_CTRL_SPEED_1000 2
378 +
379 +#define AR71XX_MII0_CTRL_IF_GMII 0
380 +#define AR71XX_MII0_CTRL_IF_MII 1
381 +#define AR71XX_MII0_CTRL_IF_RGMII 2
382 +#define AR71XX_MII0_CTRL_IF_RMII 3
383 +
384 +#define AR71XX_MII1_CTRL_IF_RGMII 0
385 +#define AR71XX_MII1_CTRL_IF_RMII 1
386 +
387 +/*
388 + * AR933X GMAC interface
389 + */
390 +#define AR933X_GMAC_REG_ETH_CFG 0x00
391 +
392 +#define AR933X_ETH_CFG_RGMII_GE0 BIT(0)
393 +#define AR933X_ETH_CFG_MII_GE0 BIT(1)
394 +#define AR933X_ETH_CFG_GMII_GE0 BIT(2)
395 +#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3)
396 +#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4)
397 +#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5)
398 +#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7)
399 +#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8)
400 +#define AR933X_ETH_CFG_RMII_GE0 BIT(9)
401 +#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0
402 +#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10)
403 +
404 +/*
405 + * AR934X GMAC Interface
406 + */
407 +#define AR934X_GMAC_REG_ETH_CFG 0x00
408 +
409 +#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0)
410 +#define AR934X_ETH_CFG_MII_GMAC0 BIT(1)
411 +#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2)
412 +#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3)
413 +#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4)
414 +#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5)
415 +#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6)
416 +#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7)
417 +#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9)
418 +#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10)
419 +#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11)
420 +#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
421 +#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
422 +#define AR934X_ETH_CFG_RXD_DELAY BIT(14)
423 +#define AR934X_ETH_CFG_RXD_DELAY_MASK 0x3
424 +#define AR934X_ETH_CFG_RXD_DELAY_SHIFT 14
425 +#define AR934X_ETH_CFG_RDV_DELAY BIT(16)
426 +#define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3
427 +#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16
428 +
429 +/*
430 + * QCA955X GMAC Interface
431 + */
432 +
433 +#define QCA955X_GMAC_REG_ETH_CFG 0x00
434 +
435 +#define QCA955X_ETH_CFG_RGMII_EN BIT(0)
436 +#define QCA955X_ETH_CFG_MII_GE0 BIT(1)
437 +#define QCA955X_ETH_CFG_GMII_GE0 BIT(2)
438 +#define QCA955X_ETH_CFG_MII_GE0_MASTER BIT(3)
439 +#define QCA955X_ETH_CFG_MII_GE0_SLAVE BIT(4)
440 +#define QCA955X_ETH_CFG_GE0_ERR_EN BIT(5)
441 +#define QCA955X_ETH_CFG_GE0_SGMII BIT(6)
442 +#define QCA955X_ETH_CFG_RMII_GE0 BIT(10)
443 +#define QCA955X_ETH_CFG_MII_CNTL_SPEED BIT(11)
444 +#define QCA955X_ETH_CFG_RMII_GE0_MASTER BIT(12)
445 +#define QCA955X_ETH_CFG_RXD_DELAY_MASK 0x3
446 +#define QCA955X_ETH_CFG_RXD_DELAY_SHIFT 14
447 +#define QCA955X_ETH_CFG_RDV_DELAY BIT(16)
448 +#define QCA955X_ETH_CFG_RDV_DELAY_MASK 0x3
449 +#define QCA955X_ETH_CFG_RDV_DELAY_SHIFT 16
450 +#define QCA955X_ETH_CFG_TXD_DELAY_MASK 0x3
451 +#define QCA955X_ETH_CFG_TXD_DELAY_SHIFT 18
452 +#define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3
453 +#define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20
454 +
455 #endif /* __ASM_MACH_AR71XX_REGS_H */