5cfb4e78d73edb34839eaa2c20216ced80f4cccf
[openwrt/openwrt.git] / target / linux / ar71xx / patches-4.4 / 620-MIPS-ath79-add-support-for-QCA953x-SoC.patch
1 From 5300a7cd7ed2f88488ddba62947b9c6bb9663777 Mon Sep 17 00:00:00 2001
2 Message-Id: <5300a7cd7ed2f88488ddba62947b9c6bb9663777.1396122227.git.mschiffer@universe-factory.net>
3 From: Matthias Schiffer <mschiffer@universe-factory.net>
4 Date: Sat, 29 Mar 2014 20:26:08 +0100
5 Subject: [PATCH 1/2] MIPS: ath79: add support for QCA953x SoC
6
7 Note that the clock calculation looks very similar to the QCA955x, but the
8 meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
9 ---
10 arch/mips/ath79/Kconfig | 6 +-
11 arch/mips/ath79/clock.c | 78 ++++++++++++++++++++++++++
12 arch/mips/ath79/common.c | 4 ++
13 arch/mips/ath79/dev-common.c | 1 +
14 arch/mips/ath79/dev-wmac.c | 20 +++++++
15 arch/mips/ath79/early_printk.c | 1 +
16 arch/mips/ath79/gpio.c | 4 +-
17 arch/mips/ath79/irq.c | 4 ++
18 arch/mips/ath79/setup.c | 8 ++-
19 arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 48 ++++++++++++++++
20 arch/mips/include/asm/mach-ath79/ath79.h | 11 ++++
21 11 files changed, 182 insertions(+), 3 deletions(-)
22
23 --- a/arch/mips/ath79/Kconfig
24 +++ b/arch/mips/ath79/Kconfig
25 @@ -116,6 +116,10 @@ config SOC_AR934X
26 select PCI_AR724X if PCI
27 def_bool n
28
29 +config SOC_QCA953X
30 + select USB_ARCH_HAS_EHCI
31 + def_bool n
32 +
33 config SOC_QCA955X
34 select HW_HAS_PCI
35 select PCI_AR724X if PCI
36 @@ -155,7 +159,7 @@ config ATH79_DEV_USB
37 def_bool n
38
39 config ATH79_DEV_WMAC
40 - depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)
41 + depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X)
42 def_bool n
43
44 config ATH79_NVRAM
45 --- a/arch/mips/ath79/clock.c
46 +++ b/arch/mips/ath79/clock.c
47 @@ -354,6 +354,91 @@ static void __init ar934x_clocks_init(vo
48 iounmap(dpll_base);
49 }
50
51 +static void __init qca953x_clocks_init(void)
52 +{
53 + unsigned long ref_rate;
54 + unsigned long cpu_rate;
55 + unsigned long ddr_rate;
56 + unsigned long ahb_rate;
57 + u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
58 + u32 cpu_pll, ddr_pll;
59 + u32 bootstrap;
60 +
61 + bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
62 + if (bootstrap & QCA953X_BOOTSTRAP_REF_CLK_40)
63 + ref_rate = 40 * 1000 * 1000;
64 + else
65 + ref_rate = 25 * 1000 * 1000;
66 +
67 + pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
68 + out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
69 + QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
70 + ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
71 + QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
72 + nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) &
73 + QCA953X_PLL_CPU_CONFIG_NINT_MASK;
74 + frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
75 + QCA953X_PLL_CPU_CONFIG_NFRAC_MASK;
76 +
77 + cpu_pll = nint * ref_rate / ref_div;
78 + cpu_pll += frac * (ref_rate >> 6) / ref_div;
79 + cpu_pll /= (1 << out_div);
80 +
81 + pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG);
82 + out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
83 + QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
84 + ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
85 + QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
86 + nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) &
87 + QCA953X_PLL_DDR_CONFIG_NINT_MASK;
88 + frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
89 + QCA953X_PLL_DDR_CONFIG_NFRAC_MASK;
90 +
91 + ddr_pll = nint * ref_rate / ref_div;
92 + ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
93 + ddr_pll /= (1 << out_div);
94 +
95 + clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG);
96 +
97 + postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
98 + QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
99 +
100 + if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
101 + cpu_rate = ref_rate;
102 + else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
103 + cpu_rate = cpu_pll / (postdiv + 1);
104 + else
105 + cpu_rate = ddr_pll / (postdiv + 1);
106 +
107 + postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
108 + QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
109 +
110 + if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
111 + ddr_rate = ref_rate;
112 + else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
113 + ddr_rate = ddr_pll / (postdiv + 1);
114 + else
115 + ddr_rate = cpu_pll / (postdiv + 1);
116 +
117 + postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
118 + QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
119 +
120 + if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
121 + ahb_rate = ref_rate;
122 + else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
123 + ahb_rate = ddr_pll / (postdiv + 1);
124 + else
125 + ahb_rate = cpu_pll / (postdiv + 1);
126 +
127 + ath79_add_sys_clkdev("ref", ref_rate);
128 + ath79_add_sys_clkdev("cpu", cpu_rate);
129 + ath79_add_sys_clkdev("ddr", ddr_rate);
130 + ath79_add_sys_clkdev("ahb", ahb_rate);
131 +
132 + clk_add_alias("wdt", NULL, "ref", NULL);
133 + clk_add_alias("uart", NULL, "ref", NULL);
134 +}
135 +
136 static void __init qca955x_clocks_init(void)
137 {
138 unsigned long ref_rate;
139 @@ -451,6 +536,8 @@ void __init ath79_clocks_init(void)
140 ar933x_clocks_init();
141 else if (soc_is_ar934x())
142 ar934x_clocks_init();
143 + else if (soc_is_qca953x())
144 + qca953x_clocks_init();
145 else if (soc_is_qca955x())
146 qca955x_clocks_init();
147 else
148 --- a/arch/mips/ath79/common.c
149 +++ b/arch/mips/ath79/common.c
150 @@ -103,6 +103,8 @@ void ath79_device_reset_set(u32 mask)
151 reg = AR933X_RESET_REG_RESET_MODULE;
152 else if (soc_is_ar934x())
153 reg = AR934X_RESET_REG_RESET_MODULE;
154 + else if (soc_is_qca953x())
155 + reg = QCA953X_RESET_REG_RESET_MODULE;
156 else if (soc_is_qca955x())
157 reg = QCA955X_RESET_REG_RESET_MODULE;
158 else
159 @@ -131,6 +133,8 @@ void ath79_device_reset_clear(u32 mask)
160 reg = AR933X_RESET_REG_RESET_MODULE;
161 else if (soc_is_ar934x())
162 reg = AR934X_RESET_REG_RESET_MODULE;
163 + else if (soc_is_qca953x())
164 + reg = QCA953X_RESET_REG_RESET_MODULE;
165 else if (soc_is_qca955x())
166 reg = QCA955X_RESET_REG_RESET_MODULE;
167 else
168 --- a/arch/mips/ath79/dev-common.c
169 +++ b/arch/mips/ath79/dev-common.c
170 @@ -94,6 +94,7 @@ void __init ath79_register_uart(void)
171 soc_is_ar724x() ||
172 soc_is_ar913x() ||
173 soc_is_ar934x() ||
174 + soc_is_qca953x() ||
175 soc_is_qca955x()) {
176 ath79_uart_data[0].uartclk = uart_clk_rate;
177 platform_device_register(&ath79_uart_device);
178 @@ -157,6 +158,9 @@ void __init ath79_gpio_init(void)
179 } else if (soc_is_ar934x()) {
180 ath79_gpio_pdata.ngpios = AR934X_GPIO_COUNT;
181 ath79_gpio_pdata.oe_inverted = 1;
182 + } else if (soc_is_qca953x()) {
183 + ath79_gpio_pdata.ngpios = QCA953X_GPIO_COUNT;
184 + ath79_gpio_pdata.oe_inverted = 1;
185 } else if (soc_is_qca955x()) {
186 ath79_gpio_pdata.ngpios = QCA955X_GPIO_COUNT;
187 ath79_gpio_pdata.oe_inverted = 1;
188 --- a/arch/mips/ath79/dev-usb.c
189 +++ b/arch/mips/ath79/dev-usb.c
190 @@ -236,6 +236,30 @@ static void __init ar934x_usb_setup(void
191 &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
192 }
193
194 +static void __init qca953x_usb_setup(void)
195 +{
196 + u32 bootstrap;
197 +
198 + bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
199 +
200 + ath79_device_reset_set(QCA953X_RESET_USBSUS_OVERRIDE);
201 + udelay(1000);
202 +
203 + ath79_device_reset_clear(QCA953X_RESET_USB_PHY);
204 + udelay(1000);
205 +
206 + ath79_device_reset_clear(QCA953X_RESET_USB_PHY_ANALOG);
207 + udelay(1000);
208 +
209 + ath79_device_reset_clear(QCA953X_RESET_USB_HOST);
210 + udelay(1000);
211 +
212 + ath79_usb_register("ehci-platform", -1,
213 + QCA953X_EHCI_BASE, QCA953X_EHCI_SIZE,
214 + ATH79_CPU_IRQ(3),
215 + &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
216 +}
217 +
218 static void qca955x_usb_reset_notifier(struct platform_device *pdev)
219 {
220 u32 base;
221 @@ -286,6 +310,8 @@ void __init ath79_register_usb(void)
222 ar933x_usb_setup();
223 else if (soc_is_ar934x())
224 ar934x_usb_setup();
225 + else if (soc_is_qca953x())
226 + qca953x_usb_setup();
227 else if (soc_is_qca955x())
228 qca955x_usb_setup();
229 else
230 --- a/arch/mips/ath79/dev-wmac.c
231 +++ b/arch/mips/ath79/dev-wmac.c
232 @@ -100,7 +100,7 @@ static int ar933x_wmac_reset(void)
233 return -ETIMEDOUT;
234 }
235
236 -static int ar933x_r1_get_wmac_revision(void)
237 +static int ar93xx_get_soc_revision(void)
238 {
239 return ath79_soc_rev;
240 }
241 @@ -125,7 +125,7 @@ static void __init ar933x_wmac_setup(voi
242 ath79_wmac_data.is_clk_25mhz = true;
243
244 if (ath79_soc_rev == 1)
245 - ath79_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision;
246 + ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
247
248 ath79_wmac_data.external_reset = ar933x_wmac_reset;
249 }
250 @@ -150,6 +150,26 @@ static void ar934x_wmac_setup(void)
251 ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
252 }
253
254 +static void qca953x_wmac_setup(void)
255 +{
256 + u32 t;
257 +
258 + ath79_wmac_device.name = "qca953x_wmac";
259 +
260 + ath79_wmac_resources[0].start = QCA953X_WMAC_BASE;
261 + ath79_wmac_resources[0].end = QCA953X_WMAC_BASE + QCA953X_WMAC_SIZE - 1;
262 + ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
263 + ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1);
264 +
265 + t = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
266 + if (t & QCA953X_BOOTSTRAP_REF_CLK_40)
267 + ath79_wmac_data.is_clk_25mhz = false;
268 + else
269 + ath79_wmac_data.is_clk_25mhz = true;
270 +
271 + ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
272 +}
273 +
274 static void qca955x_wmac_setup(void)
275 {
276 u32 t;
277 @@ -379,6 +399,8 @@ void __init ath79_register_wmac(u8 *cal_
278 ar933x_wmac_setup();
279 else if (soc_is_ar934x())
280 ar934x_wmac_setup();
281 + else if (soc_is_qca953x())
282 + qca953x_wmac_setup();
283 else if (soc_is_qca955x())
284 qca955x_wmac_setup();
285 else
286 --- a/arch/mips/ath79/early_printk.c
287 +++ b/arch/mips/ath79/early_printk.c
288 @@ -116,6 +116,8 @@ static void prom_putchar_init(void)
289 case REV_ID_MAJOR_AR9341:
290 case REV_ID_MAJOR_AR9342:
291 case REV_ID_MAJOR_AR9344:
292 + case REV_ID_MAJOR_QCA9533:
293 + case REV_ID_MAJOR_QCA9533_V2:
294 case REV_ID_MAJOR_QCA9556:
295 case REV_ID_MAJOR_QCA9558:
296 _prom_putchar = prom_putchar_ar71xx;
297 --- a/arch/mips/ath79/gpio.c
298 +++ b/arch/mips/ath79/gpio.c
299 @@ -31,7 +31,7 @@ static void __iomem *ath79_gpio_get_func
300 soc_is_ar913x() ||
301 soc_is_ar933x())
302 reg = AR71XX_GPIO_REG_FUNC;
303 - else if (soc_is_ar934x())
304 + else if (soc_is_ar934x() || soc_is_qca953x())
305 reg = AR934X_GPIO_REG_FUNC;
306 else
307 BUG();
308 @@ -64,7 +64,7 @@ void __init ath79_gpio_output_select(uns
309 unsigned int reg;
310 u32 t, s;
311
312 - BUG_ON(!soc_is_ar934x());
313 + BUG_ON(!soc_is_ar934x() && !soc_is_qca953x());
314
315 if (gpio >= AR934X_GPIO_COUNT)
316 return;
317 --- a/arch/mips/ath79/irq.c
318 +++ b/arch/mips/ath79/irq.c
319 @@ -105,6 +105,7 @@ static void __init ath79_misc_irq_init(v
320 else if (soc_is_ar724x() ||
321 soc_is_ar933x() ||
322 soc_is_ar934x() ||
323 + soc_is_qca953x() ||
324 soc_is_qca955x())
325 ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
326 else
327 @@ -148,6 +149,34 @@ static void ar934x_ip2_irq_init(void)
328 irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
329 }
330
331 +static void qca953x_ip2_irq_dispatch(struct irq_desc *desc)
332 +{
333 + u32 status;
334 +
335 + status = ath79_reset_rr(QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS);
336 +
337 + if (status & QCA953X_PCIE_WMAC_INT_PCIE_ALL) {
338 + ath79_ddr_wb_flush(3);
339 + generic_handle_irq(ATH79_IP2_IRQ(0));
340 + } else if (status & QCA953X_PCIE_WMAC_INT_WMAC_ALL) {
341 + ath79_ddr_wb_flush(4);
342 + generic_handle_irq(ATH79_IP2_IRQ(1));
343 + } else {
344 + spurious_interrupt();
345 + }
346 +}
347 +
348 +static void qca953x_irq_init(void)
349 +{
350 + int i;
351 +
352 + for (i = ATH79_IP2_IRQ_BASE;
353 + i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
354 + irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
355 +
356 + irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch);
357 +}
358 +
359 static void qca955x_ip2_irq_dispatch(struct irq_desc *desc)
360 {
361 u32 status;
362 @@ -362,7 +391,7 @@ void __init arch_init_irq(void)
363 soc_is_ar913x() || soc_is_ar933x()) {
364 irq_wb_chan[2] = 3;
365 irq_wb_chan[3] = 2;
366 - } else if (soc_is_ar934x()) {
367 + } else if (soc_is_ar934x() || soc_is_qca953x()) {
368 irq_wb_chan[3] = 2;
369 }
370
371 @@ -371,6 +400,8 @@ void __init arch_init_irq(void)
372
373 if (soc_is_ar934x())
374 ar934x_ip2_irq_init();
375 + else if (soc_is_qca953x())
376 + qca953x_irq_init();
377 else if (soc_is_qca955x())
378 qca955x_irq_init();
379 }
380 --- a/arch/mips/ath79/setup.c
381 +++ b/arch/mips/ath79/setup.c
382 @@ -64,6 +64,7 @@ static void __init ath79_detect_sys_type
383 u32 major;
384 u32 minor;
385 u32 rev = 0;
386 + u32 ver = 1;
387
388 id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
389 major = id & REV_ID_MAJOR_MASK;
390 @@ -156,6 +157,17 @@ static void __init ath79_detect_sys_type
391 rev = id & AR934X_REV_ID_REVISION_MASK;
392 break;
393
394 + case REV_ID_MAJOR_QCA9533_V2:
395 + ver = 2;
396 + ath79_soc_rev = 2;
397 + /* drop through */
398 +
399 + case REV_ID_MAJOR_QCA9533:
400 + ath79_soc = ATH79_SOC_QCA9533;
401 + chip = "9533";
402 + rev = id & QCA953X_REV_ID_REVISION_MASK;
403 + break;
404 +
405 case REV_ID_MAJOR_QCA9556:
406 ath79_soc = ATH79_SOC_QCA9556;
407 chip = "9556";
408 @@ -172,11 +184,12 @@ static void __init ath79_detect_sys_type
409 panic("ath79: unknown SoC, id:0x%08x", id);
410 }
411
412 - ath79_soc_rev = rev;
413 + if (ver == 1)
414 + ath79_soc_rev = rev;
415
416 - if (soc_is_qca955x())
417 - sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
418 - chip, rev);
419 + if (soc_is_qca953x() || soc_is_qca955x())
420 + sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
421 + chip, ver, rev);
422 else
423 sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
424 pr_info("SoC: %s\n", ath79_sys_type);
425 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
426 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
427 @@ -105,6 +105,21 @@
428 #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
429 #define AR934X_SRIF_SIZE 0x1000
430
431 +#define QCA953X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
432 +#define QCA953X_GMAC_SIZE 0x14
433 +#define QCA953X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
434 +#define QCA953X_WMAC_SIZE 0x20000
435 +#define QCA953X_EHCI_BASE 0x1b000000
436 +#define QCA953X_EHCI_SIZE 0x200
437 +#define QCA953X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
438 +#define QCA953X_SRIF_SIZE 0x1000
439 +
440 +#define QCA953X_PCI_CFG_BASE0 0x14000000
441 +#define QCA953X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000)
442 +#define QCA953X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000)
443 +#define QCA953X_PCI_MEM_BASE0 0x10000000
444 +#define QCA953X_PCI_MEM_SIZE 0x02000000
445 +
446 #define QCA955X_PCI_MEM_BASE0 0x10000000
447 #define QCA955X_PCI_MEM_BASE1 0x12000000
448 #define QCA955X_PCI_MEM_SIZE 0x02000000
449 @@ -180,6 +195,12 @@
450 #define AR934X_OTP_INTF3_ADDRESS 0x3100c
451 #define AR934X_OTP_PGENB_SETUP_HOLD_TIME_ADDRESS 0x31034
452
453 +#define QCA953X_DDR_REG_FLUSH_GE0 0x9c
454 +#define QCA953X_DDR_REG_FLUSH_GE1 0xa0
455 +#define QCA953X_DDR_REG_FLUSH_USB 0xa4
456 +#define QCA953X_DDR_REG_FLUSH_PCIE 0xa8
457 +#define QCA953X_DDR_REG_FLUSH_WMAC 0xac
458 +
459 /*
460 * PLL block
461 */
462 @@ -289,6 +310,44 @@
463
464 #define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6)
465
466 +#define QCA953X_PLL_CPU_CONFIG_REG 0x00
467 +#define QCA953X_PLL_DDR_CONFIG_REG 0x04
468 +#define QCA953X_PLL_CLK_CTRL_REG 0x08
469 +#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24
470 +#define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c
471 +#define QCA953X_PLL_ETH_SGMII_CONTROL_REG 0x48
472 +
473 +#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
474 +#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
475 +#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6
476 +#define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f
477 +#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
478 +#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
479 +#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
480 +#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
481 +
482 +#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
483 +#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
484 +#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10
485 +#define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f
486 +#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
487 +#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
488 +#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
489 +#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
490 +
491 +#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
492 +#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
493 +#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
494 +#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
495 +#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
496 +#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
497 +#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
498 +#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
499 +#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
500 +#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
501 +#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
502 +#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
503 +
504 #define QCA955X_PLL_CPU_CONFIG_REG 0x00
505 #define QCA955X_PLL_DDR_CONFIG_REG 0x04
506 #define QCA955X_PLL_CLK_CTRL_REG 0x08
507 @@ -365,6 +424,10 @@
508 #define AR934X_RESET_REG_BOOTSTRAP 0xb0
509 #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
510
511 +#define QCA953X_RESET_REG_RESET_MODULE 0x1c
512 +#define QCA953X_RESET_REG_BOOTSTRAP 0xb0
513 +#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
514 +
515 #define QCA955X_RESET_REG_RESET_MODULE 0x1c
516 #define QCA955X_RESET_REG_BOOTSTRAP 0xb0
517 #define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
518 @@ -460,6 +523,27 @@
519 #define AR934X_RESET_MBOX BIT(1)
520 #define AR934X_RESET_I2S BIT(0)
521
522 +#define QCA953X_RESET_USB_EXT_PWR BIT(29)
523 +#define QCA953X_RESET_EXTERNAL BIT(28)
524 +#define QCA953X_RESET_RTC BIT(27)
525 +#define QCA953X_RESET_FULL_CHIP BIT(24)
526 +#define QCA953X_RESET_GE1_MDIO BIT(23)
527 +#define QCA953X_RESET_GE0_MDIO BIT(22)
528 +#define QCA953X_RESET_CPU_NMI BIT(21)
529 +#define QCA953X_RESET_CPU_COLD BIT(20)
530 +#define QCA953X_RESET_DDR BIT(16)
531 +#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
532 +#define QCA953X_RESET_GE1_MAC BIT(13)
533 +#define QCA953X_RESET_ETH_SWITCH_ANALOG BIT(12)
534 +#define QCA953X_RESET_USB_PHY_ANALOG BIT(11)
535 +#define QCA953X_RESET_GE0_MAC BIT(9)
536 +#define QCA953X_RESET_ETH_SWITCH BIT(8)
537 +#define QCA953X_RESET_PCIE_PHY BIT(7)
538 +#define QCA953X_RESET_PCIE BIT(6)
539 +#define QCA953X_RESET_USB_HOST BIT(5)
540 +#define QCA953X_RESET_USB_PHY BIT(4)
541 +#define QCA953X_RESET_USBSUS_OVERRIDE BIT(3)
542 +
543 #define QCA955X_RESET_HOST BIT(31)
544 #define QCA955X_RESET_SLIC BIT(30)
545 #define QCA955X_RESET_HDMA BIT(29)
546 @@ -513,6 +597,13 @@
547 #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
548 #define AR934X_BOOTSTRAP_DDR1 BIT(0)
549
550 +#define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12)
551 +#define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11)
552 +#define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5)
553 +#define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4)
554 +#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
555 +#define QCA953X_BOOTSTRAP_DDR1 BIT(0)
556 +
557 #define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
558
559 #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
560 @@ -533,6 +624,24 @@
561 AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
562 AR934X_PCIE_WMAC_INT_PCIE_RC3)
563
564 +#define QCA953X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
565 +#define QCA953X_PCIE_WMAC_INT_WMAC_TX BIT(1)
566 +#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
567 +#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP BIT(3)
568 +#define QCA953X_PCIE_WMAC_INT_PCIE_RC BIT(4)
569 +#define QCA953X_PCIE_WMAC_INT_PCIE_RC0 BIT(5)
570 +#define QCA953X_PCIE_WMAC_INT_PCIE_RC1 BIT(6)
571 +#define QCA953X_PCIE_WMAC_INT_PCIE_RC2 BIT(7)
572 +#define QCA953X_PCIE_WMAC_INT_PCIE_RC3 BIT(8)
573 +#define QCA953X_PCIE_WMAC_INT_WMAC_ALL \
574 + (QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \
575 + QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP)
576 +
577 +#define QCA953X_PCIE_WMAC_INT_PCIE_ALL \
578 + (QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \
579 + QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \
580 + QCA953X_PCIE_WMAC_INT_PCIE_RC3)
581 +
582 #define QCA955X_EXT_INT_WMAC_MISC BIT(0)
583 #define QCA955X_EXT_INT_WMAC_TX BIT(1)
584 #define QCA955X_EXT_INT_WMAC_RXLP BIT(2)
585 @@ -575,6 +684,8 @@
586 #define REV_ID_MAJOR_AR9341 0x0120
587 #define REV_ID_MAJOR_AR9342 0x1120
588 #define REV_ID_MAJOR_AR9344 0x2120
589 +#define REV_ID_MAJOR_QCA9533 0x0140
590 +#define REV_ID_MAJOR_QCA9533_V2 0x0160
591 #define REV_ID_MAJOR_QCA9556 0x0130
592 #define REV_ID_MAJOR_QCA9558 0x1130
593
594 @@ -597,6 +708,8 @@
595
596 #define AR934X_REV_ID_REVISION_MASK 0xf
597
598 +#define QCA953X_REV_ID_REVISION_MASK 0xf
599 +
600 #define QCA955X_REV_ID_REVISION_MASK 0xf
601
602 /*
603 @@ -644,6 +757,25 @@
604 #define AR934X_GPIO_REG_OUT_FUNC5 0x40
605 #define AR934X_GPIO_REG_FUNC 0x6c
606
607 +#define QCA953X_GPIO_REG_OUT_FUNC0 0x2c
608 +#define QCA953X_GPIO_REG_OUT_FUNC1 0x30
609 +#define QCA953X_GPIO_REG_OUT_FUNC2 0x34
610 +#define QCA953X_GPIO_REG_OUT_FUNC3 0x38
611 +#define QCA953X_GPIO_REG_OUT_FUNC4 0x3c
612 +#define QCA953X_GPIO_REG_IN_ENABLE0 0x44
613 +#define QCA953X_GPIO_REG_FUNC 0x6c
614 +
615 +#define QCA953X_GPIO_OUT_MUX_SPI_CS1 10
616 +#define QCA953X_GPIO_OUT_MUX_SPI_CS2 11
617 +#define QCA953X_GPIO_OUT_MUX_SPI_CS0 9
618 +#define QCA953X_GPIO_OUT_MUX_SPI_CLK 8
619 +#define QCA953X_GPIO_OUT_MUX_SPI_MOSI 12
620 +#define QCA953X_GPIO_OUT_MUX_LED_LINK1 41
621 +#define QCA953X_GPIO_OUT_MUX_LED_LINK2 42
622 +#define QCA953X_GPIO_OUT_MUX_LED_LINK3 43
623 +#define QCA953X_GPIO_OUT_MUX_LED_LINK4 44
624 +#define QCA953X_GPIO_OUT_MUX_LED_LINK5 45
625 +
626 #define QCA955X_GPIO_REG_OUT_FUNC0 0x2c
627 #define QCA955X_GPIO_REG_OUT_FUNC1 0x30
628 #define QCA955X_GPIO_REG_OUT_FUNC2 0x34
629 @@ -658,6 +790,7 @@
630 #define AR913X_GPIO_COUNT 22
631 #define AR933X_GPIO_COUNT 30
632 #define AR934X_GPIO_COUNT 23
633 +#define QCA953X_GPIO_COUNT 18
634 #define QCA955X_GPIO_COUNT 24
635
636 /*
637 @@ -681,6 +814,24 @@
638 #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
639 #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
640
641 +#define QCA953X_SRIF_CPU_DPLL1_REG 0x1c0
642 +#define QCA953X_SRIF_CPU_DPLL2_REG 0x1c4
643 +#define QCA953X_SRIF_CPU_DPLL3_REG 0x1c8
644 +
645 +#define QCA953X_SRIF_DDR_DPLL1_REG 0x240
646 +#define QCA953X_SRIF_DDR_DPLL2_REG 0x244
647 +#define QCA953X_SRIF_DDR_DPLL3_REG 0x248
648 +
649 +#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT 27
650 +#define QCA953X_SRIF_DPLL1_REFDIV_MASK 0x1f
651 +#define QCA953X_SRIF_DPLL1_NINT_SHIFT 18
652 +#define QCA953X_SRIF_DPLL1_NINT_MASK 0x1ff
653 +#define QCA953X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff
654 +
655 +#define QCA953X_SRIF_DPLL2_LOCAL_PLL BIT(30)
656 +#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT 13
657 +#define QCA953X_SRIF_DPLL2_OUTDIV_MASK 0x7
658 +
659 #define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
660 #define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)
661 #define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13)
662 @@ -887,6 +1038,16 @@
663 #define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16
664
665 /*
666 + * QCA953X GMAC Interface
667 + */
668 +#define QCA953X_GMAC_REG_ETH_CFG 0x00
669 +
670 +#define QCA953X_ETH_CFG_SW_ONLY_MODE BIT(6)
671 +#define QCA953X_ETH_CFG_SW_PHY_SWAP BIT(7)
672 +#define QCA953X_ETH_CFG_SW_APB_ACCESS BIT(9)
673 +#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
674 +
675 +/*
676 * QCA955X GMAC Interface
677 */
678
679 --- a/arch/mips/include/asm/mach-ath79/ath79.h
680 +++ b/arch/mips/include/asm/mach-ath79/ath79.h
681 @@ -32,6 +32,7 @@ enum ath79_soc_type {
682 ATH79_SOC_AR9341,
683 ATH79_SOC_AR9342,
684 ATH79_SOC_AR9344,
685 + ATH79_SOC_QCA9533,
686 ATH79_SOC_QCA9556,
687 ATH79_SOC_QCA9558,
688 };
689 @@ -100,6 +101,16 @@ static inline int soc_is_ar934x(void)
690 return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
691 }
692
693 +static inline int soc_is_qca9533(void)
694 +{
695 + return ath79_soc == ATH79_SOC_QCA9533;
696 +}
697 +
698 +static inline int soc_is_qca953x(void)
699 +{
700 + return soc_is_qca9533();
701 +}
702 +
703 static inline int soc_is_qca9556(void)
704 {
705 return ath79_soc == ATH79_SOC_QCA9556;