a381851ccfb5500715e38ac542c916165eed93dc
[openwrt/openwrt.git] / target / linux / ar71xx / patches-4.4 / 621-MIPS-ath79-add-support-for-QCA956x-SoC.patch
1 --- a/arch/mips/ath79/Kconfig
2 +++ b/arch/mips/ath79/Kconfig
3 @@ -125,6 +125,12 @@ config SOC_QCA955X
4 select PCI_AR724X if PCI
5 def_bool n
6
7 +config SOC_QCA956X
8 + select USB_ARCH_HAS_EHCI
9 + select HW_HAS_PCI
10 + select PCI_AR724X if PCI
11 + def_bool n
12 +
13 config ATH79_DEV_M25P80
14 select ATH79_DEV_SPI
15 def_bool n
16 @@ -159,7 +165,7 @@ config ATH79_DEV_USB
17 def_bool n
18
19 config ATH79_DEV_WMAC
20 - depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X)
21 + depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X || SOC_QCA956X)
22 def_bool n
23
24 config ATH79_NVRAM
25 --- a/arch/mips/ath79/clock.c
26 +++ b/arch/mips/ath79/clock.c
27 @@ -524,6 +524,100 @@ static void __init qca955x_clocks_init(v
28 clk_add_alias("uart", NULL, "ref", NULL);
29 }
30
31 +static void __init qca956x_clocks_init(void)
32 +{
33 + unsigned long ref_rate;
34 + unsigned long cpu_rate;
35 + unsigned long ddr_rate;
36 + unsigned long ahb_rate;
37 + u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv;
38 + u32 cpu_pll, ddr_pll;
39 + u32 bootstrap;
40 +
41 + bootstrap = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
42 + if (bootstrap & QCA956X_BOOTSTRAP_REF_CLK_40)
43 + ref_rate = 40 * 1000 * 1000;
44 + else
45 + ref_rate = 25 * 1000 * 1000;
46 +
47 + pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG);
48 + out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
49 + QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
50 + ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
51 + QCA956X_PLL_CPU_CONFIG_REFDIV_MASK;
52 +
53 + pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG);
54 + nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
55 + QCA956X_PLL_CPU_CONFIG1_NINT_MASK;
56 + hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
57 + QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK;
58 + lfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT) &
59 + QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK;
60 +
61 + cpu_pll = nint * ref_rate / ref_div;
62 + cpu_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
63 + cpu_pll += (hfrac >> 13) * ref_rate / ref_div;
64 + cpu_pll /= (1 << out_div);
65 +
66 + pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG);
67 + out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
68 + QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK;
69 + ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
70 + QCA956X_PLL_DDR_CONFIG_REFDIV_MASK;
71 + pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG);
72 + nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
73 + QCA956X_PLL_DDR_CONFIG1_NINT_MASK;
74 + hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
75 + QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK;
76 + lfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT) &
77 + QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK;
78 +
79 + ddr_pll = nint * ref_rate / ref_div;
80 + ddr_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
81 + ddr_pll += (hfrac >> 13) * ref_rate / ref_div;
82 + ddr_pll /= (1 << out_div);
83 +
84 + clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG);
85 +
86 + postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
87 + QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
88 +
89 + if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
90 + cpu_rate = ref_rate;
91 + else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL)
92 + cpu_rate = ddr_pll / (postdiv + 1);
93 + else
94 + cpu_rate = cpu_pll / (postdiv + 1);
95 +
96 + postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
97 + QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
98 +
99 + if (clk_ctrl & QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
100 + ddr_rate = ref_rate;
101 + else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL)
102 + ddr_rate = cpu_pll / (postdiv + 1);
103 + else
104 + ddr_rate = ddr_pll / (postdiv + 1);
105 +
106 + postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
107 + QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
108 +
109 + if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
110 + ahb_rate = ref_rate;
111 + else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
112 + ahb_rate = ddr_pll / (postdiv + 1);
113 + else
114 + ahb_rate = cpu_pll / (postdiv + 1);
115 +
116 + ath79_add_sys_clkdev("ref", ref_rate);
117 + ath79_add_sys_clkdev("cpu", cpu_rate);
118 + ath79_add_sys_clkdev("ddr", ddr_rate);
119 + ath79_add_sys_clkdev("ahb", ahb_rate);
120 +
121 + clk_add_alias("wdt", NULL, "ref", NULL);
122 + clk_add_alias("uart", NULL, "ref", NULL);
123 +}
124 +
125 void __init ath79_clocks_init(void)
126 {
127 if (soc_is_ar71xx())
128 @@ -540,6 +634,8 @@ void __init ath79_clocks_init(void)
129 qca953x_clocks_init();
130 else if (soc_is_qca955x())
131 qca955x_clocks_init();
132 + else if (soc_is_qca956x() || soc_is_tp9343())
133 + qca956x_clocks_init();
134 else
135 BUG();
136
137 --- a/arch/mips/ath79/common.c
138 +++ b/arch/mips/ath79/common.c
139 @@ -107,6 +107,8 @@ void ath79_device_reset_set(u32 mask)
140 reg = QCA953X_RESET_REG_RESET_MODULE;
141 else if (soc_is_qca955x())
142 reg = QCA955X_RESET_REG_RESET_MODULE;
143 + else if (soc_is_qca956x() || soc_is_tp9343())
144 + reg = QCA956X_RESET_REG_RESET_MODULE;
145 else
146 panic("Reset register not defined for this SOC");
147
148 @@ -137,6 +139,8 @@ void ath79_device_reset_clear(u32 mask)
149 reg = QCA953X_RESET_REG_RESET_MODULE;
150 else if (soc_is_qca955x())
151 reg = QCA955X_RESET_REG_RESET_MODULE;
152 + else if (soc_is_qca956x() || soc_is_tp9343())
153 + reg = QCA956X_RESET_REG_RESET_MODULE;
154 else
155 panic("Reset register not defined for this SOC");
156
157 @@ -163,6 +167,8 @@ u32 ath79_device_reset_get(u32 mask)
158 reg = AR933X_RESET_REG_RESET_MODULE;
159 else if (soc_is_ar934x())
160 reg = AR934X_RESET_REG_RESET_MODULE;
161 + else if (soc_is_qca956x() || soc_is_tp9343())
162 + reg = QCA956X_RESET_REG_RESET_MODULE;
163 else
164 BUG();
165
166 --- a/arch/mips/ath79/dev-common.c
167 +++ b/arch/mips/ath79/dev-common.c
168 @@ -95,7 +95,9 @@ void __init ath79_register_uart(void)
169 soc_is_ar913x() ||
170 soc_is_ar934x() ||
171 soc_is_qca953x() ||
172 - soc_is_qca955x()) {
173 + soc_is_qca955x() ||
174 + soc_is_qca956x() ||
175 + soc_is_tp9343()) {
176 ath79_uart_data[0].uartclk = uart_clk_rate;
177 platform_device_register(&ath79_uart_device);
178 } else if (soc_is_ar933x()) {
179 @@ -164,6 +166,9 @@ void __init ath79_gpio_init(void)
180 } else if (soc_is_qca955x()) {
181 ath79_gpio_pdata.ngpios = QCA955X_GPIO_COUNT;
182 ath79_gpio_pdata.oe_inverted = 1;
183 + } else if (soc_is_qca956x() || soc_is_tp9343()) {
184 + ath79_gpio_pdata.ngpios = QCA956X_GPIO_COUNT;
185 + ath79_gpio_pdata.oe_inverted = 1;
186 } else {
187 BUG();
188 }
189 --- a/arch/mips/ath79/dev-usb.c
190 +++ b/arch/mips/ath79/dev-usb.c
191 @@ -296,6 +296,19 @@ static void __init qca955x_usb_setup(voi
192 &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
193 }
194
195 +static void __init qca956x_usb_setup(void)
196 +{
197 + ath79_usb_register("ehci-platform", 0,
198 + QCA956X_EHCI0_BASE, QCA956X_EHCI_SIZE,
199 + ATH79_IP3_IRQ(0),
200 + &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
201 +
202 + ath79_usb_register("ehci-platform", 1,
203 + QCA956X_EHCI1_BASE, QCA956X_EHCI_SIZE,
204 + ATH79_IP3_IRQ(1),
205 + &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
206 +}
207 +
208 void __init ath79_register_usb(void)
209 {
210 if (soc_is_ar71xx())
211 @@ -314,6 +327,8 @@ void __init ath79_register_usb(void)
212 qca953x_usb_setup();
213 else if (soc_is_qca955x())
214 qca955x_usb_setup();
215 + else if (soc_is_qca956x())
216 + qca956x_usb_setup();
217 else
218 BUG();
219 }
220 --- a/arch/mips/ath79/dev-wmac.c
221 +++ b/arch/mips/ath79/dev-wmac.c
222 @@ -200,6 +200,26 @@ static void qca955x_wmac_setup(void)
223 #define AR93XX_OTP_READ_DATA \
224 (soc_is_ar934x() ? AR934X_OTP_READ_DATA : AR9300_OTP_READ_DATA)
225
226 +static void qca956x_wmac_setup(void)
227 +{
228 + u32 t;
229 +
230 + ath79_wmac_device.name = "qca956x_wmac";
231 +
232 + ath79_wmac_resources[0].start = QCA956X_WMAC_BASE;
233 + ath79_wmac_resources[0].end = QCA956X_WMAC_BASE + QCA956X_WMAC_SIZE - 1;
234 + ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
235 + ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1);
236 +
237 + t = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
238 + if (t & QCA956X_BOOTSTRAP_REF_CLK_40)
239 + ath79_wmac_data.is_clk_25mhz = false;
240 + else
241 + ath79_wmac_data.is_clk_25mhz = true;
242 +
243 + ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
244 +}
245 +
246 static bool __init
247 ar93xx_wmac_otp_read_word(void __iomem *base, int addr, u32 *data)
248 {
249 @@ -403,6 +423,8 @@ void __init ath79_register_wmac(u8 *cal_
250 qca953x_wmac_setup();
251 else if (soc_is_qca955x())
252 qca955x_wmac_setup();
253 + else if (soc_is_qca956x() || soc_is_tp9343())
254 + qca956x_wmac_setup();
255 else
256 BUG();
257
258 --- a/arch/mips/ath79/early_printk.c
259 +++ b/arch/mips/ath79/early_printk.c
260 @@ -120,6 +120,8 @@ static void prom_putchar_init(void)
261 case REV_ID_MAJOR_QCA9533_V2:
262 case REV_ID_MAJOR_QCA9556:
263 case REV_ID_MAJOR_QCA9558:
264 + case REV_ID_MAJOR_TP9343:
265 + case REV_ID_MAJOR_QCA956X:
266 _prom_putchar = prom_putchar_ar71xx;
267 break;
268
269 --- a/arch/mips/ath79/gpio.c
270 +++ b/arch/mips/ath79/gpio.c
271 @@ -31,7 +31,10 @@ static void __iomem *ath79_gpio_get_func
272 soc_is_ar913x() ||
273 soc_is_ar933x())
274 reg = AR71XX_GPIO_REG_FUNC;
275 - else if (soc_is_ar934x() || soc_is_qca953x())
276 + else if (soc_is_ar934x() ||
277 + soc_is_qca953x() ||
278 + soc_is_qca956x() ||
279 + soc_is_tp9343())
280 reg = AR934X_GPIO_REG_FUNC;
281 else
282 BUG();
283 @@ -64,7 +67,7 @@ void __init ath79_gpio_output_select(uns
284 unsigned int reg;
285 u32 t, s;
286
287 - BUG_ON(!soc_is_ar934x() && !soc_is_qca953x());
288 + BUG_ON(!soc_is_ar934x() && !soc_is_qca953x() && !soc_is_qca956x());
289
290 if (gpio >= AR934X_GPIO_COUNT)
291 return;
292 --- a/arch/mips/ath79/irq.c
293 +++ b/arch/mips/ath79/irq.c
294 @@ -106,7 +106,9 @@ static void __init ath79_misc_irq_init(v
295 soc_is_ar933x() ||
296 soc_is_ar934x() ||
297 soc_is_qca953x() ||
298 - soc_is_qca955x())
299 + soc_is_qca955x() ||
300 + soc_is_qca956x() ||
301 + soc_is_tp9343())
302 ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
303 else
304 BUG();
305 @@ -263,6 +265,87 @@ static unsigned irq_wb_chan[8] = {
306 -1, -1, -1, -1, -1, -1, -1, -1,
307 };
308
309 +static void qca956x_ip2_irq_dispatch(struct irq_desc *desc)
310 +{
311 + u32 status;
312 +
313 + status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS);
314 + status &= QCA956X_EXT_INT_PCIE_RC1_ALL | QCA956X_EXT_INT_WMAC_ALL;
315 +
316 + if (status == 0) {
317 + spurious_interrupt();
318 + return;
319 + }
320 +
321 + if (status & QCA956X_EXT_INT_PCIE_RC1_ALL) {
322 + /* TODO: flush DDR? */
323 + generic_handle_irq(ATH79_IP2_IRQ(0));
324 + }
325 +
326 + if (status & QCA956X_EXT_INT_WMAC_ALL) {
327 + /* TODO: flsuh DDR? */
328 + generic_handle_irq(ATH79_IP2_IRQ(1));
329 + }
330 +}
331 +
332 +static void qca956x_ip3_irq_dispatch(struct irq_desc *desc)
333 +{
334 + u32 status;
335 +
336 + status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS);
337 + status &= QCA956X_EXT_INT_PCIE_RC2_ALL |
338 + QCA956X_EXT_INT_USB1 | QCA956X_EXT_INT_USB2;
339 +
340 + if (status == 0) {
341 + spurious_interrupt();
342 + return;
343 + }
344 +
345 + if (status & QCA956X_EXT_INT_USB1) {
346 + /* TODO: flush DDR? */
347 + generic_handle_irq(ATH79_IP3_IRQ(0));
348 + }
349 +
350 + if (status & QCA956X_EXT_INT_USB2) {
351 + /* TODO: flush DDR? */
352 + generic_handle_irq(ATH79_IP3_IRQ(1));
353 + }
354 +
355 + if (status & QCA956X_EXT_INT_PCIE_RC2_ALL) {
356 + /* TODO: flush DDR? */
357 + generic_handle_irq(ATH79_IP3_IRQ(2));
358 + }
359 +}
360 +
361 +static void qca956x_enable_timer_cb(void) {
362 + u32 misc;
363 +
364 + misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
365 + misc |= MISC_INT_MIPS_SI_TIMERINT_MASK;
366 + ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc);
367 +}
368 +
369 +static void qca956x_irq_init(void)
370 +{
371 + int i;
372 +
373 + for (i = ATH79_IP2_IRQ_BASE;
374 + i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
375 + irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
376 +
377 + irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch);
378 +
379 + for (i = ATH79_IP3_IRQ_BASE;
380 + i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
381 + irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
382 +
383 + irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
384 +
385 + /* QCA956x timer init workaround has to be applied right before setting
386 + * up the clock. Else, there will be no jiffies */
387 + late_time_init = &qca956x_enable_timer_cb;
388 +}
389 +
390 asmlinkage void plat_irq_dispatch(void)
391 {
392 unsigned long pending;
393 @@ -404,4 +487,6 @@ void __init arch_init_irq(void)
394 qca953x_irq_init();
395 else if (soc_is_qca955x())
396 qca955x_irq_init();
397 + else if (soc_is_qca956x() || soc_is_tp9343())
398 + qca956x_irq_init();
399 }
400 --- a/arch/mips/ath79/pci.c
401 +++ b/arch/mips/ath79/pci.c
402 @@ -68,6 +68,21 @@ static const struct ath79_pci_irq qca955
403 },
404 };
405
406 +static const struct ath79_pci_irq qca956x_pci_irq_map[] __initconst = {
407 + {
408 + .bus = 0,
409 + .slot = 0,
410 + .pin = 1,
411 + .irq = ATH79_PCI_IRQ(0),
412 + },
413 + {
414 + .bus = 1,
415 + .slot = 0,
416 + .pin = 1,
417 + .irq = ATH79_PCI_IRQ(1),
418 + },
419 +};
420 +
421 int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
422 {
423 int irq = -1;
424 @@ -86,6 +101,9 @@ int __init pcibios_map_irq(const struct
425 } else if (soc_is_qca955x()) {
426 ath79_pci_irq_map = qca955x_pci_irq_map;
427 ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map);
428 + } else if (soc_is_qca956x()) {
429 + ath79_pci_irq_map = qca956x_pci_irq_map;
430 + ath79_pci_nr_irqs = ARRAY_SIZE(qca956x_pci_irq_map);
431 } else {
432 pr_crit("pci %s: invalid irq map\n",
433 pci_name((struct pci_dev *) dev));
434 @@ -303,6 +321,15 @@ int __init ath79_register_pci(void)
435 QCA955X_PCI_MEM_SIZE,
436 1,
437 ATH79_IP3_IRQ(2));
438 + } else if (soc_is_qca956x()) {
439 + pdev = ath79_register_pci_ar724x(0,
440 + QCA956X_PCI_CFG_BASE1,
441 + QCA956X_PCI_CTRL_BASE1,
442 + QCA956X_PCI_CRP_BASE1,
443 + QCA956X_PCI_MEM_BASE1,
444 + QCA956X_PCI_MEM_SIZE,
445 + 1,
446 + ATH79_IP3_IRQ(2));
447 } else {
448 /* No PCI support */
449 return -ENODEV;
450 --- a/arch/mips/ath79/setup.c
451 +++ b/arch/mips/ath79/setup.c
452 @@ -180,6 +180,18 @@ static void __init ath79_detect_sys_type
453 rev = id & QCA955X_REV_ID_REVISION_MASK;
454 break;
455
456 + case REV_ID_MAJOR_QCA956X:
457 + ath79_soc = ATH79_SOC_QCA956X;
458 + chip = "956X";
459 + rev = id & QCA956X_REV_ID_REVISION_MASK;
460 + break;
461 +
462 + case REV_ID_MAJOR_TP9343:
463 + ath79_soc = ATH79_SOC_TP9343;
464 + chip = "9343";
465 + rev = id & QCA956X_REV_ID_REVISION_MASK;
466 + break;
467 +
468 default:
469 panic("ath79: unknown SoC, id:0x%08x", id);
470 }
471 @@ -187,9 +199,12 @@ static void __init ath79_detect_sys_type
472 if (ver == 1)
473 ath79_soc_rev = rev;
474
475 - if (soc_is_qca953x() || soc_is_qca955x())
476 + if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca956x())
477 sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
478 chip, ver, rev);
479 + else if (soc_is_tp9343())
480 + sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u",
481 + chip, rev);
482 else
483 sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
484 pr_info("SoC: %s\n", ath79_sys_type);
485 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
486 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
487 @@ -143,6 +143,23 @@
488 #define QCA955X_NFC_BASE 0x1b800200
489 #define QCA955X_NFC_SIZE 0xb8
490
491 +#define QCA956X_PCI_MEM_BASE1 0x12000000
492 +#define QCA956X_PCI_MEM_SIZE 0x02000000
493 +#define QCA956X_PCI_CFG_BASE1 0x16000000
494 +#define QCA956X_PCI_CFG_SIZE 0x1000
495 +#define QCA956X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000)
496 +#define QCA956X_PCI_CRP_SIZE 0x1000
497 +#define QCA956X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
498 +#define QCA956X_PCI_CTRL_SIZE 0x100
499 +
500 +#define QCA956X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
501 +#define QCA956X_WMAC_SIZE 0x20000
502 +#define QCA956X_EHCI0_BASE 0x1b000000
503 +#define QCA956X_EHCI1_BASE 0x1b400000
504 +#define QCA956X_EHCI_SIZE 0x200
505 +#define QCA956X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
506 +#define QCA956X_GMAC_SIZE 0x64
507 +
508 #define AR9300_OTP_BASE 0x14000
509 #define AR9300_OTP_STATUS 0x15f18
510 #define AR9300_OTP_STATUS_TYPE 0x7
511 @@ -152,6 +169,13 @@
512 #define AR9300_OTP_READ_DATA 0x15f1c
513
514 /*
515 + * Hidden Registers
516 + */
517 +#define QCA956X_DAM_RESET_OFFSET 0xb90001bc
518 +#define QCA956X_DAM_RESET_SIZE 0x4
519 +#define QCA956X_INLINE_CHKSUM_ENG BIT(27)
520 +
521 +/*
522 * DDR_CTRL block
523 */
524 #define AR71XX_DDR_REG_PCI_WIN0 0x7c
525 @@ -385,6 +409,49 @@
526 #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
527 #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
528
529 +#define QCA956X_PLL_CPU_CONFIG_REG 0x00
530 +#define QCA956X_PLL_CPU_CONFIG1_REG 0x04
531 +#define QCA956X_PLL_DDR_CONFIG_REG 0x08
532 +#define QCA956X_PLL_DDR_CONFIG1_REG 0x0c
533 +#define QCA956X_PLL_CLK_CTRL_REG 0x10
534 +
535 +#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
536 +#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
537 +#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
538 +#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
539 +
540 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0
541 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f
542 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5
543 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x1fff
544 +#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18
545 +#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff
546 +
547 +#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
548 +#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
549 +#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
550 +#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
551 +
552 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0
553 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f
554 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5
555 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x1fff
556 +#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18
557 +#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff
558 +
559 +#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
560 +#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
561 +#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
562 +#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
563 +#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
564 +#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
565 +#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
566 +#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
567 +#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
568 +#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL BIT(20)
569 +#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21)
570 +#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
571 +
572 /*
573 * USB_CONFIG block
574 */
575 @@ -432,6 +499,11 @@
576 #define QCA955X_RESET_REG_BOOTSTRAP 0xb0
577 #define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
578
579 +#define QCA956X_RESET_REG_RESET_MODULE 0x1c
580 +#define QCA956X_RESET_REG_BOOTSTRAP 0xb0
581 +#define QCA956X_RESET_REG_EXT_INT_STATUS 0xac
582 +
583 +#define MISC_INT_MIPS_SI_TIMERINT_MASK BIT(28)
584 #define MISC_INT_ETHSW BIT(12)
585 #define MISC_INT_TIMER4 BIT(10)
586 #define MISC_INT_TIMER3 BIT(9)
587 @@ -606,6 +678,8 @@
588
589 #define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
590
591 +#define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2)
592 +
593 #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
594 #define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
595 #define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
596 @@ -673,6 +747,37 @@
597 QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
598 QCA955X_EXT_INT_PCIE_RC2_INT3)
599
600 +#define QCA956X_EXT_INT_WMAC_MISC BIT(0)
601 +#define QCA956X_EXT_INT_WMAC_TX BIT(1)
602 +#define QCA956X_EXT_INT_WMAC_RXLP BIT(2)
603 +#define QCA956X_EXT_INT_WMAC_RXHP BIT(3)
604 +#define QCA956X_EXT_INT_PCIE_RC1 BIT(4)
605 +#define QCA956X_EXT_INT_PCIE_RC1_INT0 BIT(5)
606 +#define QCA956X_EXT_INT_PCIE_RC1_INT1 BIT(6)
607 +#define QCA956X_EXT_INT_PCIE_RC1_INT2 BIT(7)
608 +#define QCA956X_EXT_INT_PCIE_RC1_INT3 BIT(8)
609 +#define QCA956X_EXT_INT_PCIE_RC2 BIT(12)
610 +#define QCA956X_EXT_INT_PCIE_RC2_INT0 BIT(13)
611 +#define QCA956X_EXT_INT_PCIE_RC2_INT1 BIT(14)
612 +#define QCA956X_EXT_INT_PCIE_RC2_INT2 BIT(15)
613 +#define QCA956X_EXT_INT_PCIE_RC2_INT3 BIT(16)
614 +#define QCA956X_EXT_INT_USB1 BIT(24)
615 +#define QCA956X_EXT_INT_USB2 BIT(28)
616 +
617 +#define QCA956X_EXT_INT_WMAC_ALL \
618 + (QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \
619 + QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP)
620 +
621 +#define QCA956X_EXT_INT_PCIE_RC1_ALL \
622 + (QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \
623 + QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \
624 + QCA956X_EXT_INT_PCIE_RC1_INT3)
625 +
626 +#define QCA956X_EXT_INT_PCIE_RC2_ALL \
627 + (QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \
628 + QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \
629 + QCA956X_EXT_INT_PCIE_RC2_INT3)
630 +
631 #define REV_ID_MAJOR_MASK 0xfff0
632 #define REV_ID_MAJOR_AR71XX 0x00a0
633 #define REV_ID_MAJOR_AR913X 0x00b0
634 @@ -688,6 +793,8 @@
635 #define REV_ID_MAJOR_QCA9533_V2 0x0160
636 #define REV_ID_MAJOR_QCA9556 0x0130
637 #define REV_ID_MAJOR_QCA9558 0x1130
638 +#define REV_ID_MAJOR_TP9343 0x0150
639 +#define REV_ID_MAJOR_QCA956X 0x1150
640
641 #define AR71XX_REV_ID_MINOR_MASK 0x3
642 #define AR71XX_REV_ID_MINOR_AR7130 0x0
643 @@ -712,6 +819,8 @@
644
645 #define QCA955X_REV_ID_REVISION_MASK 0xf
646
647 +#define QCA956X_REV_ID_REVISION_MASK 0xf
648 +
649 /*
650 * SPI block
651 */
652 @@ -784,6 +893,19 @@
653 #define QCA955X_GPIO_REG_OUT_FUNC5 0x40
654 #define QCA955X_GPIO_REG_FUNC 0x6c
655
656 +#define QCA956X_GPIO_REG_OUT_FUNC0 0x2c
657 +#define QCA956X_GPIO_REG_OUT_FUNC1 0x30
658 +#define QCA956X_GPIO_REG_OUT_FUNC2 0x34
659 +#define QCA956X_GPIO_REG_OUT_FUNC3 0x38
660 +#define QCA956X_GPIO_REG_OUT_FUNC4 0x3c
661 +#define QCA956X_GPIO_REG_OUT_FUNC5 0x40
662 +#define QCA956X_GPIO_REG_IN_ENABLE0 0x44
663 +#define QCA956X_GPIO_REG_IN_ENABLE3 0x50
664 +#define QCA956X_GPIO_REG_FUNC 0x6c
665 +
666 +#define QCA956X_GPIO_OUT_MUX_GE0_MDO 32
667 +#define QCA956X_GPIO_OUT_MUX_GE0_MDC 33
668 +
669 #define AR71XX_GPIO_COUNT 16
670 #define AR7240_GPIO_COUNT 18
671 #define AR7241_GPIO_COUNT 20
672 @@ -792,6 +914,7 @@
673 #define AR934X_GPIO_COUNT 23
674 #define QCA953X_GPIO_COUNT 18
675 #define QCA955X_GPIO_COUNT 24
676 +#define QCA956X_GPIO_COUNT 23
677
678 /*
679 * SRIF block
680 --- a/arch/mips/include/asm/mach-ath79/ath79.h
681 +++ b/arch/mips/include/asm/mach-ath79/ath79.h
682 @@ -35,6 +35,8 @@ enum ath79_soc_type {
683 ATH79_SOC_QCA9533,
684 ATH79_SOC_QCA9556,
685 ATH79_SOC_QCA9558,
686 + ATH79_SOC_TP9343,
687 + ATH79_SOC_QCA956X,
688 };
689
690 extern enum ath79_soc_type ath79_soc;
691 @@ -126,6 +128,26 @@ static inline int soc_is_qca955x(void)
692 return soc_is_qca9556() || soc_is_qca9558();
693 }
694
695 +static inline int soc_is_tp9343(void)
696 +{
697 + return ath79_soc == ATH79_SOC_TP9343;
698 +}
699 +
700 +static inline int soc_is_qca9561(void)
701 +{
702 + return ath79_soc == ATH79_SOC_QCA956X;
703 +}
704 +
705 +static inline int soc_is_qca9563(void)
706 +{
707 + return ath79_soc == ATH79_SOC_QCA956X;
708 +}
709 +
710 +static inline int soc_is_qca956x(void)
711 +{
712 + return soc_is_qca9561() || soc_is_qca9563();
713 +}
714 +
715 void ath79_ddr_set_pci_windows(void);
716
717 extern void __iomem *ath79_gpio_base;