ar71xx: disable 40Mhz refclk for QCA953x
[openwrt/openwrt.git] / target / linux / ar71xx / patches-4.9 / 640-MIPS-ath79-add-QCA955x-wmac-reset.patch
1 --- a/arch/mips/ath79/common.c
2 +++ b/arch/mips/ath79/common.c
3 @@ -38,7 +38,7 @@ unsigned int ath79_soc_rev;
4 void __iomem *ath79_pll_base;
5 void __iomem *ath79_reset_base;
6 EXPORT_SYMBOL_GPL(ath79_reset_base);
7 -static void __iomem *ath79_ddr_base;
8 +void __iomem *ath79_ddr_base;
9 static void __iomem *ath79_ddr_wb_flush_base;
10 static void __iomem *ath79_ddr_pci_win_base;
11
12 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
13 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
14 @@ -32,7 +32,7 @@
15 #define AR71XX_SPI_SIZE 0x01000000
16
17 #define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000)
18 -#define AR71XX_DDR_CTRL_SIZE 0x100
19 +#define AR71XX_DDR_CTRL_SIZE 0x200
20 #define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
21 #define AR71XX_UART_SIZE 0x100
22 #define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
23 @@ -229,6 +229,9 @@
24 #define QCA953X_DDR_REG_FLUSH_PCIE 0xa8
25 #define QCA953X_DDR_REG_FLUSH_WMAC 0xac
26
27 +#define QCA955X_DDR_CTL_CONFIG 0x108
28 +#define QCA955X_DDR_CTL_CONFIG_ACT_WMAC BIT(23)
29 +
30 /*
31 * PLL block
32 */
33 --- a/arch/mips/ath79/dev-wmac.c
34 +++ b/arch/mips/ath79/dev-wmac.c
35 @@ -165,6 +165,27 @@ static void qca953x_wmac_setup(void)
36 ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
37 }
38
39 +static int ar955x_wmac_reset(void)
40 +{
41 + int i;
42 +
43 + /* Try to wait for WMAC DDR activity to stop */
44 + for (i = 0; i < 10; i++) {
45 + if (!(__raw_readl(ath79_ddr_base + QCA955X_DDR_CTL_CONFIG) &
46 + QCA955X_DDR_CTL_CONFIG_ACT_WMAC))
47 + break;
48 +
49 + udelay(10);
50 + }
51 +
52 + ath79_device_reset_set(QCA955X_RESET_RTC);
53 + udelay(10);
54 + ath79_device_reset_clear(QCA955X_RESET_RTC);
55 + udelay(10);
56 +
57 + return 0;
58 +}
59 +
60 static void qca955x_wmac_setup(void)
61 {
62 u32 t;
63 @@ -181,6 +202,8 @@ static void qca955x_wmac_setup(void)
64 ath79_wmac_data.is_clk_25mhz = false;
65 else
66 ath79_wmac_data.is_clk_25mhz = true;
67 +
68 + ath79_wmac_data.external_reset = ar955x_wmac_reset;
69 }
70
71 #define AR93XX_WMAC_SIZE \
72 --- a/arch/mips/ath79/common.h
73 +++ b/arch/mips/ath79/common.h
74 @@ -19,6 +19,8 @@
75 #define ATH79_MEM_SIZE_MIN (2 * 1024 * 1024)
76 #define ATH79_MEM_SIZE_MAX (256 * 1024 * 1024)
77
78 +extern void __iomem *ath79_ddr_base;
79 +
80 void ath79_clocks_init(void);
81 unsigned long ath79_get_sys_clk_rate(const char *id);
82