75f539bb0d8fed21fb7957b30988aeccd9199721
[openwrt/openwrt.git] / target / linux / archs38 / dts / nsim_hs_idu.dts
1 /*
2 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8 /dts-v1/;
9
10 /include/ "skeleton.dtsi"
11
12 / {
13 model = "Synopsys ARC HS38 nSIM simulator";
14 compatible = "snps,nsim_hs";
15 interrupt-parent = <&core_intc>;
16
17 chosen {
18 bootargs = "earlycon=arc_uart,mmio32,0xc0fc1000,115200n8 console=ttyARC0,115200n8";
19 };
20
21 aliases {
22 serial0 = &arcuart0;
23 };
24
25 fpga {
26 compatible = "simple-bus";
27 #address-cells = <1>;
28 #size-cells = <1>;
29
30 /* child and parent address space 1:1 mapped */
31 ranges;
32
33 core_intc: core-interrupt-controller {
34 compatible = "snps,archs-intc";
35 interrupt-controller;
36 #interrupt-cells = <1>;
37 };
38
39 idu_intc: idu-interrupt-controller {
40 compatible = "snps,archs-idu-intc";
41 interrupt-controller;
42 interrupt-parent = <&core_intc>;
43
44 /*
45 * <hwirq distribution>
46 * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
47 */
48 #interrupt-cells = <2>;
49
50 /*
51 * upstream irqs to core intc - downstream these are
52 * "COMMON" irq 0,1..
53 */
54 interrupts = <24 25 26 27 28 29 30 31>;
55 };
56
57 arcuart0: serial@c0fc1000 {
58 compatible = "snps,arc-uart";
59 reg = <0xc0fc1000 0x100>;
60 interrupt-parent = <&idu_intc>;
61 interrupts = <0 0>;
62 clock-frequency = <80000000>;
63 current-speed = <115200>;
64 status = "okay";
65 };
66
67 arcpct0: pct {
68 compatible = "snps,archs-pct";
69 #interrupt-cells = <1>;
70 interrupts = <20>;
71 };
72 };
73 };