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[openwrt/openwrt.git] / target / linux / aruba-2.6 / files / include / asm-mips / idt-boards / rc32434 / rc32434_pci.h
1 /**************************************************************************
2 *
3 * BRIEF MODULE DESCRIPTION
4 * PCI register definitio
5 *
6 * Copyright 2004 IDT Inc. (rischelp@idt.com)
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 *
28 *
29 **************************************************************************
30 * May 2004 rkt, neb.
31 *
32 * Initial Release
33 *
34 *
35 *
36 **************************************************************************
37 */
38
39 #ifndef __IDT_PCI_H__
40 #define __IDT_PCI_H__
41
42 enum
43 {
44 PCI0_PhysicalAddress = 0x18080000,
45 PCI_PhysicalAddress = PCI0_PhysicalAddress,
46
47 PCI0_VirtualAddress = 0xB8080000,
48 PCI_VirtualAddress = PCI0_VirtualAddress,
49 } ;
50
51 enum
52 {
53 PCI_LbaCount = 4, // Local base addresses.
54 } ;
55
56 typedef struct
57 {
58 u32 a ; // Address.
59 u32 c ; // Control.
60 u32 m ; // mapping.
61 } PCI_Map_s ;
62
63 typedef struct
64 {
65 u32 pcic ;
66 u32 pcis ;
67 u32 pcism ;
68 u32 pcicfga ;
69 u32 pcicfgd ;
70 PCI_Map_s pcilba [PCI_LbaCount] ;
71 u32 pcidac ;
72 u32 pcidas ;
73 u32 pcidasm ;
74 u32 pcidad ;
75 u32 pcidma8c ;
76 u32 pcidma9c ;
77 u32 pcitc ;
78 } volatile *PCI_t ;
79
80 // PCI messaging unit.
81 enum
82 {
83 PCIM_Count = 2,
84 } ;
85 typedef struct
86 {
87 u32 pciim [PCIM_Count] ;
88 u32 pciom [PCIM_Count] ;
89 u32 pciid ;
90 u32 pciiic ;
91 u32 pciiim ;
92 u32 pciiod ;
93 u32 pciioic ;
94 u32 pciioim ;
95 } volatile *PCIM_t ;
96
97 /*******************************************************************************
98 *
99 * PCI Control Register
100 *
101 ******************************************************************************/
102 enum
103 {
104 PCIC_en_b = 0,
105 PCIC_en_m = 0x00000001,
106 PCIC_tnr_b = 1,
107 PCIC_tnr_m = 0x00000002,
108 PCIC_sce_b = 2,
109 PCIC_sce_m = 0x00000004,
110 PCIC_ien_b = 3,
111 PCIC_ien_m = 0x00000008,
112 PCIC_aaa_b = 4,
113 PCIC_aaa_m = 0x00000010,
114 PCIC_eap_b = 5,
115 PCIC_eap_m = 0x00000020,
116 PCIC_pcim_b = 6,
117 PCIC_pcim_m = 0x000001c0,
118 PCIC_pcim_disabled_v = 0,
119 PCIC_pcim_tnr_v = 1, // Satellite - target not ready
120 PCIC_pcim_suspend_v = 2, // Satellite - suspended CPU.
121 PCIC_pcim_extern_v = 3, // Host - external arbiter.
122 PCIC_pcim_fixed_v = 4, // Host - fixed priority arb.
123 PCIC_pcim_roundrobin_v = 5, // Host - round robin priority.
124 PCIC_pcim_reserved6_v = 6,
125 PCIC_pcim_reserved7_v = 7,
126 PCIC_igm_b = 9,
127 PCIC_igm_m = 0x00000200,
128 } ;
129
130 /*******************************************************************************
131 *
132 * PCI Status Register
133 *
134 ******************************************************************************/
135 enum {
136 PCIS_eed_b = 0,
137 PCIS_eed_m = 0x00000001,
138 PCIS_wr_b = 1,
139 PCIS_wr_m = 0x00000002,
140 PCIS_nmi_b = 2,
141 PCIS_nmi_m = 0x00000004,
142 PCIS_ii_b = 3,
143 PCIS_ii_m = 0x00000008,
144 PCIS_cwe_b = 4,
145 PCIS_cwe_m = 0x00000010,
146 PCIS_cre_b = 5,
147 PCIS_cre_m = 0x00000020,
148 PCIS_mdpe_b = 6,
149 PCIS_mdpe_m = 0x00000040,
150 PCIS_sta_b = 7,
151 PCIS_sta_m = 0x00000080,
152 PCIS_rta_b = 8,
153 PCIS_rta_m = 0x00000100,
154 PCIS_rma_b = 9,
155 PCIS_rma_m = 0x00000200,
156 PCIS_sse_b = 10,
157 PCIS_sse_m = 0x00000400,
158 PCIS_ose_b = 11,
159 PCIS_ose_m = 0x00000800,
160 PCIS_pe_b = 12,
161 PCIS_pe_m = 0x00001000,
162 PCIS_tae_b = 13,
163 PCIS_tae_m = 0x00002000,
164 PCIS_rle_b = 14,
165 PCIS_rle_m = 0x00004000,
166 PCIS_bme_b = 15,
167 PCIS_bme_m = 0x00008000,
168 PCIS_prd_b = 16,
169 PCIS_prd_m = 0x00010000,
170 PCIS_rip_b = 17,
171 PCIS_rip_m = 0x00020000,
172 } ;
173
174 /*******************************************************************************
175 *
176 * PCI Status Mask Register
177 *
178 ******************************************************************************/
179 enum {
180 PCISM_eed_b = 0,
181 PCISM_eed_m = 0x00000001,
182 PCISM_wr_b = 1,
183 PCISM_wr_m = 0x00000002,
184 PCISM_nmi_b = 2,
185 PCISM_nmi_m = 0x00000004,
186 PCISM_ii_b = 3,
187 PCISM_ii_m = 0x00000008,
188 PCISM_cwe_b = 4,
189 PCISM_cwe_m = 0x00000010,
190 PCISM_cre_b = 5,
191 PCISM_cre_m = 0x00000020,
192 PCISM_mdpe_b = 6,
193 PCISM_mdpe_m = 0x00000040,
194 PCISM_sta_b = 7,
195 PCISM_sta_m = 0x00000080,
196 PCISM_rta_b = 8,
197 PCISM_rta_m = 0x00000100,
198 PCISM_rma_b = 9,
199 PCISM_rma_m = 0x00000200,
200 PCISM_sse_b = 10,
201 PCISM_sse_m = 0x00000400,
202 PCISM_ose_b = 11,
203 PCISM_ose_m = 0x00000800,
204 PCISM_pe_b = 12,
205 PCISM_pe_m = 0x00001000,
206 PCISM_tae_b = 13,
207 PCISM_tae_m = 0x00002000,
208 PCISM_rle_b = 14,
209 PCISM_rle_m = 0x00004000,
210 PCISM_bme_b = 15,
211 PCISM_bme_m = 0x00008000,
212 PCISM_prd_b = 16,
213 PCISM_prd_m = 0x00010000,
214 PCISM_rip_b = 17,
215 PCISM_rip_m = 0x00020000,
216 } ;
217
218 /*******************************************************************************
219 *
220 * PCI Configuration Address Register
221 *
222 ******************************************************************************/
223 enum {
224 PCICFGA_reg_b = 2,
225 PCICFGA_reg_m = 0x000000fc,
226 PCICFGA_reg_id_v = 0x00>>2, //use PCFGID_
227 PCICFGA_reg_04_v = 0x04>>2, //use PCFG04_
228 PCICFGA_reg_08_v = 0x08>>2, //use PCFG08_
229 PCICFGA_reg_0C_v = 0x0C>>2, //use PCFG0C_
230 PCICFGA_reg_pba0_v = 0x10>>2, //use PCIPBA_
231 PCICFGA_reg_pba1_v = 0x14>>2, //use PCIPBA_
232 PCICFGA_reg_pba2_v = 0x18>>2, //use PCIPBA_
233 PCICFGA_reg_pba3_v = 0x1c>>2, //use PCIPBA_
234 PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
235 PCICFGA_reg_3C_v = 0x3C>>2, //use PCFG3C_
236 PCICFGA_reg_pba0c_v = 0x44>>2, //use PCIPBAC_
237 PCICFGA_reg_pba0m_v = 0x48>>2,
238 PCICFGA_reg_pba1c_v = 0x4c>>2, //use PCIPBAC_
239 PCICFGA_reg_pba1m_v = 0x50>>2,
240 PCICFGA_reg_pba2c_v = 0x54>>2, //use PCIPBAC_
241 PCICFGA_reg_pba2m_v = 0x58>>2,
242 PCICFGA_reg_pba3c_v = 0x5c>>2, //use PCIPBAC_
243 PCICFGA_reg_pba3m_v = 0x60>>2,
244 PCICFGA_reg_pmgt_v = 0x64>>2,
245 PCICFGA_func_b = 8,
246 PCICFGA_func_m = 0x00000700,
247 PCICFGA_dev_b = 11,
248 PCICFGA_dev_m = 0x0000f800,
249 PCICFGA_dev_internal_v = 0,
250 PCICFGA_bus_b = 16,
251 PCICFGA_bus_m = 0x00ff0000,
252 PCICFGA_bus_type0_v = 0, //local bus
253 PCICFGA_en_b = 31, // read only
254 PCICFGA_en_m = 0x80000000,
255 } ;
256
257 enum {
258 PCFGID_vendor_b = 0,
259 PCFGID_vendor_m = 0x0000ffff,
260 PCFGID_vendor_IDT_v = 0x111d,
261 PCFGID_device_b = 16,
262 PCFGID_device_m = 0xffff0000,
263 PCFGID_device_Korinade_v = 0x0214,
264
265 PCFG04_command_ioena_b = 1,
266 PCFG04_command_ioena_m = 0x00000001,
267 PCFG04_command_memena_b = 2,
268 PCFG04_command_memena_m = 0x00000002,
269 PCFG04_command_bmena_b = 3,
270 PCFG04_command_bmena_m = 0x00000004,
271 PCFG04_command_mwinv_b = 5,
272 PCFG04_command_mwinv_m = 0x00000010,
273 PCFG04_command_parena_b = 7,
274 PCFG04_command_parena_m = 0x00000040,
275 PCFG04_command_serrena_b = 9,
276 PCFG04_command_serrena_m = 0x00000100,
277 PCFG04_command_fastbbena_b = 10,
278 PCFG04_command_fastbbena_m = 0x00000200,
279 PCFG04_status_b = 16,
280 PCFG04_status_m = 0xffff0000,
281 PCFG04_status_66MHz_b = 21, // 66 MHz enable
282 PCFG04_status_66MHz_m = 0x00200000,
283 PCFG04_status_fbb_b = 23,
284 PCFG04_status_fbb_m = 0x00800000,
285 PCFG04_status_mdpe_b = 24,
286 PCFG04_status_mdpe_m = 0x01000000,
287 PCFG04_status_dst_b = 25,
288 PCFG04_status_dst_m = 0x06000000,
289 PCFG04_status_sta_b = 27,
290 PCFG04_status_sta_m = 0x08000000,
291 PCFG04_status_rta_b = 28,
292 PCFG04_status_rta_m = 0x10000000,
293 PCFG04_status_rma_b = 29,
294 PCFG04_status_rma_m = 0x20000000,
295 PCFG04_status_sse_b = 30,
296 PCFG04_status_sse_m = 0x40000000,
297 PCFG04_status_pe_b = 31,
298 PCFG04_status_pe_m = 0x40000000,
299
300 PCFG08_revId_b = 0,
301 PCFG08_revId_m = 0x000000ff,
302 PCFG08_classCode_b = 0,
303 PCFG08_classCode_m = 0xffffff00,
304 PCFG08_classCode_bridge_v = 06,
305 PCFG08_classCode_proc_v = 0x0b3000, // processor-MIPS
306 PCFG0C_cacheline_b = 0,
307 PCFG0C_cacheline_m = 0x000000ff,
308 PCFG0C_masterLatency_b = 8,
309 PCFG0C_masterLatency_m = 0x0000ff00,
310 PCFG0C_headerType_b = 16,
311 PCFG0C_headerType_m = 0x00ff0000,
312 PCFG0C_bist_b = 24,
313 PCFG0C_bist_m = 0xff000000,
314
315 PCIPBA_msi_b = 0,
316 PCIPBA_msi_m = 0x00000001,
317 PCIPBA_p_b = 3,
318 PCIPBA_p_m = 0x00000004,
319 PCIPBA_baddr_b = 8,
320 PCIPBA_baddr_m = 0xffffff00,
321
322 PCFGSS_vendorId_b = 0,
323 PCFGSS_vendorId_m = 0x0000ffff,
324 PCFGSS_id_b = 16,
325 PCFGSS_id_m = 0xffff0000,
326
327 PCFG3C_interruptLine_b = 0,
328 PCFG3C_interruptLine_m = 0x000000ff,
329 PCFG3C_interruptPin_b = 8,
330 PCFG3C_interruptPin_m = 0x0000ff00,
331 PCFG3C_minGrant_b = 16,
332 PCFG3C_minGrant_m = 0x00ff0000,
333 PCFG3C_maxLat_b = 24,
334 PCFG3C_maxLat_m = 0xff000000,
335
336 PCIPBAC_msi_b = 0,
337 PCIPBAC_msi_m = 0x00000001,
338 PCIPBAC_p_b = 1,
339 PCIPBAC_p_m = 0x00000002,
340 PCIPBAC_size_b = 2,
341 PCIPBAC_size_m = 0x0000007c,
342 PCIPBAC_sb_b = 7,
343 PCIPBAC_sb_m = 0x00000080,
344 PCIPBAC_pp_b = 8,
345 PCIPBAC_pp_m = 0x00000100,
346 PCIPBAC_mr_b = 9,
347 PCIPBAC_mr_m = 0x00000600,
348 PCIPBAC_mr_read_v =0, //no prefetching
349 PCIPBAC_mr_readLine_v =1,
350 PCIPBAC_mr_readMult_v =2,
351 PCIPBAC_mrl_b = 11,
352 PCIPBAC_mrl_m = 0x00000800,
353 PCIPBAC_mrm_b = 12,
354 PCIPBAC_mrm_m = 0x00001000,
355 PCIPBAC_trp_b = 13,
356 PCIPBAC_trp_m = 0x00002000,
357
358 PCFG40_trdyTimeout_b = 0,
359 PCFG40_trdyTimeout_m = 0x000000ff,
360 PCFG40_retryLim_b = 8,
361 PCFG40_retryLim_m = 0x0000ff00,
362 };
363
364 /*******************************************************************************
365 *
366 * PCI Local Base Address [0|1|2|3] Register
367 *
368 ******************************************************************************/
369 enum {
370 PCILBA_baddr_b = 0, // In PCI_t -> pcilba [] .a
371 PCILBA_baddr_m = 0xffffff00,
372 } ;
373 /*******************************************************************************
374 *
375 * PCI Local Base Address Control Register
376 *
377 ******************************************************************************/
378 enum {
379 PCILBAC_msi_b = 0, // In pPci->pcilba[i].c
380 PCILBAC_msi_m = 0x00000001,
381 PCILBAC_msi_mem_v = 0,
382 PCILBAC_msi_io_v = 1,
383 PCILBAC_size_b = 2, // In pPci->pcilba[i].c
384 PCILBAC_size_m = 0x0000007c,
385 PCILBAC_sb_b = 7, // In pPci->pcilba[i].c
386 PCILBAC_sb_m = 0x00000080,
387 PCILBAC_rt_b = 8, // In pPci->pcilba[i].c
388 PCILBAC_rt_m = 0x00000100,
389 PCILBAC_rt_noprefetch_v = 0, // mem read
390 PCILBAC_rt_prefetch_v = 1, // mem readline
391 } ;
392
393 /*******************************************************************************
394 *
395 * PCI Local Base Address [0|1|2|3] Mapping Register
396 *
397 ******************************************************************************/
398 enum {
399 PCILBAM_maddr_b = 8,
400 PCILBAM_maddr_m = 0xffffff00,
401 } ;
402
403 /*******************************************************************************
404 *
405 * PCI Decoupled Access Control Register
406 *
407 ******************************************************************************/
408 enum {
409 PCIDAC_den_b = 0,
410 PCIDAC_den_m = 0x00000001,
411 } ;
412
413 /*******************************************************************************
414 *
415 * PCI Decoupled Access Status Register
416 *
417 ******************************************************************************/
418 enum {
419 PCIDAS_d_b = 0,
420 PCIDAS_d_m = 0x00000001,
421 PCIDAS_b_b = 1,
422 PCIDAS_b_m = 0x00000002,
423 PCIDAS_e_b = 2,
424 PCIDAS_e_m = 0x00000004,
425 PCIDAS_ofe_b = 3,
426 PCIDAS_ofe_m = 0x00000008,
427 PCIDAS_off_b = 4,
428 PCIDAS_off_m = 0x00000010,
429 PCIDAS_ife_b = 5,
430 PCIDAS_ife_m = 0x00000020,
431 PCIDAS_iff_b = 6,
432 PCIDAS_iff_m = 0x00000040,
433 } ;
434
435 /*******************************************************************************
436 *
437 * PCI DMA Channel 8 Configuration Register
438 *
439 ******************************************************************************/
440 enum
441 {
442 PCIDMA8C_mbs_b = 0, // Maximum Burst Size.
443 PCIDMA8C_mbs_m = 0x00000fff, // { pcidma8c }
444 PCIDMA8C_our_b = 12, // Optimize Unaligned Burst Reads.
445 PCIDMA8C_our_m = 0x00001000, // { pcidma8c }
446 } ;
447
448 /*******************************************************************************
449 *
450 * PCI DMA Channel 9 Configuration Register
451 *
452 ******************************************************************************/
453 enum
454 {
455 PCIDMA9C_mbs_b = 0, // Maximum Burst Size.
456 PCIDMA9C_mbs_m = 0x00000fff, // { pcidma9c }
457 } ;
458
459 /*******************************************************************************
460 *
461 * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
462 *
463 ******************************************************************************/
464 enum {
465 PCIDMAD_pt_b = 22, // in DEVCMD field (descriptor)
466 PCIDMAD_pt_m = 0x00c00000, // preferred transaction field
467 // These are for reads (DMA channel 8)
468 PCIDMAD_devcmd_mr_v = 0, //memory read
469 PCIDMAD_devcmd_mrl_v = 1, //memory read line
470 PCIDMAD_devcmd_mrm_v = 2, //memory read multiple
471 PCIDMAD_devcmd_ior_v = 3, //I/O read
472 // These are for writes (DMA channel 9)
473 PCIDMAD_devcmd_mw_v = 0, //memory write
474 PCIDMAD_devcmd_mwi_v = 1, //memory write invalidate
475 PCIDMAD_devcmd_iow_v = 3, //I/O write
476
477 // Swap byte field applies to both DMA channel 8 and 9
478 PCIDMAD_sb_b = 24, // in DEVCMD field (descriptor)
479 PCIDMAD_sb_m = 0x01000000, // swap byte field
480 } ;
481
482
483 /*******************************************************************************
484 *
485 * PCI Target Control Register
486 *
487 ******************************************************************************/
488 enum
489 {
490 PCITC_rtimer_b = 0, // In PCITC_t -> pcitc
491 PCITC_rtimer_m = 0x000000ff,
492 PCITC_dtimer_b = 8, // In PCITC_t -> pcitc
493 PCITC_dtimer_m = 0x0000ff00,
494 PCITC_rdr_b = 18, // In PCITC_t -> pcitc
495 PCITC_rdr_m = 0x00040000,
496 PCITC_ddt_b = 19, // In PCITC_t -> pcitc
497 PCITC_ddt_m = 0x00080000,
498 } ;
499 /*******************************************************************************
500 *
501 * PCI messaging unit [applies to both inbound and outbound registers ]
502 *
503 ******************************************************************************/
504 enum
505 {
506 PCIM_m0_b = 0, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
507 PCIM_m0_m = 0x00000001, // inbound or outbound message 0
508 PCIM_m1_b = 1, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
509 PCIM_m1_m = 0x00000002, // inbound or outbound message 1
510 PCIM_db_b = 2, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
511 PCIM_db_m = 0x00000004, // inbound or outbound doorbell
512 };
513
514
515
516
517
518
519 #define PCI_MSG_VirtualAddress 0xB8088010
520 #define rc32434_pci ((volatile PCI_t) PCI0_VirtualAddress)
521 #define rc32434_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
522
523 #define PCIM_SHFT 0x6
524 #define PCIM_BIT_LEN 0x7
525 #define PCIM_H_EA 0x3
526 #define PCIM_H_IA_FIX 0x4
527 #define PCIM_H_IA_RR 0x5
528 #if 0
529 #define PCI_ADDR_START 0x13000000
530 #endif
531
532 #define PCI_ADDR_START 0x50000000
533
534 #define CPUTOPCI_MEM_WIN 0x02000000
535 #define CPUTOPCI_IO_WIN 0x00100000
536 #define PCILBA_SIZE_SHFT 2
537 #define PCILBA_SIZE_MASK 0x1F
538 #define SIZE_256MB 0x1C
539 #define SIZE_128MB 0x1B
540 #define SIZE_64MB 0x1A
541 #define SIZE_32MB 0x19
542 #define SIZE_16MB 0x18
543 #define SIZE_4MB 0x16
544 #define SIZE_2MB 0x15
545 #define SIZE_1MB 0x14
546 #define KORINA_CONFIG0_ADDR 0x80000000
547 #define KORINA_CONFIG1_ADDR 0x80000004
548 #define KORINA_CONFIG2_ADDR 0x80000008
549 #define KORINA_CONFIG3_ADDR 0x8000000C
550 #define KORINA_CONFIG4_ADDR 0x80000010
551 #define KORINA_CONFIG5_ADDR 0x80000014
552 #define KORINA_CONFIG6_ADDR 0x80000018
553 #define KORINA_CONFIG7_ADDR 0x8000001C
554 #define KORINA_CONFIG8_ADDR 0x80000020
555 #define KORINA_CONFIG9_ADDR 0x80000024
556 #define KORINA_CONFIG10_ADDR 0x80000028
557 #define KORINA_CONFIG11_ADDR 0x8000002C
558 #define KORINA_CONFIG12_ADDR 0x80000030
559 #define KORINA_CONFIG13_ADDR 0x80000034
560 #define KORINA_CONFIG14_ADDR 0x80000038
561 #define KORINA_CONFIG15_ADDR 0x8000003C
562 #define KORINA_CONFIG16_ADDR 0x80000040
563 #define KORINA_CONFIG17_ADDR 0x80000044
564 #define KORINA_CONFIG18_ADDR 0x80000048
565 #define KORINA_CONFIG19_ADDR 0x8000004C
566 #define KORINA_CONFIG20_ADDR 0x80000050
567 #define KORINA_CONFIG21_ADDR 0x80000054
568 #define KORINA_CONFIG22_ADDR 0x80000058
569 #define KORINA_CONFIG23_ADDR 0x8000005C
570 #define KORINA_CONFIG24_ADDR 0x80000060
571 #define KORINA_CONFIG25_ADDR 0x80000064
572 #define KORINA_CMD (PCFG04_command_ioena_m | \
573 PCFG04_command_memena_m | \
574 PCFG04_command_bmena_m | \
575 PCFG04_command_mwinv_m | \
576 PCFG04_command_parena_m | \
577 PCFG04_command_serrena_m )
578
579 #define KORINA_STAT (PCFG04_status_mdpe_m | \
580 PCFG04_status_sta_m | \
581 PCFG04_status_rta_m | \
582 PCFG04_status_rma_m | \
583 PCFG04_status_sse_m | \
584 PCFG04_status_pe_m)
585
586 #define KORINA_CNFG1 ((KORINA_STAT<<16)|KORINA_CMD)
587
588 #define KORINA_REVID 0
589 #define KORINA_CLASS_CODE 0
590 #define KORINA_CNFG2 ((KORINA_CLASS_CODE<<8) | \
591 KORINA_REVID)
592
593 #define KORINA_CACHE_LINE_SIZE 4
594 #define KORINA_MASTER_LAT 0x3c
595 #define KORINA_HEADER_TYPE 0
596 #define KORINA_BIST 0
597
598 #define KORINA_CNFG3 ((KORINA_BIST << 24) | \
599 (KORINA_HEADER_TYPE<<16) | \
600 (KORINA_MASTER_LAT<<8) | \
601 KORINA_CACHE_LINE_SIZE )
602
603 #define KORINA_BAR0 0x00000008 /* 128 MB Memory */
604 #define KORINA_BAR1 0x18800001 /* 1 MB IO */
605 #define KORINA_BAR2 0x18000001 /* 2 MB IO window for Korina
606 internal Registers */
607 #define KORINA_BAR3 0x48000008 /* Spare 128 MB Memory */
608
609 #define KORINA_CNFG4 KORINA_BAR0
610 #define KORINA_CNFG5 KORINA_BAR1
611 #define KORINA_CNFG6 KORINA_BAR2
612 #define KORINA_CNFG7 KORINA_BAR3
613
614 #define KORINA_SUBSYS_VENDOR_ID 0x011d
615 #define KORINA_SUBSYSTEM_ID 0x0214
616 #define KORINA_CNFG8 0
617 #define KORINA_CNFG9 0
618 #define KORINA_CNFG10 0
619 #define KORINA_CNFG11 ((KORINA_SUBSYS_VENDOR_ID<<16) | \
620 KORINA_SUBSYSTEM_ID)
621 #define KORINA_INT_LINE 1
622 #define KORINA_INT_PIN 1
623 #define KORINA_MIN_GNT 8
624 #define KORINA_MAX_LAT 0x38
625 #define KORINA_CNFG12 0
626 #define KORINA_CNFG13 0
627 #define KORINA_CNFG14 0
628 #define KORINA_CNFG15 ((KORINA_MAX_LAT<<24) | \
629 (KORINA_MIN_GNT<<16) | \
630 (KORINA_INT_PIN<<8) | \
631 KORINA_INT_LINE)
632 #define KORINA_RETRY_LIMIT 0x80
633 #define KORINA_TRDY_LIMIT 0x80
634 #define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
635 KORINA_TRDY_LIMIT)
636 #define PCI_PBAxC_R 0x0
637 #define PCI_PBAxC_RL 0x1
638 #define PCI_PBAxC_RM 0x2
639 #define SIZE_SHFT 2
640
641 #if defined(__MIPSEB__)
642 #define KORINA_PBA0C ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
643 ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
644 PCIPBAC_pp_m | \
645 (SIZE_128MB<<SIZE_SHFT) | \
646 PCIPBAC_p_m)
647 #else
648 #define KORINA_PBA0C ( PCIPBAC_mrl_m | \
649 ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
650 PCIPBAC_pp_m | \
651 (SIZE_128MB<<SIZE_SHFT) | \
652 PCIPBAC_p_m)
653 #endif
654 #define KORINA_CNFG17 KORINA_PBA0C
655 #define KORINA_PBA0M 0x0
656 #define KORINA_CNFG18 KORINA_PBA0M
657
658 #if defined(__MIPSEB__)
659 #define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
660 PCIPBAC_msi_m)
661 #else
662 #define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | \
663 PCIPBAC_msi_m)
664 #endif
665 #define KORINA_CNFG19 KORINA_PBA1C
666 #define KORINA_PBA1M 0x0
667 #define KORINA_CNFG20 KORINA_PBA1M
668
669 #if defined(__MIPSEB__)
670 #define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
671 PCIPBAC_msi_m)
672 #else
673 #define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | \
674 PCIPBAC_msi_m)
675 #endif
676 #define KORINA_CNFG21 KORINA_PBA2C
677 #define KORINA_PBA2M 0x18000000
678 #define KORINA_CNFG22 KORINA_PBA2M
679 #define KORINA_PBA3C 0
680 #define KORINA_CNFG23 KORINA_PBA3C
681 #define KORINA_PBA3M 0
682 #define KORINA_CNFG24 KORINA_PBA3M
683
684
685
686 #define PCITC_DTIMER_VAL 8
687 #define PCITC_RTIMER_VAL 0x10
688
689
690
691
692 #endif // __IDT_PCI_H__
693
694
695
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