fix [6191]
[openwrt/openwrt.git] / target / linux / aruba-2.6 / patches / 000-aruba.patch
1 diff -Nur linux-2.6.17/arch/mips/aruba/Makefile linux-2.6.17-owrt/arch/mips/aruba/Makefile
2 --- linux-2.6.17/arch/mips/aruba/Makefile 1970-01-01 01:00:00.000000000 +0100
3 +++ linux-2.6.17-owrt/arch/mips/aruba/Makefile 2006-06-18 12:44:28.000000000 +0200
4 @@ -0,0 +1,49 @@
5 +###############################################################################
6 +#
7 +# BRIEF MODULE DESCRIPTION
8 +# Makefile for IDT EB434 BSP
9 +#
10 +# Copyright 2004 IDT Inc. (rischelp@idt.com)
11 +#
12 +# This program is free software; you can redistribute it and/or modify it
13 +# under the terms of the GNU General Public License as published by the
14 +# Free Software Foundation; either version 2 of the License, or (at your
15 +# option) any later version.
16 +#
17 +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 +#
28 +# You should have received a copy of the GNU General Public License along
29 +# with this program; if not, write to the Free Software Foundation, Inc.,
30 +# 675 Mass Ave, Cambridge, MA 02139, USA.
31 +#
32 +#
33 +###############################################################################
34 +# May 2004 rkt, neb
35 +#
36 +# Initial Release
37 +#
38 +#
39 +#
40 +###############################################################################
41 +
42 +
43 +# .S.s:
44 +# $(CPP) $(CFLAGS) $< -o $*.s
45 +# .S.o:
46 +# $(CC) $(CFLAGS) -c $< -o $*.o
47 +
48 +obj-y := prom.o setup.o irq.o time.o flash_lock.o
49 +obj-$(CONFIG_SERIAL_8250) += serial.o
50 +
51 +subdir-y += nvram
52 +obj-y += nvram/built-in.o
53 +
54 diff -Nur linux-2.6.17/arch/mips/aruba/nvram/Makefile linux-2.6.17-owrt/arch/mips/aruba/nvram/Makefile
55 --- linux-2.6.17/arch/mips/aruba/nvram/Makefile 1970-01-01 01:00:00.000000000 +0100
56 +++ linux-2.6.17-owrt/arch/mips/aruba/nvram/Makefile 2006-06-18 12:44:28.000000000 +0200
57 @@ -0,0 +1,46 @@
58 +###############################################################################
59 +#
60 +# BRIEF MODULE DESCRIPTION
61 +# Makefile for IDT EB434 nvram access routines
62 +#
63 +# Copyright 2004 IDT Inc. (rischelp@idt.com)
64 +#
65 +# This program is free software; you can redistribute it and/or modify it
66 +# under the terms of the GNU General Public License as published by the
67 +# Free Software Foundation; either version 2 of the License, or (at your
68 +# option) any later version.
69 +#
70 +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
71 +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
72 +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
73 +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
74 +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
75 +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
76 +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
77 +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
78 +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
79 +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
80 +#
81 +# You should have received a copy of the GNU General Public License along
82 +# with this program; if not, write to the Free Software Foundation, Inc.,
83 +# 675 Mass Ave, Cambridge, MA 02139, USA.
84 +#
85 +#
86 +###############################################################################
87 +# May 2004 rkt, neb
88 +#
89 +# Initial Release
90 +#
91 +#
92 +#
93 +###############################################################################
94 +
95 +obj-y := nvram434.o
96 +obj-m := $(O_TARGET)
97 +
98 +
99 +
100 +
101 +
102 +
103 +
104 diff -Nur linux-2.6.17/arch/mips/aruba/nvram/nvram434.c linux-2.6.17-owrt/arch/mips/aruba/nvram/nvram434.c
105 --- linux-2.6.17/arch/mips/aruba/nvram/nvram434.c 1970-01-01 01:00:00.000000000 +0100
106 +++ linux-2.6.17-owrt/arch/mips/aruba/nvram/nvram434.c 2006-06-18 12:44:28.000000000 +0200
107 @@ -0,0 +1,392 @@
108 +/**************************************************************************
109 + *
110 + * BRIEF MODULE DESCRIPTION
111 + * nvram interface routines.
112 + *
113 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
114 + *
115 + * This program is free software; you can redistribute it and/or modify it
116 + * under the terms of the GNU General Public License as published by the
117 + * Free Software Foundation; either version 2 of the License, or (at your
118 + * option) any later version.
119 + *
120 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
121 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
122 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
123 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
124 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
125 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
126 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
127 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
128 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
129 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
130 + *
131 + * You should have received a copy of the GNU General Public License along
132 + * with this program; if not, write to the Free Software Foundation, Inc.,
133 + * 675 Mass Ave, Cambridge, MA 02139, USA.
134 + *
135 + *
136 + **************************************************************************
137 + * May 2004 rkt, neb
138 + *
139 + * Initial Release
140 + *
141 + *
142 + *
143 + **************************************************************************
144 + */
145 +
146 +#include <linux/ctype.h>
147 +#include <linux/string.h>
148 +
149 +//#include <asm/ds1553rtc.h>
150 +#include "nvram434.h"
151 +#define NVRAM_BASE 0xbfff8000
152 +
153 +extern void setenv (char *e, char *v, int rewrite);
154 +extern void unsetenv (char *e);
155 +extern void mapenv (int (*func)(char *, char *));
156 +extern char *getenv (char *s);
157 +extern void purgeenv(void);
158 +
159 +static void nvram_initenv(void);
160 +
161 +static unsigned char
162 +nvram_getbyte(int offs)
163 +{
164 + return(*((unsigned char*)(NVRAM_BASE + offs)));
165 +}
166 +
167 +static void
168 +nvram_setbyte(int offs, unsigned char val)
169 +{
170 + unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE + offs);
171 +
172 + *nvramDataPointer = val;
173 +}
174 +
175 +/*
176 + * BigEndian!
177 + */
178 +static unsigned short
179 +nvram_getshort(int offs)
180 +{
181 + return((nvram_getbyte(offs) << 8) | nvram_getbyte(offs + 1));
182 +}
183 +
184 +static void
185 +nvram_setshort(int offs, unsigned short val)
186 +{
187 + nvram_setbyte(offs, (unsigned char)((val >> 8) & 0xff));
188 + nvram_setbyte(offs + 1, (unsigned char)(val & 0xff));
189 +}
190 +#if 0
191 +static unsigned int
192 +nvram_getint(int offs)
193 +{
194 + unsigned int val;
195 + val = nvram_getbyte(offs) << 24;
196 + val |= nvram_getbyte(offs + 1) << 16;
197 + val |= nvram_getbyte(offs + 2) << 8;
198 + val |= nvram_getbyte(offs + 3);
199 + return(val);
200 +}
201 +
202 +static void
203 +nvram_setint(int offs, unsigned int val)
204 +{
205 + nvram_setbyte(offs, val >> 24);
206 + nvram_setbyte(offs + 1, val >> 16);
207 + nvram_setbyte(offs + 2, val >> 8);
208 + nvram_setbyte(offs + 3, val);
209 +}
210 +#endif
211 +/*
212 + * calculate NVRAM checksum
213 + */
214 +static unsigned short
215 +nvram_calcsum(void)
216 +{
217 + unsigned short sum = NV_MAGIC;
218 + int i;
219 +
220 + for (i = ENV_BASE; i < ENV_TOP; i += 2)
221 + sum += nvram_getshort(i);
222 + return(sum);
223 +}
224 +
225 +/*
226 + * update the nvram checksum
227 + */
228 +static void
229 +nvram_updatesum (void)
230 +{
231 + nvram_setshort(NVOFF_CSUM, nvram_calcsum());
232 +}
233 +
234 +/*
235 + * test validity of nvram by checksumming it
236 + */
237 +static int
238 +nvram_isvalid(void)
239 +{
240 + static int is_valid;
241 +
242 + if (is_valid)
243 + return(1);
244 +
245 + if (nvram_getshort(NVOFF_MAGIC) != NV_MAGIC) {
246 + printk("nvram_isvalid FAILED\n");
247 + //nvram_initenv();
248 + }
249 + is_valid = 1;
250 + return(1);
251 +}
252 +
253 +/* return nvram address of environment string */
254 +static int
255 +nvram_matchenv(char *s)
256 +{
257 + int envsize, envp, n, i, varsize;
258 + char *var;
259 +
260 + envsize = nvram_getshort(NVOFF_ENVSIZE);
261 +
262 + if (envsize > ENV_AVAIL)
263 + return(0); /* sanity */
264 +
265 + envp = ENV_BASE;
266 +
267 + if ((n = strlen (s)) > 255)
268 + return(0);
269 +
270 + while (envsize > 0) {
271 + varsize = nvram_getbyte(envp);
272 + if (varsize == 0 || (envp + varsize) > ENV_TOP)
273 + return(0); /* sanity */
274 + for (i = envp + 1, var = s; i <= envp + n; i++, var++) {
275 + char c1 = nvram_getbyte(i);
276 + char c2 = *var;
277 + if (islower(c1))
278 + c1 = toupper(c1);
279 + if (islower(c2))
280 + c2 = toupper(c2);
281 + if (c1 != c2)
282 + break;
283 + }
284 + if (i > envp + n) { /* match so far */
285 + if (n == varsize - 1) /* match on boolean */
286 + return(envp);
287 + if (nvram_getbyte(i) == '=') /* exact match on variable */
288 + return(envp);
289 + }
290 + envsize -= varsize;
291 + envp += varsize;
292 + }
293 + return(0);
294 +}
295 +
296 +static void nvram_initenv(void)
297 +{
298 + nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
299 + nvram_setshort(NVOFF_ENVSIZE, 0);
300 +
301 + nvram_updatesum();
302 +}
303 +
304 +static void
305 +nvram_delenv(char *s)
306 +{
307 + int nenvp, envp, envsize, nbytes;
308 +
309 + envp = nvram_matchenv(s);
310 + if (envp == 0)
311 + return;
312 +
313 + nenvp = envp + nvram_getbyte(envp);
314 + envsize = nvram_getshort(NVOFF_ENVSIZE);
315 + nbytes = envsize - (nenvp - ENV_BASE);
316 + nvram_setshort(NVOFF_ENVSIZE, envsize - (nenvp - envp));
317 + while (nbytes--) {
318 + nvram_setbyte(envp, nvram_getbyte(nenvp));
319 + envp++;
320 + nenvp++;
321 + }
322 + nvram_updatesum();
323 +}
324 +
325 +static int
326 +nvram_setenv(char *s, char *v)
327 +{
328 + int ns, nv, total;
329 + int envp;
330 +
331 + if (!nvram_isvalid())
332 + return(-1);
333 +
334 + nvram_delenv(s);
335 + ns = strlen(s);
336 + if (ns == 0)
337 + return (-1);
338 + if (v && *v) {
339 + nv = strlen(v);
340 + total = ns + nv + 2;
341 + }
342 + else {
343 + nv = 0;
344 + total = ns + 1;
345 + }
346 + if (total > 255 || total > ENV_AVAIL - nvram_getshort(NVOFF_ENVSIZE))
347 + return(-1);
348 +
349 + envp = ENV_BASE + nvram_getshort(NVOFF_ENVSIZE);
350 +
351 + nvram_setbyte(envp, (unsigned char) total);
352 + envp++;
353 +
354 + while (ns--) {
355 + nvram_setbyte(envp, *s);
356 + envp++;
357 + s++;
358 + }
359 +
360 + if (nv) {
361 + nvram_setbyte(envp, '=');
362 + envp++;
363 + while (nv--) {
364 + nvram_setbyte(envp, *v);
365 + envp++;
366 + v++;
367 + }
368 + }
369 + nvram_setshort(NVOFF_ENVSIZE, envp-ENV_BASE);
370 + nvram_updatesum();
371 + return 0;
372 +}
373 +
374 +static char *
375 +nvram_getenv(char *s)
376 +{
377 + static char buf[256]; /* FIXME: this cannot be static */
378 + int envp, ns, nbytes, i;
379 +
380 + if (!nvram_isvalid())
381 + return "INVALID NVRAM"; //((char *)0);
382 +
383 + envp = nvram_matchenv(s);
384 + if (envp == 0)
385 + return "NOT FOUND"; //((char *)0);
386 + ns = strlen(s);
387 + if (nvram_getbyte(envp) == ns + 1) /* boolean */
388 + buf[0] = '\0';
389 + else {
390 + nbytes = nvram_getbyte(envp) - (ns + 2);
391 + envp += ns + 2;
392 + for (i = 0; i < nbytes; i++)
393 + buf[i] = nvram_getbyte(envp++);
394 + buf[i] = '\0';
395 + }
396 + return(buf);
397 +}
398 +
399 +static void
400 +nvram_unsetenv(char *s)
401 +{
402 + if (!nvram_isvalid())
403 + return;
404 +
405 + nvram_delenv(s);
406 +}
407 +
408 +/*
409 + * apply func to each string in environment
410 + */
411 +static void
412 +nvram_mapenv(int (*func)(char *, char *))
413 +{
414 + int envsize, envp, n, i, seeneql;
415 + char name[256], value[256];
416 + char c, *s;
417 +
418 + if (!nvram_isvalid())
419 + return;
420 +
421 + envsize = nvram_getshort(NVOFF_ENVSIZE);
422 + envp = ENV_BASE;
423 +
424 + while (envsize > 0) {
425 + value[0] = '\0';
426 + seeneql = 0;
427 + s = name;
428 + n = nvram_getbyte(envp);
429 + for (i = envp + 1; i < envp + n; i++) {
430 + c = nvram_getbyte(i);
431 + if ((c == '=') && !seeneql) {
432 + *s = '\0';
433 + s = value;
434 + seeneql = 1;
435 + continue;
436 + }
437 + *s++ = c;
438 + }
439 + *s = '\0';
440 + (*func)(name, value);
441 + envsize -= n;
442 + envp += n;
443 + }
444 +}
445 +#if 0
446 +static unsigned int
447 +digit(char c)
448 +{
449 + if ('0' <= c && c <= '9')
450 + return (c - '0');
451 + if ('A' <= c && c <= 'Z')
452 + return (10 + c - 'A');
453 + if ('a' <= c && c <= 'z')
454 + return (10 + c - 'a');
455 + return (~0);
456 +}
457 +#endif
458 +/*
459 + * Wrappers to allow 'special' environment variables to get processed
460 + */
461 +void
462 +setenv(char *e, char *v, int rewrite)
463 +{
464 + if (nvram_getenv(e) && !rewrite)
465 + return;
466 +
467 + nvram_setenv(e, v);
468 +}
469 +
470 +char *
471 +getenv(char *e)
472 +{
473 + return(nvram_getenv(e));
474 +}
475 +
476 +void
477 +unsetenv(char *e)
478 +{
479 + nvram_unsetenv(e);
480 +}
481 +
482 +void
483 +purgeenv()
484 +{
485 + int i;
486 + unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE);
487 +
488 + for (i = ENV_BASE; i < ENV_TOP; i++)
489 + *nvramDataPointer++ = 0;
490 + nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
491 + nvram_setshort(NVOFF_ENVSIZE, 0);
492 + nvram_setshort(NVOFF_CSUM, NV_MAGIC);
493 +}
494 +
495 +void
496 +mapenv(int (*func)(char *, char *))
497 +{
498 + nvram_mapenv(func);
499 +}
500 diff -Nur linux-2.6.17/arch/mips/aruba/nvram/nvram434.h linux-2.6.17-owrt/arch/mips/aruba/nvram/nvram434.h
501 --- linux-2.6.17/arch/mips/aruba/nvram/nvram434.h 1970-01-01 01:00:00.000000000 +0100
502 +++ linux-2.6.17-owrt/arch/mips/aruba/nvram/nvram434.h 2006-06-18 12:44:28.000000000 +0200
503 @@ -0,0 +1,66 @@
504 +/**************************************************************************
505 + *
506 + * BRIEF MODULE DESCRIPTION
507 + * nvram definitions.
508 + *
509 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
510 + *
511 + * This program is free software; you can redistribute it and/or modify it
512 + * under the terms of the GNU General Public License as published by the
513 + * Free Software Foundation; either version 2 of the License, or (at your
514 + * option) any later version.
515 + *
516 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
517 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
518 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
519 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
520 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
521 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
522 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
523 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
524 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
525 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
526 + *
527 + * You should have received a copy of the GNU General Public License along
528 + * with this program; if not, write to the Free Software Foundation, Inc.,
529 + * 675 Mass Ave, Cambridge, MA 02139, USA.
530 + *
531 + *
532 + **************************************************************************
533 + * May 2004 rkt, neb
534 + *
535 + * Initial Release
536 + *
537 + *
538 + *
539 + **************************************************************************
540 + */
541 +
542 +
543 +#ifndef _NVRAM_
544 +#define _NVRAM_
545 +#define NVOFFSET 0 /* use all of NVRAM */
546 +
547 +/* Offsets to reserved locations */
548 + /* size description */
549 +#define NVOFF_MAGIC (NVOFFSET + 0) /* 2 magic value */
550 +#define NVOFF_CSUM (NVOFFSET + 2) /* 2 NVRAM environment checksum */
551 +#define NVOFF_ENVSIZE (NVOFFSET + 4) /* 2 size of 'environment' */
552 +#define NVOFF_TEST (NVOFFSET + 5) /* 1 cold start test byte */
553 +#define NVOFF_ETHADDR (NVOFFSET + 6) /* 6 decoded ethernet address */
554 +#define NVOFF_UNUSED (NVOFFSET + 12) /* 0 current end of table */
555 +
556 +#define NV_MAGIC 0xdeaf /* nvram magic number */
557 +#define NV_RESERVED 6 /* number of reserved bytes */
558 +
559 +#undef NVOFF_ETHADDR
560 +#define NVOFF_ETHADDR (NVOFFSET + NV_RESERVED - 6)
561 +
562 +/* number of bytes available for environment */
563 +#define ENV_BASE (NVOFFSET + NV_RESERVED)
564 +#define ENV_TOP 0x2000
565 +#define ENV_AVAIL (ENV_TOP - ENV_BASE)
566 +
567 +#endif /* _NVRAM_ */
568 +
569 +
570 diff -Nur linux-2.6.17/arch/mips/aruba/prom.c linux-2.6.17-owrt/arch/mips/aruba/prom.c
571 --- linux-2.6.17/arch/mips/aruba/prom.c 1970-01-01 01:00:00.000000000 +0100
572 +++ linux-2.6.17-owrt/arch/mips/aruba/prom.c 2006-06-18 12:44:28.000000000 +0200
573 @@ -0,0 +1,114 @@
574 +/**************************************************************************
575 + *
576 + * BRIEF MODULE DESCRIPTION
577 + * prom interface routines
578 + *
579 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
580 + *
581 + * This program is free software; you can redistribute it and/or modify it
582 + * under the terms of the GNU General Public License as published by the
583 + * Free Software Foundation; either version 2 of the License, or (at your
584 + * option) any later version.
585 + *
586 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
587 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
588 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
589 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
590 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
591 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
592 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
593 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
594 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
595 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
596 + *
597 + * You should have received a copy of the GNU General Public License along
598 + * with this program; if not, write to the Free Software Foundation, Inc.,
599 + * 675 Mass Ave, Cambridge, MA 02139, USA.
600 + *
601 + *
602 + **************************************************************************
603 + * May 2004 rkt, neb
604 + *
605 + * Initial Release
606 + *
607 + *
608 + *
609 + **************************************************************************
610 + */
611 +
612 +#include <linux/autoconf.h>
613 +#include <linux/init.h>
614 +#include <linux/mm.h>
615 +#include <linux/module.h>
616 +#include <linux/string.h>
617 +#include <linux/console.h>
618 +#include <asm/bootinfo.h>
619 +#include <linux/bootmem.h>
620 +#include <linux/ioport.h>
621 +#include <linux/serial.h>
622 +#include <linux/serialP.h>
623 +#include <asm/serial.h>
624 +#include <linux/ioport.h>
625 +
626 +unsigned int idt_cpu_freq;
627 +EXPORT_SYMBOL(idt_cpu_freq);
628 +
629 +unsigned int arch_has_pci=0;
630 +
631 +/* Kernel Boot parameters */
632 +static unsigned char bootparm[] =
633 + "mtdparts=physmap-flash.0:3520k@0x080000(zImage),2752k@0x140000(JFFS2),8k@0x3f8000(NVRAM) "
634 + "console=ttyS0,9600 root=/dev/mtdblock1 rootfstype=jffs2 ";
635 +
636 +
637 +extern unsigned long mips_machgroup;
638 +extern unsigned long mips_machtype;
639 +
640 +extern void setup_serial_port(void);
641 +extern char * getenv(char *e);
642 +
643 +/* IDT 79EB434 memory map -- we really should be auto sizing it */
644 +#define RAM_SIZE 32*1024*1024
645 +
646 +char *__init prom_getcmdline(void)
647 +{
648 + return &(arcs_cmdline[0]);
649 +}
650 +
651 +void __init prom_init(void)
652 +{
653 + char *boardname;
654 + sprintf(arcs_cmdline, "%s", bootparm);
655 +
656 + /* set our arch type */
657 + mips_machgroup = MACH_GROUP_ARUBA;
658 + mips_machtype = MACH_ARUBA_UNKNOWN;
659 +
660 + boardname=getenv("boardname");
661 +
662 + if (!strcmp(boardname,"Muscat")) {
663 + mips_machtype = MACH_ARUBA_AP70;
664 + idt_cpu_freq = 133000000;
665 + arch_has_pci=1;
666 + } else if (!strcmp(boardname,"Mataro")) {
667 + mips_machtype = MACH_ARUBA_AP65;
668 + idt_cpu_freq = 110000000;
669 + } else if (!strcmp(boardname,"Merlot")) {
670 + mips_machtype = MACH_ARUBA_AP60;
671 + idt_cpu_freq = 90000000;
672 + }
673 +
674 + /* turn on the console */
675 + setup_serial_port();
676 +
677 + /*
678 + * give all RAM to boot allocator,
679 + * except where the kernel was loaded
680 + */
681 + add_memory_region(0,RAM_SIZE,BOOT_MEM_RAM);
682 +}
683 +
684 +void prom_free_prom_memory(void)
685 +{
686 + printk("stubbed prom_free_prom_memory()\n");
687 +}
688 diff -Nur linux-2.6.17/arch/mips/aruba/serial.c linux-2.6.17-owrt/arch/mips/aruba/serial.c
689 --- linux-2.6.17/arch/mips/aruba/serial.c 1970-01-01 01:00:00.000000000 +0100
690 +++ linux-2.6.17-owrt/arch/mips/aruba/serial.c 2006-06-18 12:44:28.000000000 +0200
691 @@ -0,0 +1,94 @@
692 +/**************************************************************************
693 + *
694 + * BRIEF MODULE DESCRIPTION
695 + * Serial port initialisation.
696 + *
697 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
698 + *
699 + * This program is free software; you can redistribute it and/or modify it
700 + * under the terms of the GNU General Public License as published by the
701 + * Free Software Foundation; either version 2 of the License, or (at your
702 + * option) any later version.
703 + *
704 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
705 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
706 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
707 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
708 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
709 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
710 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
711 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
712 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
713 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
714 + *
715 + * You should have received a copy of the GNU General Public License along
716 + * with this program; if not, write to the Free Software Foundation, Inc.,
717 + * 675 Mass Ave, Cambridge, MA 02139, USA.
718 + *
719 + *
720 + **************************************************************************
721 + * May 2004 rkt, neb
722 + *
723 + * Initial Release
724 + *
725 + *
726 + *
727 + **************************************************************************
728 + */
729 +
730 +
731 +#include <linux/autoconf.h>
732 +#include <linux/init.h>
733 +#include <linux/sched.h>
734 +#include <linux/pci.h>
735 +#include <linux/interrupt.h>
736 +#include <linux/tty.h>
737 +#include <linux/serial.h>
738 +#include <linux/serial_core.h>
739 +
740 +#include <asm/time.h>
741 +#include <asm/cpu.h>
742 +#include <asm/bootinfo.h>
743 +#include <asm/irq.h>
744 +#include <asm/serial.h>
745 +
746 +#include <asm/idt-boards/rc32434/rc32434.h>
747 +
748 +extern int __init early_serial_setup(struct uart_port *port);
749 +
750 +#define BASE_BAUD (1843200 / 16)
751 +
752 +extern unsigned int idt_cpu_freq;
753 +
754 +extern int __init setup_serial_port(void)
755 +{
756 + static struct uart_port serial_req[2];
757 +
758 + memset(serial_req, 0, sizeof(serial_req));
759 + serial_req[0].type = PORT_16550A;
760 + serial_req[0].line = 0;
761 + serial_req[0].flags = STD_COM_FLAGS;
762 + serial_req[0].iotype = SERIAL_IO_MEM;
763 + serial_req[0].regshift = 2;
764 +
765 + switch (mips_machtype) {
766 + case MACH_ARUBA_AP70:
767 + serial_req[0].irq = 104;
768 + serial_req[0].mapbase = KSEG1ADDR(0x18058003);
769 + serial_req[0].membase = (char *) KSEG1ADDR(0x18058003);
770 + serial_req[0].uartclk = idt_cpu_freq;
771 + break;
772 + case MACH_ARUBA_AP65:
773 + case MACH_ARUBA_AP60:
774 + default:
775 + serial_req[0].irq = 12;
776 + serial_req[0].mapbase = KSEG1ADDR(0xbc000003);
777 + serial_req[0].membase = (char *) KSEG1ADDR(0xbc000003);
778 + serial_req[0].uartclk = idt_cpu_freq / 2;
779 + break;
780 + }
781 +
782 + early_serial_setup(&serial_req[0]);
783 +
784 + return(0);
785 +}
786 diff -Nur linux-2.6.17/arch/mips/aruba/setup.c linux-2.6.17-owrt/arch/mips/aruba/setup.c
787 --- linux-2.6.17/arch/mips/aruba/setup.c 1970-01-01 01:00:00.000000000 +0100
788 +++ linux-2.6.17-owrt/arch/mips/aruba/setup.c 2006-06-18 12:44:28.000000000 +0200
789 @@ -0,0 +1,128 @@
790 +/**************************************************************************
791 + *
792 + * BRIEF MODULE DESCRIPTION
793 + * setup routines for IDT EB434 boards
794 + *
795 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
796 + *
797 + * This program is free software; you can redistribute it and/or modify it
798 + * under the terms of the GNU General Public License as published by the
799 + * Free Software Foundation; either version 2 of the License, or (at your
800 + * option) any later version.
801 + *
802 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
803 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
804 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
805 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
806 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
807 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
808 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
809 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
810 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
811 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
812 + *
813 + * You should have received a copy of the GNU General Public License along
814 + * with this program; if not, write to the Free Software Foundation, Inc.,
815 + * 675 Mass Ave, Cambridge, MA 02139, USA.
816 + *
817 + *
818 + **************************************************************************
819 + * May 2004 rkt, neb
820 + *
821 + * Initial Release
822 + *
823 + *
824 + *
825 + **************************************************************************
826 + */
827 +
828 +#include <linux/init.h>
829 +#include <linux/module.h>
830 +#include <linux/mm.h>
831 +#include <linux/sched.h>
832 +#include <linux/irq.h>
833 +#include <asm/bootinfo.h>
834 +#include <asm/io.h>
835 +#include <linux/ioport.h>
836 +#include <asm/mipsregs.h>
837 +#include <asm/pgtable.h>
838 +#include <asm/reboot.h>
839 +#include <asm/addrspace.h> /* for KSEG1ADDR() */
840 +#include <asm/idt-boards/rc32434/rc32434.h>
841 +#include <linux/pm.h>
842 +
843 +extern char *__init prom_getcmdline(void);
844 +
845 +extern void (*board_time_init) (void);
846 +extern void aruba_time_init(void);
847 +extern void aruba_reset(void);
848 +
849 +#define epldMask ((volatile unsigned char *)0xB900000d)
850 +
851 +static void aruba_machine_restart(char *command)
852 +{
853 + switch (mips_machtype) {
854 + case MACH_ARUBA_AP70:
855 + *(volatile u32 *)KSEG1ADDR(0x18008000) = 0x80000001;
856 + break;
857 + case MACH_ARUBA_AP65:
858 + case MACH_ARUBA_AP60:
859 + default:
860 + /* Reset*/
861 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x00080350; // reset everything in sight
862 + udelay(100);
863 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0; // reset everything in sight
864 + udelay(100);
865 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x3; // cold reset the cpu & system
866 + break;
867 + }
868 +}
869 +
870 +static void aruba_machine_halt(void)
871 +{
872 + for (;;) continue;
873 +}
874 +
875 +extern char * getenv(char *e);
876 +extern void unlock_ap60_70_flash(void);
877 +
878 +void __init plat_mem_setup(void)
879 +{
880 + board_time_init = aruba_time_init;
881 +
882 + _machine_restart = aruba_machine_restart;
883 + _machine_halt = aruba_machine_halt;
884 + pm_power_off = aruba_machine_halt;
885 +
886 + set_io_port_base(KSEG1);
887 +
888 + /* Enable PCI interrupts in EPLD Mask register */
889 + *epldMask = 0x0;
890 + *(epldMask + 1) = 0x0;
891 +
892 + write_c0_wired(0);
893 + unlock_ap60_70_flash();
894 +
895 + printk("BOARD - %s\n",getenv("boardname"));
896 +}
897 +
898 +int page_is_ram(unsigned long pagenr)
899 +{
900 + return 1;
901 +}
902 +
903 +const char *get_system_type(void)
904 +{
905 + switch (mips_machtype) {
906 + case MACH_ARUBA_AP70:
907 + return "Aruba AP70";
908 + case MACH_ARUBA_AP65:
909 + return "Aruba AP65";
910 + case MACH_ARUBA_AP60:
911 + return "Aruba AP60/AP61";
912 + default:
913 + return "Aruba UNKNOWN";
914 + }
915 +}
916 +
917 +EXPORT_SYMBOL(get_system_type);
918 diff -Nur linux-2.6.17/arch/mips/aruba/time.c linux-2.6.17-owrt/arch/mips/aruba/time.c
919 --- linux-2.6.17/arch/mips/aruba/time.c 1970-01-01 01:00:00.000000000 +0100
920 +++ linux-2.6.17-owrt/arch/mips/aruba/time.c 2006-06-18 12:44:28.000000000 +0200
921 @@ -0,0 +1,110 @@
922 +/**************************************************************************
923 + *
924 + * BRIEF MODULE DESCRIPTION
925 + * timer routines for IDT EB434 boards
926 + *
927 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
928 + *
929 + * This program is free software; you can redistribute it and/or modify it
930 + * under the terms of the GNU General Public License as published by the
931 + * Free Software Foundation; either version 2 of the License, or (at your
932 + * option) any later version.
933 + *
934 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
935 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
936 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
937 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
938 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
939 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
940 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
941 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
942 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
943 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
944 + *
945 + * You should have received a copy of the GNU General Public License along
946 + * with this program; if not, write to the Free Software Foundation, Inc.,
947 + * 675 Mass Ave, Cambridge, MA 02139, USA.
948 + *
949 + *
950 + **************************************************************************
951 + * May 2004 rkt, neb
952 + *
953 + * Initial Release
954 + *
955 + *
956 + *
957 + **************************************************************************
958 + */
959 +
960 +#include <linux/autoconf.h>
961 +#include <linux/init.h>
962 +#include <linux/kernel_stat.h>
963 +#include <linux/sched.h>
964 +#include <linux/spinlock.h>
965 +#include <linux/mc146818rtc.h>
966 +#include <linux/irq.h>
967 +#include <linux/timex.h>
968 +
969 +#include <linux/param.h>
970 +#include <asm/mipsregs.h>
971 +#include <asm/ptrace.h>
972 +#include <asm/time.h>
973 +#include <asm/hardirq.h>
974 +
975 +#include <asm/mipsregs.h>
976 +#include <asm/ptrace.h>
977 +#include <asm/debug.h>
978 +#include <asm/time.h>
979 +
980 +#include <asm/idt-boards/rc32434/rc32434.h>
981 +
982 +static unsigned long r4k_offset; /* Amount to incr compare reg each time */
983 +static unsigned long r4k_cur; /* What counter should be at next timer irq */
984 +
985 +extern unsigned int idt_cpu_freq;
986 +
987 +static unsigned long __init cal_r4koff(void)
988 +{
989 + mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
990 + return (mips_hpt_frequency / HZ);
991 +}
992 +
993 +void __init aruba_time_init(void)
994 +{
995 + unsigned int est_freq, flags;
996 + local_irq_save(flags);
997 +
998 + printk("calculating r4koff... ");
999 + r4k_offset = cal_r4koff();
1000 + printk("%08lx(%d)\n", r4k_offset, (int)r4k_offset);
1001 +
1002 + est_freq = 2 * r4k_offset * HZ;
1003 + est_freq += 5000; /* round */
1004 + est_freq -= est_freq % 10000;
1005 + printk("CPU frequency %d.%02d MHz\n", est_freq / 1000000,
1006 + (est_freq % 1000000) * 100 / 1000000);
1007 + local_irq_restore(flags);
1008 +
1009 +}
1010 +
1011 +void __init plat_timer_setup(struct irqaction *irq)
1012 +{
1013 + /* we are using the cpu counter for timer interrupts */
1014 + setup_irq(MIPS_CPU_TIMER_IRQ, irq);
1015 +
1016 + /* to generate the first timer interrupt */
1017 + r4k_cur = (read_c0_count() + r4k_offset);
1018 + write_c0_compare(r4k_cur);
1019 +
1020 +}
1021 +
1022 +asmlinkage void aruba_timer_interrupt(struct pt_regs *regs)
1023 +{
1024 + int irq = MIPS_CPU_TIMER_IRQ;
1025 +
1026 + irq_enter();
1027 + kstat_this_cpu.irqs[irq]++;
1028 +
1029 + timer_interrupt(irq, NULL);
1030 + irq_exit();
1031 +}
1032 diff -Nur linux-2.6.17/arch/mips/Kconfig linux-2.6.17-owrt/arch/mips/Kconfig
1033 --- linux-2.6.17/arch/mips/Kconfig 2006-06-18 03:49:35.000000000 +0200
1034 +++ linux-2.6.17-owrt/arch/mips/Kconfig 2006-06-18 12:44:28.000000000 +0200
1035 @@ -227,6 +227,17 @@
1036 either a NEC Vr5432 or QED RM5231. Say Y here if you wish to build
1037 a kernel for this platform.
1038
1039 +config MACH_ARUBA
1040 + bool "Support for the ARUBA product line"
1041 + select DMA_NONCOHERENT
1042 + select CPU_HAS_PREFETCH
1043 + select HW_HAS_PCI
1044 + select SWAP_IO_SPACE
1045 + select SYS_SUPPORTS_32BIT_KERNEL
1046 + select SYS_HAS_CPU_MIPS32_R1
1047 + select SYS_SUPPORTS_BIG_ENDIAN
1048 +
1049 +
1050 config MACH_JAZZ
1051 bool "Jazz family of machines"
1052 select ARC
1053 diff -Nur linux-2.6.17/arch/mips/Makefile linux-2.6.17-owrt/arch/mips/Makefile
1054 --- linux-2.6.17/arch/mips/Makefile 2006-06-18 03:49:35.000000000 +0200
1055 +++ linux-2.6.17-owrt/arch/mips/Makefile 2006-06-18 12:44:28.000000000 +0200
1056 @@ -145,6 +145,14 @@
1057 #
1058
1059 #
1060 +# Aruba
1061 +#
1062 +
1063 +core-$(CONFIG_MACH_ARUBA) += arch/mips/aruba/
1064 +cflags-$(CONFIG_MACH_ARUBA) += -Iinclude/asm-mips/aruba
1065 +load-$(CONFIG_MACH_ARUBA) += 0x80100000
1066 +
1067 +#
1068 # Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
1069 #
1070 core-$(CONFIG_MACH_JAZZ) += arch/mips/jazz/
1071 diff -Nur linux-2.6.17/arch/mips/mm/tlbex.c linux-2.6.17-owrt/arch/mips/mm/tlbex.c
1072 --- linux-2.6.17/arch/mips/mm/tlbex.c 2006-06-18 03:49:35.000000000 +0200
1073 +++ linux-2.6.17-owrt/arch/mips/mm/tlbex.c 2006-06-18 12:48:27.000000000 +0200
1074 @@ -876,7 +876,6 @@
1075 case CPU_R10000:
1076 case CPU_R12000:
1077 case CPU_R14000:
1078 - case CPU_4KC:
1079 case CPU_SB1:
1080 case CPU_SB1A:
1081 case CPU_4KSC:
1082 @@ -904,6 +903,7 @@
1083 tlbw(p);
1084 break;
1085
1086 + case CPU_4KC:
1087 case CPU_4KEC:
1088 case CPU_24K:
1089 case CPU_34K:
1090 diff -Nur linux-2.6.17/drivers/net/Kconfig linux-2.6.17-owrt/drivers/net/Kconfig
1091 --- linux-2.6.17/drivers/net/Kconfig 2006-06-18 03:49:35.000000000 +0200
1092 +++ linux-2.6.17-owrt/drivers/net/Kconfig 2006-06-18 12:44:28.000000000 +0200
1093 @@ -187,6 +187,13 @@
1094
1095 source "drivers/net/arm/Kconfig"
1096
1097 +config IDT_RC32434_ETH
1098 + tristate "IDT RC32434 Local Ethernet support"
1099 + depends on NET_ETHERNET
1100 + help
1101 + IDT RC32434 has one local ethernet port. Say Y here to enable it.
1102 + To compile this driver as a module, choose M here.
1103 +
1104 config MACE
1105 tristate "MACE (Power Mac ethernet) support"
1106 depends on NET_ETHERNET && PPC_PMAC && PPC32
1107 diff -Nur linux-2.6.17/drivers/net/Makefile linux-2.6.17-owrt/drivers/net/Makefile
1108 --- linux-2.6.17/drivers/net/Makefile 2006-06-18 03:49:35.000000000 +0200
1109 +++ linux-2.6.17-owrt/drivers/net/Makefile 2006-06-18 12:44:28.000000000 +0200
1110 @@ -38,6 +38,7 @@
1111
1112 obj-$(CONFIG_OAKNET) += oaknet.o 8390.o
1113
1114 +obj-$(CONFIG_IDT_RC32434_ETH) += rc32434_eth.o
1115 obj-$(CONFIG_DGRS) += dgrs.o
1116 obj-$(CONFIG_VORTEX) += 3c59x.o
1117 obj-$(CONFIG_TYPHOON) += typhoon.o
1118 diff -Nur linux-2.6.17/drivers/net/natsemi.c linux-2.6.17-owrt/drivers/net/natsemi.c
1119 --- linux-2.6.17/drivers/net/natsemi.c 2006-06-18 03:49:35.000000000 +0200
1120 +++ linux-2.6.17-owrt/drivers/net/natsemi.c 2006-06-18 12:44:28.000000000 +0200
1121 @@ -771,6 +771,49 @@
1122 static int netdev_get_eeprom(struct net_device *dev, u8 *buf);
1123 static struct ethtool_ops ethtool_ops;
1124
1125 +#ifdef CONFIG_MACH_ARUBA
1126 +
1127 +#include <linux/ctype.h>
1128 +
1129 +#ifndef ERR
1130 +#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
1131 +#endif
1132 +
1133 +static int parse_mac_addr(struct net_device *dev, char* macstr)
1134 +{
1135 + int i, j;
1136 + unsigned char result, value;
1137 +
1138 + for (i=0; i<6; i++) {
1139 + result = 0;
1140 + if (i != 5 && *(macstr+2) != ':') {
1141 + ERR("invalid mac address format: %d %c\n",
1142 + i, *(macstr+2));
1143 + return -EINVAL;
1144 + }
1145 + for (j=0; j<2; j++) {
1146 + if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
1147 + toupper(*macstr)-'A'+10) < 16) {
1148 + result = result*16 + value;
1149 + macstr++;
1150 + }
1151 + else {
1152 + ERR("invalid mac address "
1153 + "character: %c\n", *macstr);
1154 + return -EINVAL;
1155 + }
1156 + }
1157 +
1158 + macstr++;
1159 + dev->dev_addr[i] = result;
1160 + }
1161 +
1162 + dev->dev_addr[5]++;
1163 + return 0;
1164 +}
1165 +
1166 +#endif
1167 +
1168 static inline void __iomem *ns_ioaddr(struct net_device *dev)
1169 {
1170 return (void __iomem *) dev->base_addr;
1171 @@ -871,6 +914,7 @@
1172 goto err_ioremap;
1173 }
1174
1175 +#ifndef CONFIG_MACH_ARUBA
1176 /* Work around the dropped serial bit. */
1177 prev_eedata = eeprom_read(ioaddr, 6);
1178 for (i = 0; i < 3; i++) {
1179 @@ -879,6 +923,19 @@
1180 dev->dev_addr[i*2+1] = eedata >> 7;
1181 prev_eedata = eedata;
1182 }
1183 +#else
1184 + {
1185 + char mac[32];
1186 + unsigned char def_mac[6] = {00, 0x0b, 0x86, 0xba, 0xdb, 0xad};
1187 + extern char *getenv(char *e);
1188 + memset(mac, 0, 32);
1189 + memcpy(mac, getenv("ethaddr"), 17);
1190 + if (parse_mac_addr(dev, mac)){
1191 + printk("%s: MAC address not found\n", __func__);
1192 + memcpy(dev->dev_addr, def_mac, 6);
1193 + }
1194 + }
1195 +#endif
1196
1197 dev->base_addr = (unsigned long __force) ioaddr;
1198 dev->irq = irq;
1199 diff -Nur linux-2.6.17/drivers/net/rc32434_eth.c linux-2.6.17-owrt/drivers/net/rc32434_eth.c
1200 --- linux-2.6.17/drivers/net/rc32434_eth.c 1970-01-01 01:00:00.000000000 +0100
1201 +++ linux-2.6.17-owrt/drivers/net/rc32434_eth.c 2006-06-18 12:44:28.000000000 +0200
1202 @@ -0,0 +1,1273 @@
1203 +/**************************************************************************
1204 + *
1205 + * BRIEF MODULE DESCRIPTION
1206 + * Driver for the IDT RC32434 on-chip ethernet controller.
1207 + *
1208 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
1209 + *
1210 + * This program is free software; you can redistribute it and/or modify it
1211 + * under the terms of the GNU General Public License as published by the
1212 + * Free Software Foundation; either version 2 of the License, or (at your
1213 + * option) any later version.
1214 + *
1215 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1216 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1217 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1218 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1219 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1220 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1221 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1222 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1223 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1224 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1225 + *
1226 + * You should have received a copy of the GNU General Public License along
1227 + * with this program; if not, write to the Free Software Foundation, Inc.,
1228 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1229 + *
1230 + *
1231 + **************************************************************************
1232 + * May 2004 rkt, neb
1233 + *
1234 + * Based on the driver developed by B. Maruthanayakam, H. Kou and others.
1235 + *
1236 + * Aug 2004 Sadik
1237 + *
1238 + * Added NAPI
1239 + *
1240 + **************************************************************************
1241 + */
1242 +
1243 +#include <linux/autoconf.h>
1244 +#include <linux/version.h>
1245 +#include <linux/module.h>
1246 +#include <linux/kernel.h>
1247 +#include <linux/moduleparam.h>
1248 +#include <linux/sched.h>
1249 +#include <linux/ctype.h>
1250 +#include <linux/types.h>
1251 +#include <linux/fcntl.h>
1252 +#include <linux/interrupt.h>
1253 +#include <linux/ptrace.h>
1254 +#include <linux/init.h>
1255 +#include <linux/ioport.h>
1256 +#include <linux/proc_fs.h>
1257 +#include <linux/in.h>
1258 +#include <linux/slab.h>
1259 +#include <linux/string.h>
1260 +#include <linux/delay.h>
1261 +#include <linux/netdevice.h>
1262 +#include <linux/etherdevice.h>
1263 +#include <linux/skbuff.h>
1264 +#include <linux/errno.h>
1265 +#include <asm/bootinfo.h>
1266 +#include <asm/system.h>
1267 +#include <asm/bitops.h>
1268 +#include <asm/pgtable.h>
1269 +#include <asm/segment.h>
1270 +#include <asm/io.h>
1271 +#include <asm/dma.h>
1272 +
1273 +#include "rc32434_eth.h"
1274 +
1275 +#define DRIVER_VERSION "(mar2904)"
1276 +
1277 +#define DRIVER_NAME "rc32434 Ethernet driver. " DRIVER_VERSION
1278 +
1279 +
1280 +#define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \
1281 + ((dev)->dev_addr[1]))
1282 +#define STATION_ADDRESS_LOW(dev) (((dev)->dev_addr[2] << 24) | \
1283 + ((dev)->dev_addr[3] << 16) | \
1284 + ((dev)->dev_addr[4] << 8) | \
1285 + ((dev)->dev_addr[5]))
1286 +
1287 +#define MII_CLOCK 1250000 /* no more than 2.5MHz */
1288 +static char mac0[18] = "08:00:06:05:40:01";
1289 +
1290 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,52)
1291 +module_param_string(mac0, mac0, 18, 0);
1292 +#else
1293 +MODULE_PARM(mac0, "c18");
1294 +#endif
1295 +MODULE_PARM_DESC(mac0, "MAC address for RC32434 ethernet0");
1296 +
1297 +static struct rc32434_if_t {
1298 + char *name;
1299 + struct net_device *dev;
1300 + char* mac_str;
1301 + int weight;
1302 + u32 iobase;
1303 + u32 rxdmabase;
1304 + u32 txdmabase;
1305 + int rx_dma_irq;
1306 + int tx_dma_irq;
1307 + int rx_ovr_irq;
1308 + int tx_und_irq;
1309 +} rc32434_iflist[] =
1310 +{
1311 + {
1312 + "rc32434_eth0", NULL, mac0,
1313 + 64,
1314 + ETH0_PhysicalAddress,
1315 + ETH0_RX_DMA_ADDR,
1316 + ETH0_TX_DMA_ADDR,
1317 + ETH0_DMA_RX_IRQ,
1318 + ETH0_DMA_TX_IRQ,
1319 + ETH0_RX_OVR_IRQ,
1320 + ETH0_TX_UND_IRQ
1321 + }
1322 +};
1323 +
1324 +
1325 +static int parse_mac_addr(struct net_device *dev, char* macstr)
1326 +{
1327 + int i, j;
1328 + unsigned char result, value;
1329 +
1330 + for (i=0; i<6; i++) {
1331 + result = 0;
1332 + if (i != 5 && *(macstr+2) != ':') {
1333 + ERR("invalid mac address format: %d %c\n",
1334 + i, *(macstr+2));
1335 + return -EINVAL;
1336 + }
1337 + for (j=0; j<2; j++) {
1338 + if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
1339 + toupper(*macstr)-'A'+10) < 16) {
1340 + result = result*16 + value;
1341 + macstr++;
1342 + }
1343 + else {
1344 + ERR("invalid mac address "
1345 + "character: %c\n", *macstr);
1346 + return -EINVAL;
1347 + }
1348 + }
1349 +
1350 + macstr++;
1351 + dev->dev_addr[i] = result;
1352 + }
1353 +
1354 + return 0;
1355 +}
1356 +
1357 +
1358 +
1359 +static inline void rc32434_abort_tx(struct net_device *dev)
1360 +{
1361 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1362 + rc32434_abort_dma(dev, lp->tx_dma_regs);
1363 +
1364 +}
1365 +
1366 +static inline void rc32434_abort_rx(struct net_device *dev)
1367 +{
1368 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1369 + rc32434_abort_dma(dev, lp->rx_dma_regs);
1370 +
1371 +}
1372 +
1373 +static inline void rc32434_start_tx(struct rc32434_local *lp, volatile DMAD_t td)
1374 +{
1375 + rc32434_start_dma(lp->tx_dma_regs, CPHYSADDR(td));
1376 +}
1377 +
1378 +static inline void rc32434_start_rx(struct rc32434_local *lp, volatile DMAD_t rd)
1379 +{
1380 + rc32434_start_dma(lp->rx_dma_regs, CPHYSADDR(rd));
1381 +}
1382 +
1383 +static inline void rc32434_chain_tx(struct rc32434_local *lp, volatile DMAD_t td)
1384 +{
1385 + rc32434_chain_dma(lp->tx_dma_regs, CPHYSADDR(td));
1386 +}
1387 +
1388 +static inline void rc32434_chain_rx(struct rc32434_local *lp, volatile DMAD_t rd)
1389 +{
1390 + rc32434_chain_dma(lp->rx_dma_regs, CPHYSADDR(rd));
1391 +}
1392 +
1393 +#ifdef RC32434_PROC_DEBUG
1394 +static int rc32434_read_proc(char *buf, char **start, off_t fpos,
1395 + int length, int *eof, void *data)
1396 +{
1397 + struct net_device *dev = (struct net_device *)data;
1398 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1399 + int len = 0;
1400 +
1401 + /* print out header */
1402 + len += sprintf(buf + len, "\n\tRC32434 Ethernet Debug\n\n");
1403 + len += sprintf (buf + len,
1404 + "DMA halt count = %10d, DMA run count = %10d\n",
1405 + lp->dma_halt_cnt, lp->dma_run_cnt);
1406 +
1407 + if (fpos >= len) {
1408 + *start = buf;
1409 + *eof = 1;
1410 + return 0;
1411 + }
1412 + *start = buf + fpos;
1413 +
1414 + if ((len -= fpos) > length)
1415 + return length;
1416 + *eof = 1;
1417 +
1418 + return len;
1419 +
1420 +}
1421 +#endif
1422 +
1423 +
1424 +/*
1425 + * Restart the RC32434 ethernet controller.
1426 + */
1427 +static int rc32434_restart(struct net_device *dev)
1428 +{
1429 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1430 +
1431 + /*
1432 + * Disable interrupts
1433 + */
1434 + disable_irq(lp->rx_irq);
1435 + disable_irq(lp->tx_irq);
1436 +#ifdef RC32434_REVISION
1437 + disable_irq(lp->ovr_irq);
1438 +#endif
1439 + disable_irq(lp->und_irq);
1440 +
1441 + /* Mask F E bit in Tx DMA */
1442 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) | DMASM_f_m | DMASM_e_m, &lp->tx_dma_regs->dmasm);
1443 + /* Mask D H E bit in Rx DMA */
1444 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) | DMASM_d_m | DMASM_h_m | DMASM_e_m, &lp->rx_dma_regs->dmasm);
1445 +
1446 + rc32434_init(dev);
1447 + rc32434_multicast_list(dev);
1448 +
1449 + enable_irq(lp->und_irq);
1450 +#ifdef RC32434_REVISION
1451 + enable_irq(lp->ovr_irq);
1452 +#endif
1453 + enable_irq(lp->tx_irq);
1454 + enable_irq(lp->rx_irq);
1455 +
1456 + return 0;
1457 +}
1458 +
1459 +int rc32434_init_module(void)
1460 +{
1461 +#ifdef CONFIG_MACH_ARUBA
1462 + if (mips_machtype != MACH_ARUBA_AP70)
1463 + return 1;
1464 +#endif
1465 +
1466 + printk(KERN_INFO DRIVER_NAME " \n");
1467 + return rc32434_probe(0);
1468 +}
1469 +
1470 +static int rc32434_probe(int port_num)
1471 +{
1472 + struct rc32434_if_t *bif = &rc32434_iflist[port_num];
1473 + struct rc32434_local *lp = NULL;
1474 + struct net_device *dev = NULL;
1475 + int i, retval,err;
1476 +
1477 + dev = alloc_etherdev(sizeof(struct rc32434_local));
1478 + if(!dev) {
1479 + ERR("rc32434_eth: alloc_etherdev failed\n");
1480 + return -1;
1481 + }
1482 +
1483 + SET_MODULE_OWNER(dev);
1484 + bif->dev = dev;
1485 +
1486 +#ifdef CONFIG_MACH_ARUBA
1487 + {
1488 + extern char * getenv(char *e);
1489 + memcpy(bif->mac_str, getenv("ethaddr"), 17);
1490 + }
1491 +#endif
1492 +
1493 + printk("mac: %s\n", bif->mac_str);
1494 + if ((retval = parse_mac_addr(dev, bif->mac_str))) {
1495 + ERR("MAC address parse failed\n");
1496 + free_netdev(dev);
1497 + return -1;
1498 + }
1499 +
1500 +
1501 + /* Initialize the device structure. */
1502 + if (dev->priv == NULL) {
1503 + lp = (struct rc32434_local *)kmalloc(sizeof(*lp), GFP_KERNEL);
1504 + memset(lp, 0, sizeof(struct rc32434_local));
1505 + }
1506 + else {
1507 + lp = (struct rc32434_local *)dev->priv;
1508 + }
1509 +
1510 + lp->rx_irq = bif->rx_dma_irq;
1511 + lp->tx_irq = bif->tx_dma_irq;
1512 + lp->ovr_irq = bif->rx_ovr_irq;
1513 + lp->und_irq = bif->tx_und_irq;
1514 +
1515 + lp->eth_regs = ioremap_nocache(bif->iobase, sizeof(*lp->eth_regs));
1516 +
1517 + if (!lp->eth_regs) {
1518 + ERR("Can't remap eth registers\n");
1519 + retval = -ENXIO;
1520 + goto probe_err_out;
1521 + }
1522 +
1523 + lp->rx_dma_regs = ioremap_nocache(bif->rxdmabase, sizeof(struct DMA_Chan_s));
1524 +
1525 + if (!lp->rx_dma_regs) {
1526 + ERR("Can't remap Rx DMA registers\n");
1527 + retval = -ENXIO;
1528 + goto probe_err_out;
1529 + }
1530 + lp->tx_dma_regs = ioremap_nocache(bif->txdmabase,sizeof(struct DMA_Chan_s));
1531 +
1532 + if (!lp->tx_dma_regs) {
1533 + ERR("Can't remap Tx DMA registers\n");
1534 + retval = -ENXIO;
1535 + goto probe_err_out;
1536 + }
1537 +
1538 +#ifdef RC32434_PROC_DEBUG
1539 + lp->ps = create_proc_read_entry (bif->name, 0, proc_net,
1540 + rc32434_read_proc, dev);
1541 +#endif
1542 +
1543 + lp->td_ring = (DMAD_t)kmalloc(TD_RING_SIZE + RD_RING_SIZE, GFP_KERNEL);
1544 + if (!lp->td_ring) {
1545 + ERR("Can't allocate descriptors\n");
1546 + retval = -ENOMEM;
1547 + goto probe_err_out;
1548 + }
1549 +
1550 + dma_cache_inv((unsigned long)(lp->td_ring), TD_RING_SIZE + RD_RING_SIZE);
1551 +
1552 + /* now convert TD_RING pointer to KSEG1 */
1553 + lp->td_ring = (DMAD_t )KSEG1ADDR(lp->td_ring);
1554 + lp->rd_ring = &lp->td_ring[RC32434_NUM_TDS];
1555 +
1556 +
1557 + spin_lock_init(&lp->lock);
1558 +
1559 + dev->base_addr = bif->iobase;
1560 + /* just use the rx dma irq */
1561 + dev->irq = bif->rx_dma_irq;
1562 +
1563 + dev->priv = lp;
1564 +
1565 + dev->open = rc32434_open;
1566 + dev->stop = rc32434_close;
1567 + dev->hard_start_xmit = rc32434_send_packet;
1568 + dev->get_stats = rc32434_get_stats;
1569 + dev->set_multicast_list = &rc32434_multicast_list;
1570 + dev->tx_timeout = rc32434_tx_timeout;
1571 + dev->watchdog_timeo = RC32434_TX_TIMEOUT;
1572 +
1573 +#ifdef CONFIG_IDT_USE_NAPI
1574 + dev->poll = rc32434_poll;
1575 + dev->weight = bif->weight;
1576 + printk("Using NAPI with weight %d\n",dev->weight);
1577 +#else
1578 + lp->rx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
1579 + tasklet_init(lp->rx_tasklet, rc32434_rx_tasklet, (unsigned long)dev);
1580 +#endif
1581 + lp->tx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
1582 + tasklet_init(lp->tx_tasklet, rc32434_tx_tasklet, (unsigned long)dev);
1583 +
1584 + if ((err = register_netdev(dev))) {
1585 + printk(KERN_ERR "rc32434 ethernet. Cannot register net device %d\n", err);
1586 + free_netdev(dev);
1587 + retval = -EINVAL;
1588 + goto probe_err_out;
1589 + }
1590 +
1591 + INFO("Rx IRQ %d, Tx IRQ %d, ", bif->rx_dma_irq, bif->tx_dma_irq);
1592 + for (i = 0; i < 6; i++) {
1593 + printk("%2.2x", dev->dev_addr[i]);
1594 + if (i<5)
1595 + printk(":");
1596 + }
1597 + printk("\n");
1598 +
1599 + return 0;
1600 +
1601 + probe_err_out:
1602 + rc32434_cleanup_module();
1603 + ERR(" failed. Returns %d\n", retval);
1604 + return retval;
1605 +
1606 +}
1607 +
1608 +
1609 +static void rc32434_cleanup_module(void)
1610 +{
1611 + int i;
1612 +
1613 + for (i = 0; rc32434_iflist[i].iobase; i++) {
1614 + struct rc32434_if_t * bif = &rc32434_iflist[i];
1615 + if (bif->dev != NULL) {
1616 + struct rc32434_local *lp = (struct rc32434_local *)bif->dev->priv;
1617 + if (lp != NULL) {
1618 + if (lp->eth_regs)
1619 + iounmap((void*)lp->eth_regs);
1620 + if (lp->rx_dma_regs)
1621 + iounmap((void*)lp->rx_dma_regs);
1622 + if (lp->tx_dma_regs)
1623 + iounmap((void*)lp->tx_dma_regs);
1624 + if (lp->td_ring)
1625 + kfree((void*)KSEG0ADDR(lp->td_ring));
1626 +
1627 +#ifdef RC32434_PROC_DEBUG
1628 + if (lp->ps) {
1629 + remove_proc_entry(bif->name, proc_net);
1630 + }
1631 +#endif
1632 + kfree(lp);
1633 + }
1634 +
1635 + unregister_netdev(bif->dev);
1636 + free_netdev(bif->dev);
1637 + kfree(bif->dev);
1638 + }
1639 + }
1640 +}
1641 +
1642 +
1643 +
1644 +static int rc32434_open(struct net_device *dev)
1645 +{
1646 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1647 +
1648 + /* Initialize */
1649 + if (rc32434_init(dev)) {
1650 + ERR("Error: cannot open the Ethernet device\n");
1651 + return -EAGAIN;
1652 + }
1653 +
1654 + /* Install the interrupt handler that handles the Done Finished Ovr and Und Events */
1655 + if (request_irq(lp->rx_irq, &rc32434_rx_dma_interrupt,
1656 + SA_SHIRQ | SA_INTERRUPT,
1657 + "rc32434 ethernet Rx", dev)) {
1658 + ERR(": unable to get Rx DMA IRQ %d\n",
1659 + lp->rx_irq);
1660 + return -EAGAIN;
1661 + }
1662 + if (request_irq(lp->tx_irq, &rc32434_tx_dma_interrupt,
1663 + SA_SHIRQ | SA_INTERRUPT,
1664 + "rc32434 ethernet Tx", dev)) {
1665 + ERR(": unable to get Tx DMA IRQ %d\n",
1666 + lp->tx_irq);
1667 + free_irq(lp->rx_irq, dev);
1668 + return -EAGAIN;
1669 + }
1670 +
1671 +#ifdef RC32434_REVISION
1672 + /* Install handler for overrun error. */
1673 + if (request_irq(lp->ovr_irq, &rc32434_ovr_interrupt,
1674 + SA_SHIRQ | SA_INTERRUPT,
1675 + "Ethernet Overflow", dev)) {
1676 + ERR(": unable to get OVR IRQ %d\n",
1677 + lp->ovr_irq);
1678 + free_irq(lp->rx_irq, dev);
1679 + free_irq(lp->tx_irq, dev);
1680 + return -EAGAIN;
1681 + }
1682 +#endif
1683 +
1684 + /* Install handler for underflow error. */
1685 + if (request_irq(lp->und_irq, &rc32434_und_interrupt,
1686 + SA_SHIRQ | SA_INTERRUPT,
1687 + "Ethernet Underflow", dev)) {
1688 + ERR(": unable to get UND IRQ %d\n",
1689 + lp->und_irq);
1690 + free_irq(lp->rx_irq, dev);
1691 + free_irq(lp->tx_irq, dev);
1692 +#ifdef RC32434_REVISION
1693 + free_irq(lp->ovr_irq, dev);
1694 +#endif
1695 + return -EAGAIN;
1696 + }
1697 +
1698 +
1699 + return 0;
1700 +}
1701 +
1702 +
1703 +
1704 +
1705 +static int rc32434_close(struct net_device *dev)
1706 +{
1707 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1708 + u32 tmp;
1709 +
1710 + /* Disable interrupts */
1711 + disable_irq(lp->rx_irq);
1712 + disable_irq(lp->tx_irq);
1713 +#ifdef RC32434_REVISION
1714 + disable_irq(lp->ovr_irq);
1715 +#endif
1716 + disable_irq(lp->und_irq);
1717 +
1718 + tmp = rc32434_readl(&lp->tx_dma_regs->dmasm);
1719 + tmp = tmp | DMASM_f_m | DMASM_e_m;
1720 + rc32434_writel(tmp, &lp->tx_dma_regs->dmasm);
1721 +
1722 + tmp = rc32434_readl(&lp->rx_dma_regs->dmasm);
1723 + tmp = tmp | DMASM_d_m | DMASM_h_m | DMASM_e_m;
1724 + rc32434_writel(tmp, &lp->rx_dma_regs->dmasm);
1725 +
1726 + free_irq(lp->rx_irq, dev);
1727 + free_irq(lp->tx_irq, dev);
1728 +#ifdef RC32434_REVISION
1729 + free_irq(lp->ovr_irq, dev);
1730 +#endif
1731 + free_irq(lp->und_irq, dev);
1732 + return 0;
1733 +}
1734 +
1735 +
1736 +/* transmit packet */
1737 +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev)
1738 +{
1739 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1740 + unsigned long flags;
1741 + u32 length;
1742 + DMAD_t td;
1743 +
1744 +
1745 + spin_lock_irqsave(&lp->lock, flags);
1746 +
1747 + td = &lp->td_ring[lp->tx_chain_tail];
1748 +
1749 + /* stop queue when full, drop pkts if queue already full */
1750 + if(lp->tx_count >= (RC32434_NUM_TDS - 2)) {
1751 + lp->tx_full = 1;
1752 +
1753 + if(lp->tx_count == (RC32434_NUM_TDS - 2)) {
1754 + netif_stop_queue(dev);
1755 + }
1756 + else {
1757 + lp->stats.tx_dropped++;
1758 + dev_kfree_skb_any(skb);
1759 + spin_unlock_irqrestore(&lp->lock, flags);
1760 + return 1;
1761 + }
1762 + }
1763 +
1764 + lp->tx_count ++;
1765 +
1766 + lp->tx_skb[lp->tx_chain_tail] = skb;
1767 +
1768 + length = skb->len;
1769 +
1770 + /* Setup the transmit descriptor. */
1771 + td->ca = CPHYSADDR(skb->data);
1772 +
1773 + if(rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0) {
1774 + if( lp->tx_chain_status == empty ) {
1775 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1776 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1777 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
1778 + lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */
1779 + }
1780 + else {
1781 + td->control = DMA_COUNT(length) |DMAD_cof_m|DMAD_iof_m; /* Update tail */
1782 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */
1783 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */
1784 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1785 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
1786 + lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */
1787 + lp->tx_chain_status = empty;
1788 + }
1789 + }
1790 + else {
1791 + if( lp->tx_chain_status == empty ) {
1792 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1793 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1794 + lp->tx_chain_status = filled;
1795 + }
1796 + else {
1797 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1798 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */
1799 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */
1800 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1801 + }
1802 + }
1803 +
1804 + dev->trans_start = jiffies;
1805 +
1806 + spin_unlock_irqrestore(&lp->lock, flags);
1807 +
1808 + return 0;
1809 +}
1810 +
1811 +
1812 +/* Ethernet MII-PHY Handler */
1813 +static void rc32434_mii_handler(unsigned long data)
1814 +{
1815 + struct net_device *dev = (struct net_device *)data;
1816 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1817 + unsigned long flags;
1818 + unsigned long duplex_status;
1819 + int port_addr = (lp->rx_irq == 0x2c? 1:0) << 8;
1820 +
1821 + spin_lock_irqsave(&lp->lock, flags);
1822 +
1823 + /* Two ports are using the same MII, the difference is the PHY address */
1824 + rc32434_writel(0, &rc32434_eth0_regs->miimcfg);
1825 + rc32434_writel(0, &rc32434_eth0_regs->miimcmd);
1826 + rc32434_writel(port_addr |0x05, &rc32434_eth0_regs->miimaddr);
1827 + rc32434_writel(MIIMCMD_scn_m, &rc32434_eth0_regs->miimcmd);
1828 + while(rc32434_readl(&rc32434_eth0_regs->miimind) & MIIMIND_nv_m);
1829 +
1830 + ERR("irq:%x port_addr:%x RDD:%x\n",
1831 + lp->rx_irq, port_addr, rc32434_readl(&rc32434_eth0_regs->miimrdd));
1832 + duplex_status = (rc32434_readl(&rc32434_eth0_regs->miimrdd) & 0x140)? ETHMAC2_fd_m: 0;
1833 + if(duplex_status != lp->duplex_mode) {
1834 + ERR("The MII-PHY is Auto-negotiated to %s-Duplex mode for Eth-%x\n", duplex_status? "Full":"Half", lp->rx_irq == 0x2c? 1:0);
1835 + lp->duplex_mode = duplex_status;
1836 + rc32434_restart(dev);
1837 + }
1838 +
1839 + lp->mii_phy_timer.expires = jiffies + 10 * HZ;
1840 + add_timer(&lp->mii_phy_timer);
1841 +
1842 + spin_unlock_irqrestore(&lp->lock, flags);
1843 +
1844 +}
1845 +
1846 +#ifdef RC32434_REVISION
1847 +/* Ethernet Rx Overflow interrupt */
1848 +static irqreturn_t
1849 +rc32434_ovr_interrupt(int irq, void *dev_id)
1850 +{
1851 + struct net_device *dev = (struct net_device *)dev_id;
1852 + struct rc32434_local *lp;
1853 + unsigned int ovr;
1854 + irqreturn_t retval = IRQ_NONE;
1855 +
1856 + ASSERT(dev != NULL);
1857 +
1858 + lp = (struct rc32434_local *)dev->priv;
1859 + spin_lock(&lp->lock);
1860 + ovr = rc32434_readl(&lp->eth_regs->ethintfc);
1861 +
1862 + if(ovr & ETHINTFC_ovr_m) {
1863 + netif_stop_queue(dev);
1864 +
1865 + /* clear OVR bit */
1866 + rc32434_writel((ovr & ~ETHINTFC_ovr_m), &lp->eth_regs->ethintfc);
1867 +
1868 + /* Restart interface */
1869 + rc32434_restart(dev);
1870 + retval = IRQ_HANDLED;
1871 + }
1872 + spin_unlock(&lp->lock);
1873 +
1874 + return retval;
1875 +}
1876 +
1877 +#endif
1878 +
1879 +
1880 +/* Ethernet Tx Underflow interrupt */
1881 +static irqreturn_t
1882 +rc32434_und_interrupt(int irq, void *dev_id)
1883 +{
1884 + struct net_device *dev = (struct net_device *)dev_id;
1885 + struct rc32434_local *lp;
1886 + unsigned int und;
1887 + irqreturn_t retval = IRQ_NONE;
1888 +
1889 + ASSERT(dev != NULL);
1890 +
1891 + lp = (struct rc32434_local *)dev->priv;
1892 +
1893 + spin_lock(&lp->lock);
1894 +
1895 + und = rc32434_readl(&lp->eth_regs->ethintfc);
1896 +
1897 + if(und & ETHINTFC_und_m) {
1898 + netif_stop_queue(dev);
1899 +
1900 + rc32434_writel((und & ~ETHINTFC_und_m), &lp->eth_regs->ethintfc);
1901 +
1902 + /* Restart interface */
1903 + rc32434_restart(dev);
1904 + retval = IRQ_HANDLED;
1905 + }
1906 +
1907 + spin_unlock(&lp->lock);
1908 +
1909 + return retval;
1910 +}
1911 +
1912 +
1913 +/* Ethernet Rx DMA interrupt */
1914 +static irqreturn_t
1915 +rc32434_rx_dma_interrupt(int irq, void *dev_id)
1916 +{
1917 + struct net_device *dev = (struct net_device *)dev_id;
1918 + struct rc32434_local* lp;
1919 + volatile u32 dmas,dmasm;
1920 + irqreturn_t retval;
1921 +
1922 + ASSERT(dev != NULL);
1923 +
1924 + lp = (struct rc32434_local *)dev->priv;
1925 +
1926 + spin_lock(&lp->lock);
1927 + dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
1928 + if(dmas & (DMAS_d_m|DMAS_h_m|DMAS_e_m)) {
1929 + /* Mask D H E bit in Rx DMA */
1930 + dmasm = rc32434_readl(&lp->rx_dma_regs->dmasm);
1931 + rc32434_writel(dmasm | (DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
1932 +#ifdef CONFIG_IDT_USE_NAPI
1933 + if(netif_rx_schedule_prep(dev))
1934 + __netif_rx_schedule(dev);
1935 +#else
1936 + tasklet_hi_schedule(lp->rx_tasklet);
1937 +#endif
1938 +
1939 + if (dmas & DMAS_e_m)
1940 + ERR(": DMA error\n");
1941 +
1942 + retval = IRQ_HANDLED;
1943 + }
1944 + else
1945 + retval = IRQ_NONE;
1946 +
1947 + spin_unlock(&lp->lock);
1948 + return retval;
1949 +}
1950 +
1951 +#ifdef CONFIG_IDT_USE_NAPI
1952 +static int rc32434_poll(struct net_device *rx_data_dev, int *budget)
1953 +#else
1954 +static void rc32434_rx_tasklet(unsigned long rx_data_dev)
1955 +#endif
1956 +{
1957 + struct net_device *dev = (struct net_device *)rx_data_dev;
1958 + struct rc32434_local* lp = netdev_priv(dev);
1959 + volatile DMAD_t rd = &lp->rd_ring[lp->rx_next_done];
1960 + struct sk_buff *skb, *skb_new;
1961 + u8* pkt_buf;
1962 + u32 devcs, count, pkt_len, pktuncrc_len;
1963 + volatile u32 dmas;
1964 +#ifdef CONFIG_IDT_USE_NAPI
1965 + u32 received = 0;
1966 + int rx_work_limit = min(*budget,dev->quota);
1967 +#else
1968 + unsigned long flags;
1969 + spin_lock_irqsave(&lp->lock, flags);
1970 +#endif
1971 +
1972 + while ( (count = RC32434_RBSIZE - (u32)DMA_COUNT(rd->control)) != 0) {
1973 +#ifdef CONFIG_IDT_USE_NAPI
1974 + if(--rx_work_limit <0)
1975 + {
1976 + break;
1977 + }
1978 +#endif
1979 + /* init the var. used for the later operations within the while loop */
1980 + skb_new = NULL;
1981 + devcs = rd->devcs;
1982 + pkt_len = RCVPKT_LENGTH(devcs);
1983 + skb = lp->rx_skb[lp->rx_next_done];
1984 +
1985 + if (count < 64) {
1986 + lp->stats.rx_errors++;
1987 + lp->stats.rx_dropped++;
1988 + }
1989 + else if ((devcs & ( ETHRX_ld_m)) != ETHRX_ld_m) {
1990 + /* check that this is a whole packet */
1991 + /* WARNING: DMA_FD bit incorrectly set in Rc32434 (errata ref #077) */
1992 + lp->stats.rx_errors++;
1993 + lp->stats.rx_dropped++;
1994 + }
1995 + else if ( (devcs & ETHRX_rok_m) ) {
1996 +
1997 + {
1998 + /* must be the (first and) last descriptor then */
1999 + pkt_buf = (u8*)lp->rx_skb[lp->rx_next_done]->data;
2000 +
2001 + pktuncrc_len = pkt_len - 4;
2002 + /* invalidate the cache */
2003 + dma_cache_inv((unsigned long)pkt_buf, pktuncrc_len);
2004 +
2005 + /* Malloc up new buffer. */
2006 + skb_new = dev_alloc_skb(RC32434_RBSIZE + 2);
2007 +
2008 + if (skb_new != NULL){
2009 + /* Make room */
2010 + skb_put(skb, pktuncrc_len);
2011 +
2012 + skb->protocol = eth_type_trans(skb, dev);
2013 +
2014 + /* pass the packet to upper layers */
2015 +#ifdef CONFIG_IDT_USE_NAPI
2016 + netif_receive_skb(skb);
2017 +#else
2018 + netif_rx(skb);
2019 +#endif
2020 +
2021 + dev->last_rx = jiffies;
2022 + lp->stats.rx_packets++;
2023 + lp->stats.rx_bytes += pktuncrc_len;
2024 +
2025 + if (IS_RCV_MP(devcs))
2026 + lp->stats.multicast++;
2027 +
2028 + /* 16 bit align */
2029 + skb_reserve(skb_new, 2);
2030 +
2031 + skb_new->dev = dev;
2032 + lp->rx_skb[lp->rx_next_done] = skb_new;
2033 + }
2034 + else {
2035 + ERR("no memory, dropping rx packet.\n");
2036 + lp->stats.rx_errors++;
2037 + lp->stats.rx_dropped++;
2038 + }
2039 + }
2040 +
2041 + }
2042 + else {
2043 + /* This should only happen if we enable accepting broken packets */
2044 + lp->stats.rx_errors++;
2045 + lp->stats.rx_dropped++;
2046 +
2047 + /* add statistics counters */
2048 + if (IS_RCV_CRC_ERR(devcs)) {
2049 + DBG(2, "RX CRC error\n");
2050 + lp->stats.rx_crc_errors++;
2051 + }
2052 + else if (IS_RCV_LOR_ERR(devcs)) {
2053 + DBG(2, "RX LOR error\n");
2054 + lp->stats.rx_length_errors++;
2055 + }
2056 + else if (IS_RCV_LE_ERR(devcs)) {
2057 + DBG(2, "RX LE error\n");
2058 + lp->stats.rx_length_errors++;
2059 + }
2060 + else if (IS_RCV_OVR_ERR(devcs)) {
2061 + lp->stats.rx_over_errors++;
2062 + }
2063 + else if (IS_RCV_CV_ERR(devcs)) {
2064 + /* code violation */
2065 + DBG(2, "RX CV error\n");
2066 + lp->stats.rx_frame_errors++;
2067 + }
2068 + else if (IS_RCV_CES_ERR(devcs)) {
2069 + DBG(2, "RX Preamble error\n");
2070 + }
2071 + }
2072 +
2073 + rd->devcs = 0;
2074 +
2075 + /* restore descriptor's curr_addr */
2076 + if(skb_new)
2077 + rd->ca = CPHYSADDR(skb_new->data);
2078 + else
2079 + rd->ca = CPHYSADDR(skb->data);
2080 +
2081 + rd->control = DMA_COUNT(RC32434_RBSIZE) |DMAD_cod_m |DMAD_iod_m;
2082 + lp->rd_ring[(lp->rx_next_done-1)& RC32434_RDS_MASK].control &= ~(DMAD_cod_m);
2083 +
2084 + lp->rx_next_done = (lp->rx_next_done + 1) & RC32434_RDS_MASK;
2085 + rd = &lp->rd_ring[lp->rx_next_done];
2086 + rc32434_writel( ~DMAS_d_m, &lp->rx_dma_regs->dmas);
2087 + }
2088 +#ifdef CONFIG_IDT_USE_NAPI
2089 + dev->quota -= received;
2090 + *budget =- received;
2091 + if(rx_work_limit < 0)
2092 + goto not_done;
2093 +#endif
2094 +
2095 + dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
2096 +
2097 + if(dmas & DMAS_h_m) {
2098 + rc32434_writel( ~(DMAS_h_m | DMAS_e_m), &lp->rx_dma_regs->dmas);
2099 +#ifdef RC32434_PROC_DEBUG
2100 + lp->dma_halt_cnt++;
2101 +#endif
2102 + rd->devcs = 0;
2103 + skb = lp->rx_skb[lp->rx_next_done];
2104 + rd->ca = CPHYSADDR(skb->data);
2105 + rc32434_chain_rx(lp,rd);
2106 + }
2107 +
2108 +#ifdef CONFIG_IDT_USE_NAPI
2109 + netif_rx_complete(dev);
2110 +#endif
2111 + /* Enable D H E bit in Rx DMA */
2112 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m |DMASM_e_m), &lp->rx_dma_regs->dmasm);
2113 +#ifdef CONFIG_IDT_USE_NAPI
2114 + return 0;
2115 + not_done:
2116 + return 1;
2117 +#else
2118 + spin_unlock_irqrestore(&lp->lock, flags);
2119 + return;
2120 +#endif
2121 +
2122 +
2123 +}
2124 +
2125 +
2126 +
2127 +/* Ethernet Tx DMA interrupt */
2128 +static irqreturn_t
2129 +rc32434_tx_dma_interrupt(int irq, void *dev_id)
2130 +{
2131 + struct net_device *dev = (struct net_device *)dev_id;
2132 + struct rc32434_local *lp;
2133 + volatile u32 dmas,dmasm;
2134 + irqreturn_t retval;
2135 +
2136 + ASSERT(dev != NULL);
2137 +
2138 + lp = (struct rc32434_local *)dev->priv;
2139 +
2140 + spin_lock(&lp->lock);
2141 +
2142 + dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
2143 +
2144 + if (dmas & (DMAS_f_m | DMAS_e_m)) {
2145 + dmasm = rc32434_readl(&lp->tx_dma_regs->dmasm);
2146 + /* Mask F E bit in Tx DMA */
2147 + rc32434_writel(dmasm | (DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2148 +
2149 + tasklet_hi_schedule(lp->tx_tasklet);
2150 +
2151 + if(lp->tx_chain_status == filled && (rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0)) {
2152 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr));
2153 + lp->tx_chain_status = empty;
2154 + lp->tx_chain_head = lp->tx_chain_tail;
2155 + dev->trans_start = jiffies;
2156 + }
2157 +
2158 + if (dmas & DMAS_e_m)
2159 + ERR(": DMA error\n");
2160 +
2161 + retval = IRQ_HANDLED;
2162 + }
2163 + else
2164 + retval = IRQ_NONE;
2165 +
2166 + spin_unlock(&lp->lock);
2167 +
2168 + return retval;
2169 +}
2170 +
2171 +
2172 +static void rc32434_tx_tasklet(unsigned long tx_data_dev)
2173 +{
2174 + struct net_device *dev = (struct net_device *)tx_data_dev;
2175 + struct rc32434_local* lp = (struct rc32434_local *)dev->priv;
2176 + volatile DMAD_t td = &lp->td_ring[lp->tx_next_done];
2177 + u32 devcs;
2178 + unsigned long flags;
2179 + volatile u32 dmas;
2180 +
2181 + spin_lock_irqsave(&lp->lock, flags);
2182 +
2183 + /* process all desc that are done */
2184 + while(IS_DMA_FINISHED(td->control)) {
2185 + if(lp->tx_full == 1) {
2186 + netif_wake_queue(dev);
2187 + lp->tx_full = 0;
2188 + }
2189 +
2190 + devcs = lp->td_ring[lp->tx_next_done].devcs;
2191 + if ((devcs & (ETHTX_fd_m | ETHTX_ld_m)) != (ETHTX_fd_m | ETHTX_ld_m)) {
2192 + lp->stats.tx_errors++;
2193 + lp->stats.tx_dropped++;
2194 +
2195 + /* should never happen */
2196 + DBG(1, __FUNCTION__ ": split tx ignored\n");
2197 + }
2198 + else if (IS_TX_TOK(devcs)) {
2199 + lp->stats.tx_packets++;
2200 + }
2201 + else {
2202 + lp->stats.tx_errors++;
2203 + lp->stats.tx_dropped++;
2204 +
2205 + /* underflow */
2206 + if (IS_TX_UND_ERR(devcs))
2207 + lp->stats.tx_fifo_errors++;
2208 +
2209 + /* oversized frame */
2210 + if (IS_TX_OF_ERR(devcs))
2211 + lp->stats.tx_aborted_errors++;
2212 +
2213 + /* excessive deferrals */
2214 + if (IS_TX_ED_ERR(devcs))
2215 + lp->stats.tx_carrier_errors++;
2216 +
2217 + /* collisions: medium busy */
2218 + if (IS_TX_EC_ERR(devcs))
2219 + lp->stats.collisions++;
2220 +
2221 + /* late collision */
2222 + if (IS_TX_LC_ERR(devcs))
2223 + lp->stats.tx_window_errors++;
2224 +
2225 + }
2226 +
2227 + /* We must always free the original skb */
2228 + if (lp->tx_skb[lp->tx_next_done] != NULL) {
2229 + dev_kfree_skb_any(lp->tx_skb[lp->tx_next_done]);
2230 + lp->tx_skb[lp->tx_next_done] = NULL;
2231 + }
2232 +
2233 + lp->td_ring[lp->tx_next_done].control = DMAD_iof_m;
2234 + lp->td_ring[lp->tx_next_done].devcs = ETHTX_fd_m | ETHTX_ld_m;
2235 + lp->td_ring[lp->tx_next_done].link = 0;
2236 + lp->td_ring[lp->tx_next_done].ca = 0;
2237 + lp->tx_count --;
2238 +
2239 + /* go on to next transmission */
2240 + lp->tx_next_done = (lp->tx_next_done + 1) & RC32434_TDS_MASK;
2241 + td = &lp->td_ring[lp->tx_next_done];
2242 +
2243 + }
2244 +
2245 + dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
2246 + rc32434_writel( ~dmas, &lp->tx_dma_regs->dmas);
2247 +
2248 + /* Enable F E bit in Tx DMA */
2249 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2250 + spin_unlock_irqrestore(&lp->lock, flags);
2251 +
2252 +}
2253 +
2254 +
2255 +static struct net_device_stats * rc32434_get_stats(struct net_device *dev)
2256 +{
2257 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2258 + return &lp->stats;
2259 +}
2260 +
2261 +
2262 +/*
2263 + * Set or clear the multicast filter for this adaptor.
2264 + */
2265 +static void rc32434_multicast_list(struct net_device *dev)
2266 +{
2267 + /* listen to broadcasts always and to treat */
2268 + /* IFF bits independantly */
2269 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2270 + unsigned long flags;
2271 + u32 recognise = ETHARC_ab_m; /* always accept broadcasts */
2272 +
2273 + if (dev->flags & IFF_PROMISC) /* set promiscuous mode */
2274 + recognise |= ETHARC_pro_m;
2275 +
2276 + if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 15))
2277 + recognise |= ETHARC_am_m; /* all multicast & bcast */
2278 + else if (dev->mc_count > 0) {
2279 + DBG(2, __FUNCTION__ ": mc_count %d\n", dev->mc_count);
2280 + recognise |= ETHARC_am_m; /* for the time being */
2281 + }
2282 +
2283 + spin_lock_irqsave(&lp->lock, flags);
2284 + rc32434_writel(recognise, &lp->eth_regs->etharc);
2285 + spin_unlock_irqrestore(&lp->lock, flags);
2286 +}
2287 +
2288 +
2289 +static void rc32434_tx_timeout(struct net_device *dev)
2290 +{
2291 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2292 + unsigned long flags;
2293 +
2294 + spin_lock_irqsave(&lp->lock, flags);
2295 + rc32434_restart(dev);
2296 + spin_unlock_irqrestore(&lp->lock, flags);
2297 +
2298 +}
2299 +
2300 +
2301 +/*
2302 + * Initialize the RC32434 ethernet controller.
2303 + */
2304 +static int rc32434_init(struct net_device *dev)
2305 +{
2306 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2307 + int i, j;
2308 +
2309 + /* Disable DMA */
2310 + rc32434_abort_tx(dev);
2311 + rc32434_abort_rx(dev);
2312 +
2313 + /* reset ethernet logic */
2314 + rc32434_writel(0, &lp->eth_regs->ethintfc);
2315 + while((rc32434_readl(&lp->eth_regs->ethintfc) & ETHINTFC_rip_m))
2316 + dev->trans_start = jiffies;
2317 +
2318 + /* Enable Ethernet Interface */
2319 + rc32434_writel(ETHINTFC_en_m, &lp->eth_regs->ethintfc);
2320 +
2321 +#ifndef CONFIG_IDT_USE_NAPI
2322 + tasklet_disable(lp->rx_tasklet);
2323 +#endif
2324 + tasklet_disable(lp->tx_tasklet);
2325 +
2326 + /* Initialize the transmit Descriptors */
2327 + for (i = 0; i < RC32434_NUM_TDS; i++) {
2328 + lp->td_ring[i].control = DMAD_iof_m;
2329 + lp->td_ring[i].devcs = ETHTX_fd_m | ETHTX_ld_m;
2330 + lp->td_ring[i].ca = 0;
2331 + lp->td_ring[i].link = 0;
2332 + if (lp->tx_skb[i] != NULL) {
2333 + dev_kfree_skb_any(lp->tx_skb[i]);
2334 + lp->tx_skb[i] = NULL;
2335 + }
2336 + }
2337 + lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail = lp->tx_full = lp->tx_count = 0;
2338 + lp-> tx_chain_status = empty;
2339 +
2340 + /*
2341 + * Initialize the receive descriptors so that they
2342 + * become a circular linked list, ie. let the last
2343 + * descriptor point to the first again.
2344 + */
2345 + for (i=0; i<RC32434_NUM_RDS; i++) {
2346 + struct sk_buff *skb = lp->rx_skb[i];
2347 +
2348 + if (lp->rx_skb[i] == NULL) {
2349 + skb = dev_alloc_skb(RC32434_RBSIZE + 2);
2350 + if (skb == NULL) {
2351 + ERR("No memory in the system\n");
2352 + for (j = 0; j < RC32434_NUM_RDS; j ++)
2353 + if (lp->rx_skb[j] != NULL)
2354 + dev_kfree_skb_any(lp->rx_skb[j]);
2355 +
2356 + return 1;
2357 + }
2358 + else {
2359 + skb->dev = dev;
2360 + skb_reserve(skb, 2);
2361 + lp->rx_skb[i] = skb;
2362 + lp->rd_ring[i].ca = CPHYSADDR(skb->data);
2363 +
2364 + }
2365 + }
2366 + lp->rd_ring[i].control = DMAD_iod_m | DMA_COUNT(RC32434_RBSIZE);
2367 + lp->rd_ring[i].devcs = 0;
2368 + lp->rd_ring[i].ca = CPHYSADDR(skb->data);
2369 + lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[i+1]);
2370 +
2371 + }
2372 + /* loop back */
2373 + lp->rd_ring[RC32434_NUM_RDS-1].link = CPHYSADDR(&lp->rd_ring[0]);
2374 + lp->rx_next_done = 0;
2375 +
2376 + lp->rd_ring[RC32434_NUM_RDS-1].control |= DMAD_cod_m;
2377 + lp->rx_chain_head = 0;
2378 + lp->rx_chain_tail = 0;
2379 + lp->rx_chain_status = empty;
2380 +
2381 + rc32434_writel(0, &lp->rx_dma_regs->dmas);
2382 + /* Start Rx DMA */
2383 + rc32434_start_rx(lp, &lp->rd_ring[0]);
2384 +
2385 + /* Enable F E bit in Tx DMA */
2386 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2387 + /* Enable D H E bit in Rx DMA */
2388 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
2389 +
2390 + /* Accept only packets destined for this Ethernet device address */
2391 + rc32434_writel(ETHARC_ab_m, &lp->eth_regs->etharc);
2392 +
2393 + /* Set all Ether station address registers to their initial values */
2394 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0);
2395 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0);
2396 +
2397 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1);
2398 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1);
2399 +
2400 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2);
2401 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2);
2402 +
2403 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3);
2404 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3);
2405 +
2406 +
2407 + /* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */
2408 + rc32434_writel(ETHMAC2_pe_m | ETHMAC2_cen_m | ETHMAC2_fd_m, &lp->eth_regs->ethmac2);
2409 + //ETHMAC2_flc_m ETHMAC2_fd_m lp->duplex_mode
2410 +
2411 + /* Back to back inter-packet-gap */
2412 + rc32434_writel(0x15, &lp->eth_regs->ethipgt);
2413 + /* Non - Back to back inter-packet-gap */
2414 + rc32434_writel(0x12, &lp->eth_regs->ethipgr);
2415 +
2416 + /* Management Clock Prescaler Divisor */
2417 + /* Clock independent setting */
2418 + rc32434_writel(((idt_cpu_freq)/MII_CLOCK+1) & ~1,
2419 + &lp->eth_regs->ethmcp);
2420 +
2421 + /* don't transmit until fifo contains 48b */
2422 + rc32434_writel(48, &lp->eth_regs->ethfifott);
2423 +
2424 + rc32434_writel(ETHMAC1_re_m, &lp->eth_regs->ethmac1);
2425 +
2426 +#ifndef CONFIG_IDT_USE_NAPI
2427 + tasklet_enable(lp->rx_tasklet);
2428 +#endif
2429 + tasklet_enable(lp->tx_tasklet);
2430 +
2431 + netif_start_queue(dev);
2432 +
2433 +
2434 + return 0;
2435 +
2436 +}
2437 +
2438 +
2439 +#ifndef MODULE
2440 +
2441 +static int __init rc32434_setup(char *options)
2442 +{
2443 + /* no options yet */
2444 + return 1;
2445 +}
2446 +
2447 +static int __init rc32434_setup_ethaddr0(char *options)
2448 +{
2449 + memcpy(mac0, options, 17);
2450 + mac0[17]= '\0';
2451 + return 1;
2452 +}
2453 +
2454 +__setup("rc32434eth=", rc32434_setup);
2455 +__setup("ethaddr0=", rc32434_setup_ethaddr0);
2456 +
2457 +
2458 +#endif /* MODULE */
2459 +
2460 +module_init(rc32434_init_module);
2461 +module_exit(rc32434_cleanup_module);
2462 +
2463 +
2464 +
2465 +
2466 +
2467 +
2468 +
2469 +
2470 +
2471 +
2472 +
2473 +
2474 +
2475 +
2476 diff -Nur linux-2.6.17/drivers/net/rc32434_eth.h linux-2.6.17-owrt/drivers/net/rc32434_eth.h
2477 --- linux-2.6.17/drivers/net/rc32434_eth.h 1970-01-01 01:00:00.000000000 +0100
2478 +++ linux-2.6.17-owrt/drivers/net/rc32434_eth.h 2006-06-18 12:44:28.000000000 +0200
2479 @@ -0,0 +1,187 @@
2480 +/**************************************************************************
2481 + *
2482 + * BRIEF MODULE DESCRIPTION
2483 + * Definitions for IDT RC32434 on-chip ethernet controller.
2484 + *
2485 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2486 + *
2487 + * This program is free software; you can redistribute it and/or modify it
2488 + * under the terms of the GNU General Public License as published by the
2489 + * Free Software Foundation; either version 2 of the License, or (at your
2490 + * option) any later version.
2491 + *
2492 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2493 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2494 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2495 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2496 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2497 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2498 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2499 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2500 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2501 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2502 + *
2503 + * You should have received a copy of the GNU General Public License along
2504 + * with this program; if not, write to the Free Software Foundation, Inc.,
2505 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2506 + *
2507 + *
2508 + **************************************************************************
2509 + * May 2004 rkt, neb
2510 + *
2511 + * Initial Release
2512 + *
2513 + * Aug 2004
2514 + *
2515 + * Added NAPI
2516 + *
2517 + **************************************************************************
2518 + */
2519 +
2520 +
2521 +#include <asm/idt-boards/rc32434/rc32434.h>
2522 +#include <asm/idt-boards/rc32434/rc32434_dma_v.h>
2523 +#include <asm/idt-boards/rc32434/rc32434_eth_v.h>
2524 +
2525 +#define RC32434_DEBUG 2
2526 +//#define RC32434_PROC_DEBUG
2527 +#undef RC32434_DEBUG
2528 +
2529 +#ifdef RC32434_DEBUG
2530 +
2531 +/* use 0 for production, 1 for verification, >2 for debug */
2532 +static int rc32434_debug = RC32434_DEBUG;
2533 +#define ASSERT(expr) \
2534 + if(!(expr)) { \
2535 + printk( "Assertion failed! %s,%s,%s,line=%d\n", \
2536 + #expr,__FILE__,__FUNCTION__,__LINE__); }
2537 +#define DBG(lvl, format, arg...) if (rc32434_debug > lvl) printk(KERN_INFO "%s: " format, dev->name , ## arg)
2538 +#else
2539 +#define ASSERT(expr) do {} while (0)
2540 +#define DBG(lvl, format, arg...) do {} while (0)
2541 +#endif
2542 +
2543 +#define INFO(format, arg...) printk(KERN_INFO "%s: " format, dev->name , ## arg)
2544 +#define ERR(format, arg...) printk(KERN_ERR "%s: " format, dev->name , ## arg)
2545 +#define WARN(format, arg...) printk(KERN_WARNING "%s: " format, dev->name , ## arg)
2546 +
2547 +#define ETH0_DMA_RX_IRQ GROUP1_IRQ_BASE + 0
2548 +#define ETH0_DMA_TX_IRQ GROUP1_IRQ_BASE + 1
2549 +#define ETH0_RX_OVR_IRQ GROUP3_IRQ_BASE + 9
2550 +#define ETH0_TX_UND_IRQ GROUP3_IRQ_BASE + 10
2551 +
2552 +#define ETH0_RX_DMA_ADDR (DMA0_PhysicalAddress + 0*DMA_CHAN_OFFSET)
2553 +#define ETH0_TX_DMA_ADDR (DMA0_PhysicalAddress + 1*DMA_CHAN_OFFSET)
2554 +
2555 +/* the following must be powers of two */
2556 +#ifdef CONFIG_IDT_USE_NAPI
2557 +#define RC32434_NUM_RDS 64 /* number of receive descriptors */
2558 +#define RC32434_NUM_TDS 64 /* number of transmit descriptors */
2559 +#else
2560 +#define RC32434_NUM_RDS 128 /* number of receive descriptors */
2561 +#define RC32434_NUM_TDS 128 /* number of transmit descriptors */
2562 +#endif
2563 +
2564 +#define RC32434_RBSIZE 1536 /* size of one resource buffer = Ether MTU */
2565 +#define RC32434_RDS_MASK (RC32434_NUM_RDS-1)
2566 +#define RC32434_TDS_MASK (RC32434_NUM_TDS-1)
2567 +#define RD_RING_SIZE (RC32434_NUM_RDS * sizeof(struct DMAD_s))
2568 +#define TD_RING_SIZE (RC32434_NUM_TDS * sizeof(struct DMAD_s))
2569 +
2570 +#define RC32434_TX_TIMEOUT HZ * 100
2571 +
2572 +#define rc32434_eth0_regs ((ETH_t)(ETH0_VirtualAddress))
2573 +#define rc32434_eth1_regs ((ETH_t)(ETH1_VirtualAddress))
2574 +
2575 +enum status { filled, empty};
2576 +#define IS_DMA_FINISHED(X) (((X) & (DMAD_f_m)) != 0)
2577 +#define IS_DMA_DONE(X) (((X) & (DMAD_d_m)) != 0)
2578 +
2579 +
2580 +/* Information that need to be kept for each board. */
2581 +struct rc32434_local {
2582 + ETH_t eth_regs;
2583 + DMA_Chan_t rx_dma_regs;
2584 + DMA_Chan_t tx_dma_regs;
2585 + volatile DMAD_t td_ring; /* transmit descriptor ring */
2586 + volatile DMAD_t rd_ring; /* receive descriptor ring */
2587 +
2588 + struct sk_buff* tx_skb[RC32434_NUM_TDS]; /* skbuffs for pkt to trans */
2589 + struct sk_buff* rx_skb[RC32434_NUM_RDS]; /* skbuffs for pkt to trans */
2590 +
2591 +#ifndef CONFIG_IDT_USE_NAPI
2592 + struct tasklet_struct * rx_tasklet;
2593 +#endif
2594 + struct tasklet_struct * tx_tasklet;
2595 +
2596 + int rx_next_done;
2597 + int rx_chain_head;
2598 + int rx_chain_tail;
2599 + enum status rx_chain_status;
2600 +
2601 + int tx_next_done;
2602 + int tx_chain_head;
2603 + int tx_chain_tail;
2604 + enum status tx_chain_status;
2605 + int tx_count;
2606 + int tx_full;
2607 +
2608 + struct timer_list mii_phy_timer;
2609 + unsigned long duplex_mode;
2610 +
2611 + int rx_irq;
2612 + int tx_irq;
2613 + int ovr_irq;
2614 + int und_irq;
2615 +
2616 + struct net_device_stats stats;
2617 + spinlock_t lock;
2618 +
2619 + /* debug /proc entry */
2620 + struct proc_dir_entry *ps;
2621 + int dma_halt_cnt; int dma_run_cnt;
2622 +};
2623 +
2624 +extern unsigned int idt_cpu_freq;
2625 +
2626 +/* Index to functions, as function prototypes. */
2627 +static int rc32434_open(struct net_device *dev);
2628 +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev);
2629 +static void rc32434_mii_handler(unsigned long data);
2630 +static irqreturn_t rc32434_und_interrupt(int irq, void *dev_id);
2631 +static irqreturn_t rc32434_rx_dma_interrupt(int irq, void *dev_id);
2632 +static irqreturn_t rc32434_tx_dma_interrupt(int irq, void *dev_id);
2633 +#ifdef RC32434_REVISION
2634 +static irqreturn_t rc32434_ovr_interrupt(int irq, void *dev_id);
2635 +#endif
2636 +static int rc32434_close(struct net_device *dev);
2637 +static struct net_device_stats *rc32434_get_stats(struct net_device *dev);
2638 +static void rc32434_multicast_list(struct net_device *dev);
2639 +static int rc32434_init(struct net_device *dev);
2640 +static void rc32434_tx_timeout(struct net_device *dev);
2641 +
2642 +static void rc32434_tx_tasklet(unsigned long tx_data_dev);
2643 +#ifdef CONFIG_IDT_USE_NAPI
2644 +static int rc32434_poll(struct net_device *rx_data_dev, int *budget);
2645 +#else
2646 +static void rc32434_rx_tasklet(unsigned long rx_data_dev);
2647 +#endif
2648 +static void rc32434_cleanup_module(void);
2649 +static int rc32434_probe(int port_num);
2650 +int rc32434_init_module(void);
2651 +
2652 +
2653 +static inline void rc32434_abort_dma(struct net_device *dev, DMA_Chan_t ch)
2654 +{
2655 + if (rc32434_readl(&ch->dmac) & DMAC_run_m) {
2656 + rc32434_writel(0x10, &ch->dmac);
2657 +
2658 + while (!(rc32434_readl(&ch->dmas) & DMAS_h_m))
2659 + dev->trans_start = jiffies;
2660 +
2661 + rc32434_writel(0, &ch->dmas);
2662 + }
2663 +
2664 + rc32434_writel(0, &ch->dmadptr);
2665 + rc32434_writel(0, &ch->dmandptr);
2666 +}
2667 diff -Nur linux-2.6.17/include/asm-mips/bootinfo.h linux-2.6.17-owrt/include/asm-mips/bootinfo.h
2668 --- linux-2.6.17/include/asm-mips/bootinfo.h 2006-06-18 03:49:35.000000000 +0200
2669 +++ linux-2.6.17-owrt/include/asm-mips/bootinfo.h 2006-06-18 12:44:28.000000000 +0200
2670 @@ -218,6 +218,17 @@
2671 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
2672 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
2673
2674 +
2675 +/*
2676 + * Valid machtype for group ARUBA
2677 + */
2678 +#define MACH_GROUP_ARUBA 23
2679 +#define MACH_ARUBA_UNKNOWN 0
2680 +#define MACH_ARUBA_AP60 1
2681 +#define MACH_ARUBA_AP65 2
2682 +#define MACH_ARUBA_AP70 3
2683 +#define MACH_ARUBA_AP40 4
2684 +
2685 #define CL_SIZE COMMAND_LINE_SIZE
2686
2687 const char *get_system_type(void);
2688 diff -Nur linux-2.6.17/include/asm-mips/cpu.h linux-2.6.17-owrt/include/asm-mips/cpu.h
2689 --- linux-2.6.17/include/asm-mips/cpu.h 2006-06-18 03:49:35.000000000 +0200
2690 +++ linux-2.6.17-owrt/include/asm-mips/cpu.h 2006-06-18 12:45:56.000000000 +0200
2691 @@ -54,6 +54,9 @@
2692 #define PRID_IMP_R14000 0x0f00
2693 #define PRID_IMP_R8000 0x1000
2694 #define PRID_IMP_PR4450 0x1200
2695 +#define PRID_IMP_RC32334 0x1800
2696 +#define PRID_IMP_RC32355 0x1900
2697 +#define PRID_IMP_RC32365 0x1900
2698 #define PRID_IMP_R4600 0x2000
2699 #define PRID_IMP_R4700 0x2100
2700 #define PRID_IMP_TX39 0x2200
2701 @@ -200,7 +203,8 @@
2702 #define CPU_SB1A 62
2703 #define CPU_74K 63
2704 #define CPU_R14000 64
2705 -#define CPU_LAST 64
2706 +#define CPU_RC32300 65
2707 +#define CPU_LAST 65
2708
2709 /*
2710 * ISA Level encodings
2711 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32300.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32300.h
2712 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32300.h 1970-01-01 01:00:00.000000000 +0100
2713 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32300.h 2006-06-18 12:44:28.000000000 +0200
2714 @@ -0,0 +1,142 @@
2715 +/**************************************************************************
2716 + *
2717 + * BRIEF MODULE DESCRIPTION
2718 + * RC32300 helper routines
2719 + *
2720 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2721 + *
2722 + * This program is free software; you can redistribute it and/or modify it
2723 + * under the terms of the GNU General Public License as published by the
2724 + * Free Software Foundation; either version 2 of the License, or (at your
2725 + * option) any later version.
2726 + *
2727 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2728 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2729 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2730 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2731 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2732 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2733 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2734 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2735 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2736 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2737 + *
2738 + * You should have received a copy of the GNU General Public License along
2739 + * with this program; if not, write to the Free Software Foundation, Inc.,
2740 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2741 + *
2742 + *
2743 + **************************************************************************
2744 + * May 2004 P. Sadik.
2745 + *
2746 + * Initial Release
2747 + *
2748 + *
2749 + *
2750 + **************************************************************************
2751 + */
2752 +
2753 +#ifndef __IDT_RC32300_H__
2754 +#define __IDT_RC32300_H__
2755 +
2756 +#include <linux/delay.h>
2757 +#include <asm/io.h>
2758 +
2759 +
2760 +/* cpu pipeline flush */
2761 +static inline void rc32300_sync(void)
2762 +{
2763 + __asm__ volatile ("sync");
2764 +}
2765 +
2766 +static inline void rc32300_sync_udelay(int us)
2767 +{
2768 + __asm__ volatile ("sync");
2769 + udelay(us);
2770 +}
2771 +
2772 +static inline void rc32300_sync_delay(int ms)
2773 +{
2774 + __asm__ volatile ("sync");
2775 + mdelay(ms);
2776 +}
2777 +
2778 +/*
2779 + * Macros to access internal RC32300 registers. No byte
2780 + * swapping should be done when accessing the internal
2781 + * registers.
2782 + */
2783 +
2784 +static inline u8 rc32300_readb(unsigned long pa)
2785 +{
2786 + return *((volatile u8 *)KSEG1ADDR(pa));
2787 +}
2788 +static inline u16 rc32300_readw(unsigned long pa)
2789 +{
2790 + return *((volatile u16 *)KSEG1ADDR(pa));
2791 +}
2792 +static inline u32 rc32300_readl(unsigned long pa)
2793 +{
2794 + return *((volatile u32 *)KSEG1ADDR(pa));
2795 +}
2796 +static inline void rc32300_writeb(u8 val, unsigned long pa)
2797 +{
2798 + *((volatile u8 *)KSEG1ADDR(pa)) = val;
2799 +}
2800 +static inline void rc32300_writew(u16 val, unsigned long pa)
2801 +{
2802 + *((volatile u16 *)KSEG1ADDR(pa)) = val;
2803 +}
2804 +static inline void rc32300_writel(u32 val, unsigned long pa)
2805 +{
2806 + *((volatile u32 *)KSEG1ADDR(pa)) = val;
2807 +}
2808 +
2809 +
2810 +#define local_readb __raw_readb
2811 +#define local_readw __raw_readw
2812 +#define local_readl __raw_readl
2813 +
2814 +#define local_writeb __raw_writeb
2815 +#define local_writew __raw_writew
2816 +#define local_writel __raw_writel
2817 +
2818 +
2819 +/*
2820 + * C access to CLZ and CLO instructions
2821 + * (count leading zeroes/ones).
2822 + */
2823 +static inline int rc32300_clz(unsigned long val)
2824 +{
2825 + int ret;
2826 + __asm__ volatile (
2827 + ".set\tnoreorder\n\t"
2828 + ".set\tnoat\n\t"
2829 + ".set\tmips32\n\t"
2830 + "clz\t%0,%1\n\t"
2831 + ".set\tmips0\n\t"
2832 + ".set\tat\n\t"
2833 + ".set\treorder"
2834 + : "=r" (ret)
2835 + : "r" (val));
2836 +
2837 + return ret;
2838 +}
2839 +static inline int rc32300_clo(unsigned long val)
2840 +{
2841 + int ret;
2842 + __asm__ volatile (
2843 + ".set\tnoreorder\n\t"
2844 + ".set\tnoat\n\t"
2845 + ".set\tmips32\n\t"
2846 + "clo\t%0,%1\n\t"
2847 + ".set\tmips0\n\t"
2848 + ".set\tat\n\t"
2849 + ".set\treorder"
2850 + : "=r" (ret)
2851 + : "r" (val));
2852 +
2853 + return ret;
2854 +}
2855 +
2856 +#endif // __IDT_RC32300_H__
2857 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32334.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32334.h
2858 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32334.h 1970-01-01 01:00:00.000000000 +0100
2859 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32334.h 2006-06-18 12:44:28.000000000 +0200
2860 @@ -0,0 +1,207 @@
2861 +/**************************************************************************
2862 + *
2863 + * BRIEF MODULE DESCRIPTION
2864 + * Definitions for IDT RC32334 CPU.
2865 + *
2866 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2867 + *
2868 + * This program is free software; you can redistribute it and/or modify it
2869 + * under the terms of the GNU General Public License as published by the
2870 + * Free Software Foundation; either version 2 of the License, or (at your
2871 + * option) any later version.
2872 + *
2873 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2874 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2875 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2876 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2877 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2878 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2879 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2880 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2881 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2882 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2883 + *
2884 + * You should have received a copy of the GNU General Public License along
2885 + * with this program; if not, write to the Free Software Foundation, Inc.,
2886 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2887 + *
2888 + *
2889 + **************************************************************************
2890 + * May 2004 P. Sadik.
2891 + *
2892 + * Initial Release
2893 + *
2894 + *
2895 + *
2896 + **************************************************************************
2897 + */
2898 +
2899 +
2900 +#ifndef __IDT_RC32334_H__
2901 +#define __IDT_RC32334_H__
2902 +
2903 +#include <linux/delay.h>
2904 +#include <asm/io.h>
2905 +
2906 +/* Base address of internal registers */
2907 +#define RC32334_REG_BASE 0x18000000
2908 +
2909 +/* CPU and IP Bus Control */
2910 +#define CPU_PORT_WIDTH 0xffffe200 // virtual!
2911 +#define CPU_BTA 0xffffe204 // virtual!
2912 +#define CPU_BUSERR_ADDR 0xffffe208 // virtual!
2913 +#define CPU_IP_BTA (RC32334_REG_BASE + 0x0000)
2914 +#define CPU_IP_ADDR_LATCH (RC32334_REG_BASE + 0x0004)
2915 +#define CPU_IP_ARBITRATION (RC32334_REG_BASE + 0x0008)
2916 +#define CPU_IP_BUSERR_CNTL (RC32334_REG_BASE + 0x0010)
2917 +#define CPU_IP_BUSERR_ADDR (RC32334_REG_BASE + 0x0014)
2918 +#define CPU_IP_SYSID (RC32334_REG_BASE + 0x0018)
2919 +
2920 +/* Memory Controller */
2921 +#define MEM_BASE_BANK0 (RC32334_REG_BASE + 0x0080)
2922 +#define MEM_MASK_BANK0 (RC32334_REG_BASE + 0x0084)
2923 +#define MEM_CNTL_BANK0 (RC32334_REG_BASE + 0x0200)
2924 +#define MEM_BASE_BANK1 (RC32334_REG_BASE + 0x0088)
2925 +#define MEM_MASK_BANK1 (RC32334_REG_BASE + 0x008c)
2926 +#define MEM_CNTL_BANK1 (RC32334_REG_BASE + 0x0204)
2927 +#define MEM_CNTL_BANK2 (RC32334_REG_BASE + 0x0208)
2928 +#define MEM_CNTL_BANK3 (RC32334_REG_BASE + 0x020c)
2929 +#define MEM_CNTL_BANK4 (RC32334_REG_BASE + 0x0210)
2930 +#define MEM_CNTL_BANK5 (RC32334_REG_BASE + 0x0214)
2931 +
2932 +/* PCI Controller */
2933 +#define PCI_INTR_PEND (RC32334_REG_BASE + 0x05b0)
2934 +#define PCI_INTR_MASK (RC32334_REG_BASE + 0x05b4)
2935 +#define PCI_INTR_CLEAR (RC32334_REG_BASE + 0x05b8)
2936 +#define CPU2PCI_INTR_PEND (RC32334_REG_BASE + 0x05c0)
2937 +#define CPU2PCI_INTR_MASK (RC32334_REG_BASE + 0x05c4)
2938 +#define CPU2PCI_INTR_CLEAR (RC32334_REG_BASE + 0x05c8)
2939 +#define PCI2CPU_INTR_PEND (RC32334_REG_BASE + 0x05d0)
2940 +#define PCI2CPU_INTR_MASK (RC32334_REG_BASE + 0x05d4)
2941 +#define PCI2CPU_INTR_CLEAR (RC32334_REG_BASE + 0x05d8)
2942 +#define PCI_MEM1_BASE (RC32334_REG_BASE + 0x20b0)
2943 +#define PCI_MEM2_BASE (RC32334_REG_BASE + 0x20b8)
2944 +#define PCI_MEM3_BASE (RC32334_REG_BASE + 0x20c0)
2945 +#define PCI_IO1_BASE (RC32334_REG_BASE + 0x20c8)
2946 +#define PCI_ARBITRATION (RC32334_REG_BASE + 0x20e0)
2947 +#define PCI_CPU_MEM1_BASE (RC32334_REG_BASE + 0x20e8)
2948 +#define PCI_CPU_IO_BASE (RC32334_REG_BASE + 0x2100)
2949 +#define PCI_CFG_CNTL (RC32334_REG_BASE + 0x2cf8)
2950 +#define PCI_CFG_DATA (RC32334_REG_BASE + 0x2cfc)
2951 +
2952 +/* Timers */
2953 +#define TIMER0_CNTL (RC32334_REG_BASE + 0x0700)
2954 +#define TIMER0_COUNT (RC32334_REG_BASE + 0x0704)
2955 +#define TIMER0_COMPARE (RC32334_REG_BASE + 0x0708)
2956 +#define TIMER_REG_OFFSET 0x10
2957 +
2958 +/* Programmable I/O */
2959 +#define PIO_DATA0 (RC32334_REG_BASE + 0x0600)
2960 +#define PIO_DATA1 (RC32334_REG_BASE + 0x0610)
2961 +
2962 +/*
2963 + * DMA
2964 + *
2965 + * NOTE: DMA_IO is a trick for non linear RC32300_IO_DMA stuff
2966 + *
2967 + * DMA0: 18001400
2968 + * DMA1: 18001440
2969 + * DMA2: 18001900
2970 + * DMA3: 18001940
2971 + * NB: dma number must be immediate value or variable.
2972 + * It MUST NOT be a function since it would get called twice!
2973 + */
2974 +#define DMA_IO(n) (((n)>1?0x500:0)+((n)&1?0x40:0))
2975 +
2976 +#define RC32300_IO_DMA(n) (RC32334_REG_BASE + 0x1400 + DMA_IO(n))
2977 +#define RC32300_DMA_CONFREG(n) RC32300_IO_DMA(n)
2978 +#define RC32300_DMA_BASEREG(n) (RC32300_IO_DMA(n)+0x4)
2979 +
2980 +#define RC32300_DMA_CURRREG(n) (RC32300_IO_DMA(n)+0x8)
2981 +#define RC32300_DMA_STATREG(n) (RC32300_IO_DMA(n)+0x10)
2982 +#define RC32300_DMA_SRCREG(n) (RC32300_IO_DMA(n)+0x14)
2983 +#define RC32300_DMA_DSTREG(n) (RC32300_IO_DMA(n)+0x18)
2984 +#define RC32300_DMA_NEXTREG(n) (RC32300_IO_DMA(n)+0x1c)
2985 +
2986 +#define RC32300_DMA_IRQ(n) (GROUP7_IRQ_BASE+5*(n))
2987 +
2988 +/* Expansion Interrupt Controller */
2989 +#define IC_GROUP0_PEND (RC32334_REG_BASE + 0x0500)
2990 +#define IC_GROUP0_MASK (RC32334_REG_BASE + 0x0504)
2991 +#define IC_GROUP0_CLEAR (RC32334_REG_BASE + 0x0508)
2992 +#define IC_GROUP_OFFSET 0x10
2993 +
2994 +#define NUM_INTR_GROUPS 15
2995 +/*
2996 + * The IRQ mapping is as follows:
2997 + *
2998 + * IRQ Mapped To
2999 + * --- -------------------
3000 + * 0 SW0 (IP0) SW0 intr
3001 + * 1 SW1 (IP1) SW1 intr
3002 + * 2 Int0 (IP2) board-specific
3003 + * 3 Int1 (IP3) board-specific
3004 + * 4 Int2 (IP4) board-specific
3005 + * - Int3 (IP5) not used, mapped to IRQ's 8 and up
3006 + * 6 Int4 (IP6) board-specific
3007 + * 7 Int5 (IP7) CP0 Timer
3008 + *
3009 + * IRQ's 8 and up are all mapped to Int3 (IP5), which
3010 + * internally on the RC32334 is routed to the Expansion
3011 + * Interrupt Controller.
3012 + */
3013 +#define MIPS_CPU_TIMER_IRQ 7
3014 +
3015 +#define GROUP1_IRQ_BASE 8 // bus error
3016 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 1) // PIO active low
3017 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 12) // PIO active high
3018 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 8) // Timer Rollovers
3019 +#define GROUP5_IRQ_BASE (GROUP4_IRQ_BASE + 8) // UART0
3020 +#define GROUP6_IRQ_BASE (GROUP5_IRQ_BASE + 3) // UART1
3021 +#define GROUP7_IRQ_BASE (GROUP6_IRQ_BASE + 3) // DMA Ch0
3022 +#define GROUP8_IRQ_BASE (GROUP7_IRQ_BASE + 5) // DMA Ch1
3023 +#define GROUP9_IRQ_BASE (GROUP8_IRQ_BASE + 5) // DMA Ch2
3024 +#define GROUP10_IRQ_BASE (GROUP9_IRQ_BASE + 5) // DMA Ch3
3025 +#define GROUP11_IRQ_BASE (GROUP10_IRQ_BASE + 5) // PCI Ctlr errors
3026 +#define GROUP12_IRQ_BASE (GROUP11_IRQ_BASE + 4) // PCI Satellite Mode
3027 +#define GROUP13_IRQ_BASE (GROUP12_IRQ_BASE + 16) // PCI to CPU Mailbox
3028 +#define GROUP14_IRQ_BASE (GROUP13_IRQ_BASE + 4) // SPI
3029 +
3030 +#define RC32334_NR_IRQS (GROUP14_IRQ_BASE + 1)
3031 +
3032 +/* 16550 UARTs */
3033 +#ifdef __MIPSEB__
3034 +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0803)
3035 +#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0823)
3036 +#else
3037 +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0800)
3038 +#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0820)
3039 +#endif
3040 +
3041 +#define RC32300_UART0_IRQ GROUP5_IRQ_BASE
3042 +#define RC32300_UART1_IRQ GROUP6_IRQ_BASE
3043 +
3044 +#define IDT_CLOCK_MULT 2
3045 +
3046 +/* NVRAM */
3047 +#define NVRAM_BASE 0x12000000
3048 +#define NVRAM_ENVSIZE_OFF 4
3049 +#define NVRAM_ENVSTART_OFF 0x40
3050 +
3051 +/* LCD 4-digit display */
3052 +#define LCD_CLEAR 0x14000400
3053 +#define LCD_DIGIT0 0x1400000f
3054 +#define LCD_DIGIT1 0x14000008
3055 +#define LCD_DIGIT2 0x14000007
3056 +#define LCD_DIGIT3 0x14000003
3057 +
3058 +/* Interrupts routed on 79S334A board (see rc32334.h) */
3059 +#define RC32334_SCC8530_IRQ 2
3060 +#define RC32334_PCI_INTA_IRQ 3
3061 +#define RC32334_PCI_INTB_IRQ 4
3062 +#define RC32334_PCI_INTC_IRQ 6
3063 +#define RC32334_PCI_INTD_IRQ 7
3064 +
3065 +#define RAM_SIZE (32*1024*1024)
3066 +
3067 +#endif // __IDT_RC32334_H__
3068 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355_dma.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355_dma.h
3069 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355_dma.h 1970-01-01 01:00:00.000000000 +0100
3070 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355_dma.h 2006-06-18 12:44:28.000000000 +0200
3071 @@ -0,0 +1,206 @@
3072 +/**************************************************************************
3073 + *
3074 + * BRIEF MODULE DESCRIPTION
3075 + * DMA controller defines on IDT RC32355
3076 + *
3077 + * Copyright 2004 IDT Inc.
3078 + * Author: Integrated Device Technology Inc. rischelp@idt.com
3079 + *
3080 + *
3081 + * This program is free software; you can redistribute it and/or modify it
3082 + * under the terms of the GNU General Public License as published by the
3083 + * Free Software Foundation; either version 2 of the License, or (at your
3084 + * option) any later version.
3085 + *
3086 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3087 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3088 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3089 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3090 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3091 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3092 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3093 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3094 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3095 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3096 + *
3097 + * You should have received a copy of the GNU General Public License along
3098 + * with this program; if not, write to the Free Software Foundation, Inc.,
3099 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3100 + *
3101 + *
3102 + * May 2004 rkt
3103 + * Initial Release
3104 + *
3105 + **************************************************************************
3106 + */
3107 +
3108 +#ifndef BANYAN_DMA_H
3109 +#define BANYAN_DMA_H
3110 +#include <asm/idt-boards/rc32300/rc32300.h>
3111 +
3112 +/*
3113 + * An image of one RC32355 dma channel registers
3114 + */
3115 +typedef struct {
3116 + u32 dmac;
3117 + u32 dmas;
3118 + u32 dmasm;
3119 + u32 dmadptr;
3120 + u32 dmandptr;
3121 +} rc32355_dma_ch_t;
3122 +
3123 +/*
3124 + * An image of all RC32355 dma channel registers
3125 + */
3126 +typedef struct {
3127 + rc32355_dma_ch_t ch[16];
3128 +} rc32355_dma_regs_t;
3129 +
3130 +
3131 +#define rc32355_dma_regs ((rc32355_dma_regs_t*)KSEG1ADDR(RC32355_DMA_BASE))
3132 +
3133 +
3134 +/* DMAC register layout */
3135 +
3136 +#define DMAC_RUN 0x1 /* Halts processing when cleared */
3137 +#define DMAC_DM 0x2 /* Done Mask, ignore DMA events */
3138 +#define DMAC_MODE_MASK 0xC /* DMA operating mode */
3139 +
3140 +#define DMAC_MODE_AUTO 0x0 /* DMA Auto Request Mode */
3141 +#define DMAC_MODE_BURST 0x4 /* DMA Burst Request Mode */
3142 +#define DMAC_MODE_TFER 0x8 /* DMA Transfer Request Mode */
3143 +
3144 +/* DMAS and DMASM register layout */
3145 +
3146 +#define DMAS_F 0x01 /* Finished */
3147 +#define DMAS_D 0x02 /* Done */
3148 +#define DMAS_C 0x04 /* Chain */
3149 +#define DMAS_E 0x08 /* Error */
3150 +#define DMAS_H 0x10 /* Halt */
3151 +
3152 +/* Polling count for DMAS_H bit in DMAS register after halting DMA */
3153 +#define DMA_HALT_TIMEOUT 500
3154 +
3155 +
3156 +static inline int rc32355_halt_dma(rc32355_dma_ch_t* ch)
3157 +{
3158 + int timeout=1;
3159 +
3160 + if (local_readl(&ch->dmac) & DMAC_RUN) {
3161 + local_writel(0, &ch->dmac);
3162 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
3163 + if (local_readl(&ch->dmas) & DMAS_H) {
3164 + local_writel(0, &ch->dmas);
3165 + break;
3166 + }
3167 + }
3168 + }
3169 +
3170 + return timeout ? 0 : 1;
3171 +}
3172 +
3173 +static inline void rc32355_start_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
3174 +{
3175 + local_writel(0, &ch->dmandptr);
3176 + local_writel(dma_addr, &ch->dmadptr);
3177 +}
3178 +
3179 +static inline void rc32355_chain_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
3180 +{
3181 + local_writel(dma_addr, &ch->dmandptr);
3182 +}
3183 +
3184 +
3185 +/* The following can be used to describe DMA channels 0 to 15, and the */
3186 +/* sub device's needed to select them in the DMADESC_DS_MASK field */
3187 +
3188 +#define DMA_CHAN_ATM01 0 /* ATM interface 0,1 chan */
3189 +
3190 +#define DMA_CHAN_ATM0IN 0 /* ATM interface 0 input */
3191 +#define DMA_DEV_ATM0IN 0 /* ATM interface 0 input */
3192 +
3193 +#define DMA_CHAN_ATM1IN 0 /* ATM interface 1 input */
3194 +#define DMA_DEV_ATM1IN 1 /* ATM interface 1 input */
3195 +
3196 +#define DMA_CHAN_ATM0OUT 0 /* ATM interface 0 output */
3197 +#define DMA_DEV_ATM0OUT 2 /* ATM interface 0 output */
3198 +
3199 +#define DMA_CHAN_ATM1OUT 0 /* ATM interface 1 output */
3200 +#define DMA_DEV_ATM1OUT 3 /* ATM interface 1 output */
3201 +
3202 +/* for entry in {0,1,2,3,4,5,6,7} - note 5,6,7 share with those below */
3203 +#define DMA_CHAN_ATMVCC(entry) ((entry)+1) /* ATM VC cache entry */
3204 +#define DMA_DEV_ATMVCC(entry) 0
3205 +
3206 +#define DMA_CHAN_MEMTOMEM 6 /* Memory to memory DMA */
3207 +#define DMA_DEV_MEMTOMEM 1 /* Memory to memory DMA */
3208 +
3209 +#define DMA_CHAN_ATMFMB0 7 /* ATM Frame Mode Buffer 0 */
3210 +#define DMA_DEV_ATMFMB0 1 /* ATM Frame Mode Buffer 0 */
3211 +
3212 +#define DMA_CHAN_ATMFMB1 8 /* ATM Frame Mode Buffer 1 */
3213 +#define DMA_DEV_ATMFMB1 1 /* ATM Frame Mode Buffer 1 */
3214 +
3215 +#define DMA_CHAN_ETHERIN 9 /* Ethernet input */
3216 +#define DMA_DEV_ETHERIN 0 /* Ethernet input */
3217 +
3218 +#define DMA_CHAN_ETHEROUT 10 /* Ethernet output */
3219 +#define DMA_DEV_ETHEROUT 0 /* Ethernet output */
3220 +
3221 +#define DMA_CHAN_TDMIN 11 /* TDM Bus input */
3222 +#define DMA_DEV_TDMIN 0 /* TDM Bus input */
3223 +
3224 +#define DMA_CHAN_TDMOUT 12 /* TDM Bus output */
3225 +#define DMA_DEV_TDMOUT 0 /* TDM Bus output */
3226 +
3227 +#define DMA_CHAN_USBIN 13 /* USB input */
3228 +#define DMA_DEV_USBIN 0 /* USB input */
3229 +
3230 +#define DMA_CHAN_USBOUT 14 /* USB output */
3231 +#define DMA_DEV_USBOUT 0 /* USB output */
3232 +
3233 +#define DMA_CHAN_EXTERN 15 /* External DMA */
3234 +#define DMA_DEV_EXTERN 0 /* External DMA */
3235 +
3236 +/*
3237 + * An RC32355 dma descriptor in system memory
3238 + */
3239 +typedef struct {
3240 + u32 cmdstat; /* control and status */
3241 + u32 curr_addr; /* current address of data */
3242 + u32 devcs; /* peripheral-specific control and status */
3243 + u32 link; /* link to next descriptor */
3244 +} rc32355_dma_desc_t;
3245 +
3246 +/* Values for the descriptor cmdstat word */
3247 +
3248 +#define DMADESC_F 0x80000000u /* Finished bit */
3249 +#define DMADESC_D 0x40000000u /* Done bit */
3250 +#define DMADESC_T 0x20000000u /* Terminated bit */
3251 +#define DMADESC_IOD 0x10000000u /* Interrupt On Done */
3252 +#define DMADESC_IOF 0x08000000u /* Interrupt On Finished */
3253 +#define DMADESC_COD 0x04000000u /* Chain On Done */
3254 +#define DMADESC_COF 0x02000000u /* Chain On Finished */
3255 +
3256 +#define DMADESC_DEVCMD_MASK 0x01C00000u /* Device Command mask */
3257 +#define DMADESC_DEVCMD_SHIFT 22 /* Device Command shift */
3258 +
3259 +#define DMADESC_DS_MASK 0x00300000u /* Device Select mask */
3260 +#define DMADESC_DS_SHIFT 20 /* Device Select shift */
3261 +
3262 +#define DMADESC_COUNT_MASK 0x0003FFFFu /* Byte Count mask */
3263 +#define DMADESC_COUNT_SHIFT 0 /* Byte Count shift */
3264 +
3265 +#define IS_DMA_FINISHED(X) ( ( (X) & DMADESC_F ) >> 31) /* F Bit */
3266 +#define IS_DMA_DONE(X) ( ( (X) & DMADESC_D ) >> 30) /* D Bit */
3267 +#define IS_DMA_TERMINATED(X) ( ( (X) & DMADESC_T ) >> 29) /* T Bit */
3268 +#define IS_DMA_USED(X) (((X) & (DMADESC_F | DMADESC_D | DMADESC_T)) != 0)
3269 +
3270 +#define DMA_DEVCMD(devcmd) \
3271 + (((devcmd) << DMADESC_DEVCMD_SHIFT) & DMADESC_DS_MASK)
3272 +#define DMA_DS(ds) \
3273 + (((ds) << DMADESC_DS_SHIFT) & DMADESC_DS_MASK)
3274 +#define DMA_COUNT(count) \
3275 + ((count) & DMADESC_COUNT_MASK)
3276 +
3277 +#endif /* RC32355_DMA_H */
3278 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355_eth.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355_eth.h
3279 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355_eth.h 1970-01-01 01:00:00.000000000 +0100
3280 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355_eth.h 2006-06-18 12:44:28.000000000 +0200
3281 @@ -0,0 +1,442 @@
3282 +/**************************************************************************
3283 + *
3284 + * BRIEF MODULE DESCRIPTION
3285 + * Ethernet registers on IDT RC32355
3286 + *
3287 + * Copyright 2004 IDT Inc.
3288 + * Author: Integrated Device Technology Inc. rischelp@idt.com
3289 + *
3290 + *
3291 + * This program is free software; you can redistribute it and/or modify it
3292 + * under the terms of the GNU General Public License as published by the
3293 + * Free Software Foundation; either version 2 of the License, or (at your
3294 + * option) any later version.
3295 + *
3296 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3297 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3298 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3299 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3300 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3301 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3302 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3303 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3304 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3305 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3306 + *
3307 + * You should have received a copy of the GNU General Public License along
3308 + * with this program; if not, write to the Free Software Foundation, Inc.,
3309 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3310 + *
3311 + *
3312 + * May 2004 rkt
3313 + * Initial Release
3314 + *
3315 + **************************************************************************
3316 + */
3317 +
3318 +
3319 +#ifndef RC32355_ETHER_H
3320 +#define RC32355_ETHER_H
3321 +
3322 +#include <asm/idt-boards/rc32300/rc32355_dma.h>
3323 +
3324 +/*
3325 + * A partial image of the RC32355 ethernet registers
3326 + */
3327 +typedef struct {
3328 + u32 ethintfc;
3329 + u32 ethfifott;
3330 + u32 etharc;
3331 + u32 ethhash0;
3332 + u32 ethhash1;
3333 + u32 ethfifost;
3334 + u32 ethfifos;
3335 + u32 ethodeops;
3336 + u32 ethis;
3337 + u32 ethos;
3338 + u32 ethmcp;
3339 + u32 _u1;
3340 + u32 ethid;
3341 + u32 _u2;
3342 + u32 _u3;
3343 + u32 _u4;
3344 + u32 ethod;
3345 + u32 _u5;
3346 + u32 _u6;
3347 + u32 _u7;
3348 + u32 ethodeop;
3349 + u32 _u8[43];
3350 + u32 ethsal0;
3351 + u32 ethsah0;
3352 + u32 ethsal1;
3353 + u32 ethsah1;
3354 + u32 ethsal2;
3355 + u32 ethsah2;
3356 + u32 ethsal3;
3357 + u32 ethsah3;
3358 + u32 ethrbc;
3359 + u32 ethrpc;
3360 + u32 ethrupc;
3361 + u32 ethrfc;
3362 + u32 ethtbc;
3363 + u32 ethgpf;
3364 + u32 _u9[50];
3365 + u32 ethmac1;
3366 + u32 ethmac2;
3367 + u32 ethipgt;
3368 + u32 ethipgr;
3369 + u32 ethclrt;
3370 + u32 ethmaxf;
3371 + u32 _u10;
3372 + u32 ethmtest;
3373 + u32 miimcfg;
3374 + u32 miimcmd;
3375 + u32 miimaddr;
3376 + u32 miimwtd;
3377 + u32 miimrdd;
3378 + u32 miimind;
3379 + u32 _u11;
3380 + u32 _u12;
3381 + u32 ethcfsa0;
3382 + u32 ethcfsa1;
3383 + u32 ethcfsa2;
3384 +} rc32355_eth_regs_t;
3385 +
3386 +#define rc32355_eth_regs ((rc32355_eth_regs_t*)KSEG1ADDR(RC32355_ETH_BASE))
3387 +
3388 +#define ETH_INTFC (RC32355_ETH_BASE + 0x000) /* INTerFace Control */
3389 +#define ETH_FIFOTT (RC32355_ETH_BASE + 0x004) /* FIFO Transmit Threshold */
3390 +#define ETH_ARC (RC32355_ETH_BASE + 0x008) /* Address Recognition Ctrl */
3391 +#define ETH_HASH0 (RC32355_ETH_BASE + 0x00C) /* 32 multicast Hash bits */
3392 +#define ETH_HASH1 (RC32355_ETH_BASE + 0x010) /* another 32 Hash bits */
3393 +#define ETH_FIFOST (RC32355_ETH_BASE + 0x014) /* FIFO Status Threshold */
3394 +#define ETH_FIFOS (RC32355_ETH_BASE + 0x018) /* FIFO Status Register */
3395 +#define ETH_ODEOPS (RC32355_ETH_BASE + 0x01C) /* Out Data End-Of-Pkt Size */
3396 +#define ETH_IS (RC32355_ETH_BASE + 0x020) /* Input Status */
3397 +#define ETH_OS (RC32355_ETH_BASE + 0x024) /* Output Status */
3398 +#define ETH_MCP (RC32355_ETH_BASE + 0x028) /* Managemt Clock Prescaler */
3399 +#define ETH_ID (RC32355_ETH_BASE + 0x030) /* Input Data register */
3400 +#define ETH_OD (RC32355_ETH_BASE + 0x040) /* Output Data register */
3401 +#define ETH_ODEOP (RC32355_ETH_BASE + 0x050) /* OD End-Of-Packet Size */
3402 +
3403 +/* for n in { 0, 1, 2, 3 } */
3404 +#define ETH_SAL(n) (RC32355_ETH_BASE + 0x100 + (n * 8)) /* Stn Address 2-5 */
3405 +#define ETH_SAH(n) (RC32355_ETH_BASE + 0x104 + (n * 8)) /* Stn Address 0-1 */
3406 +
3407 +#define ETH_RBC (RC32355_ETH_BASE + 0x120) /* Receive Byte Count */
3408 +#define ETH_RPC (RC32355_ETH_BASE + 0x124) /* Receive Packet Count */
3409 +#define ETH_RUPC (RC32355_ETH_BASE + 0x128) /* Rx Undersized Pkt count */
3410 +#define ETH_RFC (RC32355_ETH_BASE + 0x12C) /* Receive Fragment Count */
3411 +#define ETH_TBC (RC32355_ETH_BASE + 0x130) /* Transmit Byte Count */
3412 +#define ETH_GPF (RC32355_ETH_BASE + 0x134) /* Generate Pause Frame */
3413 +#define ETH_MAC1 (RC32355_ETH_BASE + 0x200) /* Medium Access Control 1 */
3414 +#define ETH_MAC2 (RC32355_ETH_BASE + 0x204) /* Medium Access Control 2 */
3415 +#define ETH_IPGT (RC32355_ETH_BASE + 0x208) /* Back-to-back InterPkt Gap */
3416 +#define ETH_IPGR (RC32355_ETH_BASE + 0x20C) /* Non " InterPkt Gap */
3417 +#define ETH_CLRT (RC32355_ETH_BASE + 0x210) /* Collis'n Window and Retry */
3418 +#define ETH_MAXF (RC32355_ETH_BASE + 0x214) /* Maximum Frame Length */
3419 +#define ETH_MTEST (RC32355_ETH_BASE + 0x21C) /* MAC Test */
3420 +
3421 +#define ETHMIIM_CFG (RC32355_ETH_BASE + 0x220) /* MII Mgmt Configuration */
3422 +#define ETHMIIM_CMD (RC32355_ETH_BASE + 0x224) /* MII Mgmt Command */
3423 +#define ETHMIIM_ADDR (RC32355_ETH_BASE + 0x228) /* MII Mgmt Address */
3424 +#define ETHMIIM_WTD (RC32355_ETH_BASE + 0x22C) /* MII Mgmt Write Data */
3425 +#define ETHMIIM_RDD (RC32355_ETH_BASE + 0x230) /* MII Mgmt Read Data */
3426 +#define ETHMIIM_IND (RC32355_ETH_BASE + 0x234) /* MII Mgmt Indicators */
3427 +
3428 +/* for n in { 0, 1, 2 } */
3429 +#define ETH_CFSA(n) (RC32355_ETH_BASE + 0x240 + ((n) * 4)) /* Station Addr */
3430 +
3431 +
3432 +/*
3433 + * Register Interpretations follow
3434 + */
3435 +
3436 +/******************************************************************************
3437 + * ETHINTFC register
3438 + *****************************************************************************/
3439 +
3440 +#define ETHERINTFC_EN (1<<0)
3441 +#define ETHERINTFC_ITS (1<<1)
3442 +#define ETHERINTFC_RES (1<<2)
3443 +#define ETHERINTFC_RIP (1<<2)
3444 +#define ETHERINTFC_JAM (1<<3)
3445 +
3446 +/******************************************************************************
3447 + * ETHFIFOTT register
3448 + *****************************************************************************/
3449 +
3450 +#define ETHERFIFOTT_TTH(v) (((v)&0x3f)<<0)
3451 +
3452 +/******************************************************************************
3453 + * ETHARC register
3454 + *****************************************************************************/
3455 +
3456 +#define ETHERARC_PRO (1<<0)
3457 +#define ETHERARC_AM (1<<1)
3458 +#define ETHERARC_AFM (1<<2)
3459 +#define ETHERARC_AB (1<<3)
3460 +
3461 +/******************************************************************************
3462 + * ETHHASH registers
3463 + *****************************************************************************/
3464 +
3465 +#define ETHERHASH0(v) (((v)&0xffff)<<0)
3466 +#define ETHERHASH1(v) (((v)&0xffff)<<0)
3467 +
3468 +/******************************************************************************
3469 + * ETHSA registers
3470 + *****************************************************************************/
3471 +
3472 +#define ETHERSAL0(v) (((v)&0xffff)<<0)
3473 +#define ETHERSAL1(v) (((v)&0xffff)<<0)
3474 +#define ETHERSAL2(v) (((v)&0xffff)<<0)
3475 +#define ETHERSAL3(v) (((v)&0xffff)<<0)
3476 +#define ETHERSAH0(v) (((v)&0xff)<<0)
3477 +#define ETHERSAH1(v) (((v)&0xff)<<0)
3478 +#define ETHERSAH2(v) (((v)&0xff)<<0)
3479 +#define ETHERSAH3(v) (((v)&0xff)<<0)
3480 +
3481 +/******************************************************************************
3482 + * ETHFIFOST register
3483 + *****************************************************************************/
3484 +
3485 +#define ETHERFIFOST_IRTH(v) (((v)&0x3f)<<0)
3486 +#define ETHERFIFOST_ORTH(v) (((v)&0x3f)<<16)
3487 +
3488 +/******************************************************************************
3489 + * ETHFIFOS register
3490 + *****************************************************************************/
3491 +
3492 +#define ETHERFIFOS_IR (1<<0)
3493 +#define ETHERFIFOS_OR (1<<1)
3494 +#define ETHERFIFOS_OVR (1<<2)
3495 +#define ETHERFIFOS_UND (1<<3)
3496 +
3497 +/******************************************************************************
3498 + * DATA registers
3499 + *****************************************************************************/
3500 +
3501 +#define ETHERID(v) (((v)&0xffff)<<0)
3502 +#define ETHEROD(v) (((v)&0xffff)<<0)
3503 +
3504 +/******************************************************************************
3505 + * ETHODEOPS register
3506 + *****************************************************************************/
3507 +
3508 +#define ETHERODEOPS_SIZE(v) (((v)&0x3)<<0)
3509 +
3510 +/******************************************************************************
3511 + * ETHODEOP register
3512 + *****************************************************************************/
3513 +
3514 +#define ETHERODEOP(v) (((v)&0xffff)<<0)
3515 +
3516 +/******************************************************************************
3517 + * ETHIS register
3518 + *****************************************************************************/
3519 +
3520 +#define ETHERIS_EOP (1<<0)
3521 +#define ETHERIS_ROK (1<<2)
3522 +#define ETHERIS_FM (1<<3)
3523 +#define ETHERIS_MP (1<<4)
3524 +#define ETHERIS_BP (1<<5)
3525 +#define ETHERIS_VLT (1<<6)
3526 +#define ETHERIS_CF (1<<7)
3527 +#define ETHERIS_OVR (1<<8)
3528 +#define ETHERIS_CRC (1<<9)
3529 +#define ETHERIS_CV (1<<10)
3530 +#define ETHERIS_DB (1<<11)
3531 +#define ETHERIS_LE (1<<12)
3532 +#define ETHERIS_LOR (1<<13)
3533 +#define ETHERIS_SIZE(v) (((v)&0x3)<<14)
3534 +#define ETHERIS_LENGTH(v) (((v)&0xff)<<16)
3535 +
3536 +/******************************************************************************
3537 + * ETHOS register
3538 + *****************************************************************************/
3539 +
3540 +#define ETHEROS_T (1<<0)
3541 +#define ETHEROS_TOK (1<<6)
3542 +#define ETHEROS_MP (1<<7)
3543 +#define ETHEROS_BP (1<<8)
3544 +#define ETHEROS_UND (1<<9)
3545 +#define ETHEROS_OF (1<<10)
3546 +#define ETHEROS_ED (1<<11)
3547 +#define ETHEROS_EC (1<<12)
3548 +#define ETHEROS_LC (1<<13)
3549 +#define ETHEROS_TD (1<<14)
3550 +#define ETHEROS_CRC (1<<15)
3551 +#define ETHEROS_LE (1<<16)
3552 +#define ETHEROS_CC(v) (((v)&0xf)<<17)
3553 +#define ETHEROS_PFD (1<<21)
3554 +
3555 +/******************************************************************************
3556 + * Statistics registers
3557 + *****************************************************************************/
3558 +
3559 +#define ETHERRBC(v) (((v)&0xffff)<<0)
3560 +#define ETHERRPC(v) (((v)&0xffff)<<0)
3561 +#define ETHERRUPC(v) (((v)&0xffff)<<0)
3562 +#define ETHERRFC(v) (((v)&0xffff)<<0)
3563 +#define ETHERTBC(v) (((v)&0xffff)<<0)
3564 +
3565 +/******************************************************************************
3566 + * ETHGPF register
3567 + *****************************************************************************/
3568 +
3569 +#define ETHERGPF_PTV(v) (((v)&0xff)<<0)
3570 +
3571 +/******************************************************************************
3572 + * MAC registers
3573 + *****************************************************************************/
3574 +//ETHMAC1
3575 +#define ETHERMAC1_RE (1<<0)
3576 +#define ETHERMAC1_PAF (1<<1)
3577 +#define ETHERMAC1_RFC (1<<2)
3578 +#define ETHERMAC1_TFC (1<<3)
3579 +#define ETHERMAC1_LB (1<<4)
3580 +#define ETHERMAC1_MR (1<<15)
3581 +
3582 +//ETHMAC2
3583 +#define ETHERMAC2_FD (1<<0)
3584 +#define ETHERMAC2_FLC (1<<1)
3585 +#define ETHERMAC2_HFE (1<<2)
3586 +#define ETHERMAC2_DC (1<<3)
3587 +#define ETHERMAC2_CEN (1<<4)
3588 +#define ETHERMAC2_PE (1<<5)
3589 +#define ETHERMAC2_VPE (1<<6)
3590 +#define ETHERMAC2_APE (1<<7)
3591 +#define ETHERMAC2_PPE (1<<8)
3592 +#define ETHERMAC2_LPE (1<<9)
3593 +#define ETHERMAC2_NB (1<<12)
3594 +#define ETHERMAC2_BP (1<<13)
3595 +#define ETHERMAC2_ED (1<<14)
3596 +
3597 +//ETHIPGT
3598 +#define ETHERIPGT(v) (((v)&0x3f)<<0)
3599 +
3600 +//ETHIPGR
3601 +#define ETHERIPGR_IPGR1(v) (((v)&0x3f)<<0)
3602 +#define ETHERIPGR_IPGR2(v) (((v)&0x3f)<<8)
3603 +
3604 +//ETHCLRT
3605 +#define ETHERCLRT_MAXRET(v) (((v)&0x3f)<<0)
3606 +#define ETHERCLRT_COLWIN(v) (((v)&0x3f)<<8)
3607 +
3608 +//ETHMAXF
3609 +#define ETHERMAXF(v) (((v)&0x3f)<<0)
3610 +
3611 +//ETHMTEST
3612 +#define ETHERMTEST_TB (1<<2)
3613 +
3614 +//ETHMCP
3615 +#define ETHERMCP_DIV(v) (((v)&0xff)<<0)
3616 +
3617 +//MIIMCFG
3618 +#define ETHERMIIMCFG_CS(v) (((v)&0x3)<<2)
3619 +#define ETHERMIIMCFG_R (1<<15)
3620 +
3621 +//MIIMCMD
3622 +#define ETHERMIIMCMD_RD (1<<0)
3623 +#define ETHERMIIMCMD_SCN (1<<1)
3624 +
3625 +//MIIMADDR
3626 +#define ETHERMIIMADDR_REGADDR(v) (((v)&0x1f)<<0)
3627 +#define ETHERMIIMADDR_PHYADDR(v) (((v)&0x1f)<<8)
3628 +
3629 +//MIIMWTD
3630 +#define ETHERMIIMWTD(v) (((v)&0xff)<<0)
3631 +
3632 +//MIIMRDD
3633 +#define ETHERMIIMRDD(v) (((v)&0xff)<<0)
3634 +
3635 +//MIIMIND
3636 +#define ETHERMIIMIND_BSY (1<<0)
3637 +#define ETHERMIIMIND_SCN (1<<1)
3638 +#define ETHERMIIMIND_NV (1<<2)
3639 +
3640 +//DMA DEVCS IN
3641 +#define ETHERDMA_IN_LENGTH(v) (((v)&0xffff)<<16)
3642 +#define ETHERDMA_IN_CES (1<<14)
3643 +#define ETHERDMA_IN_LOR (1<<13)
3644 +#define ETHERDMA_IN_LE (1<<12)
3645 +#define ETHERDMA_IN_DB (1<<11)
3646 +#define ETHERDMA_IN_CV (1<<10)
3647 +#define ETHERDMA_IN_CRC (1<<9)
3648 +#define ETHERDMA_IN_OVR (1<<8)
3649 +#define ETHERDMA_IN_CF (1<<7)
3650 +#define ETHERDMA_IN_VLT (1<<6)
3651 +#define ETHERDMA_IN_BP (1<<5)
3652 +#define ETHERDMA_IN_MP (1<<4)
3653 +#define ETHERDMA_IN_FM (1<<3)
3654 +#define ETHERDMA_IN_ROK (1<<2)
3655 +#define ETHERDMA_IN_LD (1<<1)
3656 +#define ETHERDMA_IN_FD (1<<0)
3657 +
3658 +//DMA DEVCS OUT
3659 +#define ETHERDMA_OUT_CC(v) (((v)&0xf)<<17)
3660 +#define ETHERDMA_OUT_CNT 0x001e0000
3661 +#define ETHERDMA_OUT_SHFT 17
3662 +#define ETHERDMA_OUT_LE (1<<16)
3663 +
3664 +#define ETHERDMA_OUT_CRC (1<<15)
3665 +#define ETHERDMA_OUT_TD (1<<14)
3666 +#define ETHERDMA_OUT_LC (1<<13)
3667 +#define ETHERDMA_OUT_EC (1<<12)
3668 +#define ETHERDMA_OUT_ED (1<<11)
3669 +#define ETHERDMA_OUT_OF (1<<10)
3670 +#define ETHERDMA_OUT_UND (1<<9)
3671 +#define ETHERDMA_OUT_BP (1<<8)
3672 +#define ETHERDMA_OUT_MP (1<<7)
3673 +#define ETHERDMA_OUT_TOK (1<<6)
3674 +#define ETHERDMA_OUT_HEN (1<<5)
3675 +#define ETHERDMA_OUT_CEN (1<<4)
3676 +#define ETHERDMA_OUT_PEN (1<<3)
3677 +#define ETHERDMA_OUT_OEN (1<<2)
3678 +#define ETHERDMA_OUT_LD (1<<1)
3679 +#define ETHERDMA_OUT_FD (1<<0)
3680 +
3681 +#define RCV_ERRS \
3682 + (ETHERDMA_IN_OVR | ETHERDMA_IN_CRC | ETHERDMA_IN_CV | ETHERDMA_IN_LE)
3683 +#define TX_ERRS \
3684 + (ETHERDMA_OUT_LC | ETHERDMA_OUT_EC | ETHERDMA_OUT_ED | \
3685 + ETHERDMA_OUT_OF | ETHERDMA_OUT_UND)
3686 +
3687 +#define IS_RCV_ROK(X) (((X) & (1<<2)) >> 2) /* Receive Okay */
3688 +#define IS_RCV_FM(X) (((X) & (1<<3)) >> 3) /* Is Filter Match */
3689 +#define IS_RCV_MP(X) (((X) & (1<<4)) >> 4) /* Is it MP */
3690 +#define IS_RCV_BP(X) (((X) & (1<<5)) >> 5) /* Is it BP */
3691 +#define IS_RCV_VLT(X) (((X) & (1<<6)) >> 6) /* VLAN Tag Detect */
3692 +#define IS_RCV_CF(X) (((X) & (1<<7)) >> 7) /* Control Frame */
3693 +#define IS_RCV_OVR_ERR(X) (((X) & (1<<8)) >> 8) /* Receive Overflow */
3694 +#define IS_RCV_CRC_ERR(X) (((X) & (1<<9)) >> 9) /* CRC Error */
3695 +#define IS_RCV_CV_ERR(X) (((X) & (1<<10))>>10) /* Code Violation */
3696 +#define IS_RCV_DB_ERR(X) (((X) & (1<<11))>>11) /* Dribble Bits */
3697 +#define IS_RCV_LE_ERR(X) (((X) & (1<<12))>>12) /* Length error */
3698 +#define IS_RCV_LOR_ERR(X) (((X) & (1<<13))>>13) /* Length Out of
3699 + Range */
3700 +#define IS_RCV_CES_ERR(X) (((X) & (1<<14))>>14) /* Preamble error */
3701 +#define RCVPKT_LENGTH(X) (((X) & 0xFFFF0000)>>16) /* Length of the
3702 + received packet */
3703 +
3704 +#define IS_TX_TOK(X) (((X) & (1<<6) ) >> 6 ) /* Transmit Okay */
3705 +#define IS_TX_MP(X) (((X) & (1<<7) ) >> 7 ) /* Multicast */
3706 +
3707 +#define IS_TX_BP(X) (((X) & (1<<8) ) >> 8 ) /* Broadcast */
3708 +#define IS_TX_UND_ERR(X) (((X) & (1<<9) ) >> 9 ) /* Transmit FIFO
3709 + Underflow */
3710 +#define IS_TX_OF_ERR(X) (((X) & (1<<10)) >>10 ) /* Oversized frame */
3711 +#define IS_TX_ED_ERR(X) (((X) & (1<<11)) >>11 ) /* Excessive
3712 + deferral */
3713 +#define IS_TX_EC_ERR(X) (((X) & (1<<12)) >>12 ) /* Excessive
3714 + collisions */
3715 +#define IS_TX_LC_ERR(X) (((X) & (1<<13)) >>13 ) /* Late Collision */
3716 +#define IS_TX_TD_ERR(X) (((X) & (1<<14)) >>14 ) /* Transmit deferred*/
3717 +#define IS_TX_CRC_ERR(X) (((X) & (1<<15)) >>15 ) /* CRC Error */
3718 +#define IS_TX_LE_ERR(X) (((X) & (1<<16)) >>16 ) /* Length Error */
3719 +
3720 +#define TX_COLLISION_COUNT(X) (((X) & 0x001E0000u)>>17) /* Collision Count */
3721 +
3722 +#endif /* RC32355_ETHER_H */
3723 +
3724 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355.h
3725 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355.h 1970-01-01 01:00:00.000000000 +0100
3726 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355.h 2006-06-18 12:44:28.000000000 +0200
3727 @@ -0,0 +1,177 @@
3728 +/**************************************************************************
3729 + *
3730 + * BRIEF MODULE DESCRIPTION
3731 + * Definitions for IDT RC32355 CPU.
3732 + *
3733 + * Copyright 2004 IDT Inc.
3734 + * Author: Integrated Device Technology Inc. rischelp@idt.com
3735 + *
3736 + *
3737 + * This program is free software; you can redistribute it and/or modify it
3738 + * under the terms of the GNU General Public License as published by the
3739 + * Free Software Foundation; either version 2 of the License, or (at your
3740 + * option) any later version.
3741 + *
3742 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3743 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3744 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3745 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3746 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3747 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3748 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3749 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3750 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3751 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3752 + *
3753 + * You should have received a copy of the GNU General Public License along
3754 + * with this program; if not, write to the Free Software Foundation, Inc.,
3755 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3756 + *
3757 + *
3758 + * May 2004 rkt
3759 + * Initial Release
3760 + *
3761 + **************************************************************************
3762 + */
3763 +
3764 +