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03332b6e30e2de19299aa5b90cf0a65476a740c0
[openwrt/openwrt.git] / target / linux / ath25 / patches-3.18 / 010-board.patch
1 --- a/arch/mips/Kconfig
2 +++ b/arch/mips/Kconfig
3 @@ -96,6 +96,19 @@ config AR7
4 Support for the Texas Instruments AR7 System-on-a-Chip
5 family: TNETD7100, 7200 and 7300.
6
7 +config ATH25
8 + bool "Atheros AR231x/AR531x SoC support"
9 + select CEVT_R4K
10 + select CSRC_R4K
11 + select DMA_NONCOHERENT
12 + select IRQ_CPU
13 + select IRQ_DOMAIN
14 + select SYS_HAS_CPU_MIPS32_R1
15 + select SYS_SUPPORTS_BIG_ENDIAN
16 + select SYS_SUPPORTS_32BIT_KERNEL
17 + help
18 + Support for Atheros AR231x and Atheros AR531x based boards
19 +
20 config ATH79
21 bool "Atheros AR71XX/AR724X/AR913X based boards"
22 select ARCH_REQUIRE_GPIOLIB
23 @@ -835,6 +848,7 @@ config MIPS_PARAVIRT
24 endchoice
25
26 source "arch/mips/alchemy/Kconfig"
27 +source "arch/mips/ath25/Kconfig"
28 source "arch/mips/ath79/Kconfig"
29 source "arch/mips/bcm47xx/Kconfig"
30 source "arch/mips/bcm63xx/Kconfig"
31 --- a/arch/mips/Kbuild.platforms
32 +++ b/arch/mips/Kbuild.platforms
33 @@ -2,6 +2,7 @@
34
35 platforms += alchemy
36 platforms += ar7
37 +platforms += ath25
38 platforms += ath79
39 platforms += bcm47xx
40 platforms += bcm63xx
41 --- /dev/null
42 +++ b/arch/mips/ath25/Platform
43 @@ -0,0 +1,6 @@
44 +#
45 +# Atheros AR531X/AR231X WiSoC
46 +#
47 +platform-$(CONFIG_ATH25) += ath25/
48 +cflags-$(CONFIG_ATH25) += -I$(srctree)/arch/mips/include/asm/mach-ath25
49 +load-$(CONFIG_ATH25) += 0xffffffff80041000
50 --- /dev/null
51 +++ b/arch/mips/ath25/Kconfig
52 @@ -0,0 +1,9 @@
53 +config SOC_AR5312
54 + bool "Atheros AR5312/AR2312+ SoC support"
55 + depends on ATH25
56 + default y
57 +
58 +config SOC_AR2315
59 + bool "Atheros AR2315+ SoC support"
60 + depends on ATH25
61 + default y
62 --- /dev/null
63 +++ b/arch/mips/ath25/Makefile
64 @@ -0,0 +1,13 @@
65 +#
66 +# This file is subject to the terms and conditions of the GNU General Public
67 +# License. See the file "COPYING" in the main directory of this archive
68 +# for more details.
69 +#
70 +# Copyright (C) 2006 FON Technology, SL.
71 +# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
72 +# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
73 +#
74 +
75 +obj-y += board.o prom.o devices.o
76 +obj-$(CONFIG_SOC_AR5312) += ar5312.o
77 +obj-$(CONFIG_SOC_AR2315) += ar2315.o
78 --- /dev/null
79 +++ b/arch/mips/ath25/board.c
80 @@ -0,0 +1,234 @@
81 +/*
82 + * This file is subject to the terms and conditions of the GNU General Public
83 + * License. See the file "COPYING" in the main directory of this archive
84 + * for more details.
85 + *
86 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
87 + * Copyright (C) 2006 FON Technology, SL.
88 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
89 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
90 + */
91 +
92 +#include <linux/init.h>
93 +#include <linux/interrupt.h>
94 +#include <asm/irq_cpu.h>
95 +#include <asm/reboot.h>
96 +#include <asm/bootinfo.h>
97 +#include <asm/time.h>
98 +
99 +#include <ath25_platform.h>
100 +#include "devices.h"
101 +#include "ar5312.h"
102 +#include "ar2315.h"
103 +
104 +void (*ath25_irq_dispatch)(void);
105 +
106 +static inline bool check_radio_magic(const void __iomem *addr)
107 +{
108 + addr += 0x7a; /* offset for flash magic */
109 + return (__raw_readb(addr) == 0x5a) && (__raw_readb(addr + 1) == 0xa5);
110 +}
111 +
112 +static inline bool check_notempty(const void __iomem *addr)
113 +{
114 + return __raw_readl(addr) != 0xffffffff;
115 +}
116 +
117 +static inline bool check_board_data(const void __iomem *addr, bool broken)
118 +{
119 + /* config magic found */
120 + if (__raw_readl(addr) == ATH25_BD_MAGIC)
121 + return true;
122 +
123 + if (!broken)
124 + return false;
125 +
126 + /* broken board data detected, use radio data to find the
127 + * offset, user will fix this */
128 +
129 + if (check_radio_magic(addr + 0x1000))
130 + return true;
131 + if (check_radio_magic(addr + 0xf8))
132 + return true;
133 +
134 + return false;
135 +}
136 +
137 +static const void __iomem * __init find_board_config(const void __iomem *limit,
138 + const bool broken)
139 +{
140 + const void __iomem *addr;
141 + const void __iomem *begin = limit - 0x1000;
142 + const void __iomem *end = limit - 0x30000;
143 +
144 + for (addr = begin; addr >= end; addr -= 0x1000)
145 + if (check_board_data(addr, broken))
146 + return addr;
147 +
148 + return NULL;
149 +}
150 +
151 +static const void __iomem * __init find_radio_config(const void __iomem *limit,
152 + const void __iomem *bcfg)
153 +{
154 + const void __iomem *rcfg, *begin, *end;
155 +
156 + /*
157 + * Now find the start of Radio Configuration data, using heuristics:
158 + * Search forward from Board Configuration data by 0x1000 bytes
159 + * at a time until we find non-0xffffffff.
160 + */
161 + begin = bcfg + 0x1000;
162 + end = limit;
163 + for (rcfg = begin; rcfg < end; rcfg += 0x1000)
164 + if (check_notempty(rcfg) && check_radio_magic(rcfg))
165 + return rcfg;
166 +
167 + /* AR2316 relocates radio config to new location */
168 + begin = bcfg + 0xf8;
169 + end = limit - 0x1000 + 0xf8;
170 + for (rcfg = begin; rcfg < end; rcfg += 0x1000)
171 + if (check_notempty(rcfg) && check_radio_magic(rcfg))
172 + return rcfg;
173 +
174 + return NULL;
175 +}
176 +
177 +/*
178 + * NB: Search region size could be larger than the actual flash size,
179 + * but this shouldn't be a problem here, because the flash
180 + * will simply be mapped multiple times.
181 + */
182 +int __init ath25_find_config(phys_addr_t base, unsigned long size)
183 +{
184 + const void __iomem *flash_base, *flash_limit;
185 + struct ath25_boarddata *config;
186 + unsigned int rcfg_size;
187 + int broken_boarddata = 0;
188 + const void __iomem *bcfg, *rcfg;
189 + u8 *board_data;
190 + u8 *radio_data;
191 + u8 *mac_addr;
192 + u32 offset;
193 +
194 + flash_base = ioremap_nocache(base, size);
195 + flash_limit = flash_base + size;
196 +
197 + ath25_board.config = NULL;
198 + ath25_board.radio = NULL;
199 +
200 + /* Copy the board and radio data to RAM, because accessing the mapped
201 + * memory of the flash directly after booting is not safe */
202 +
203 + /* Try to find valid board and radio data */
204 + bcfg = find_board_config(flash_limit, false);
205 +
206 + /* If that fails, try to at least find valid radio data */
207 + if (!bcfg) {
208 + bcfg = find_board_config(flash_limit, true);
209 + broken_boarddata = 1;
210 + }
211 +
212 + if (!bcfg) {
213 + pr_warn("WARNING: No board configuration data found!\n");
214 + goto error;
215 + }
216 +
217 + board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
218 + ath25_board.config = (struct ath25_boarddata *)board_data;
219 + memcpy_fromio(board_data, bcfg, 0x100);
220 + if (broken_boarddata) {
221 + pr_warn("WARNING: broken board data detected\n");
222 + config = ath25_board.config;
223 + if (is_zero_ether_addr(config->enet0_mac)) {
224 + pr_info("Fixing up empty mac addresses\n");
225 + config->reset_config_gpio = 0xffff;
226 + config->sys_led_gpio = 0xffff;
227 + random_ether_addr(config->wlan0_mac);
228 + config->wlan0_mac[0] &= ~0x06;
229 + random_ether_addr(config->enet0_mac);
230 + random_ether_addr(config->enet1_mac);
231 + }
232 + }
233 +
234 + /* Radio config starts 0x100 bytes after board config, regardless
235 + * of what the physical layout on the flash chip looks like */
236 +
237 + rcfg = find_radio_config(flash_limit, bcfg);
238 + if (!rcfg) {
239 + pr_warn("WARNING: Could not find Radio Configuration data\n");
240 + goto error;
241 + }
242 +
243 + radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
244 + ath25_board.radio = radio_data;
245 + offset = radio_data - board_data;
246 + pr_info("Radio config found at offset 0x%x (0x%x)\n", rcfg - bcfg,
247 + offset);
248 + rcfg_size = BOARD_CONFIG_BUFSZ - offset;
249 + memcpy_fromio(radio_data, rcfg, rcfg_size);
250 +
251 + mac_addr = &radio_data[0x1d * 2];
252 + if (is_broadcast_ether_addr(mac_addr)) {
253 + pr_info("Radio MAC is blank; using board-data\n");
254 + ether_addr_copy(mac_addr, ath25_board.config->wlan0_mac);
255 + }
256 +
257 + iounmap(flash_base);
258 +
259 + return 0;
260 +
261 +error:
262 + iounmap(flash_base);
263 + return -ENODEV;
264 +}
265 +
266 +static void ath25_halt(void)
267 +{
268 + local_irq_disable();
269 + unreachable();
270 +}
271 +
272 +void __init plat_mem_setup(void)
273 +{
274 + _machine_halt = ath25_halt;
275 + pm_power_off = ath25_halt;
276 +
277 + if (is_ar5312())
278 + ar5312_plat_mem_setup();
279 + else
280 + ar2315_plat_mem_setup();
281 +
282 + /* Disable data watchpoints */
283 + write_c0_watchlo0(0);
284 +}
285 +
286 +asmlinkage void plat_irq_dispatch(void)
287 +{
288 + ath25_irq_dispatch();
289 +}
290 +
291 +void __init plat_time_init(void)
292 +{
293 + if (is_ar5312())
294 + ar5312_plat_time_init();
295 + else
296 + ar2315_plat_time_init();
297 +}
298 +
299 +unsigned int __cpuinit get_c0_compare_int(void)
300 +{
301 + return CP0_LEGACY_COMPARE_IRQ;
302 +}
303 +
304 +void __init arch_init_irq(void)
305 +{
306 + clear_c0_status(ST0_IM);
307 + mips_cpu_irq_init();
308 +
309 + /* Initialize interrupt controllers */
310 + if (is_ar5312())
311 + ar5312_arch_init_irq();
312 + else
313 + ar2315_arch_init_irq();
314 +}
315 --- /dev/null
316 +++ b/arch/mips/ath25/prom.c
317 @@ -0,0 +1,26 @@
318 +/*
319 + * This file is subject to the terms and conditions of the GNU General Public
320 + * License. See the file "COPYING" in the main directory of this archive
321 + * for more details.
322 + *
323 + * Copyright MontaVista Software Inc
324 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
325 + * Copyright (C) 2006 FON Technology, SL.
326 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
327 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
328 + */
329 +
330 +/*
331 + * Prom setup file for AR5312/AR231x SoCs
332 + */
333 +
334 +#include <linux/init.h>
335 +#include <asm/bootinfo.h>
336 +
337 +void __init prom_init(void)
338 +{
339 +}
340 +
341 +void __init prom_free_prom_memory(void)
342 +{
343 +}
344 --- /dev/null
345 +++ b/arch/mips/include/asm/mach-ath25/ath25_platform.h
346 @@ -0,0 +1,73 @@
347 +#ifndef __ASM_MACH_ATH25_PLATFORM_H
348 +#define __ASM_MACH_ATH25_PLATFORM_H
349 +
350 +#include <linux/etherdevice.h>
351 +
352 +/*
353 + * This is board-specific data that is stored in a "fixed" location in flash.
354 + * It is shared across operating systems, so it should not be changed lightly.
355 + * The main reason we need it is in order to extract the ethernet MAC
356 + * address(es).
357 + */
358 +struct ath25_boarddata {
359 + u32 magic; /* board data is valid */
360 +#define ATH25_BD_MAGIC 0x35333131 /* "5311", for all 531x/231x platforms */
361 + u16 cksum; /* checksum (starting with BD_REV 2) */
362 + u16 rev; /* revision of this struct */
363 +#define BD_REV 4
364 + char board_name[64]; /* Name of board */
365 + u16 major; /* Board major number */
366 + u16 minor; /* Board minor number */
367 + u32 flags; /* Board configuration */
368 +#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
369 +#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
370 +#define BD_UART1 0x00000004 /* UART1 is stuffed */
371 +#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
372 +#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
373 +#define BD_SYSLED 0x00000020 /* System LED stuffed */
374 +#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
375 +#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
376 +#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
377 +#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
378 +#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ mem_cap for testing */
379 +#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
380 +#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
381 +#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
382 +#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
383 +#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
384 +#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
385 +#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
386 + u16 reset_config_gpio; /* Reset factory GPIO pin */
387 + u16 sys_led_gpio; /* System LED GPIO pin */
388 +
389 + u32 cpu_freq; /* CPU core frequency in Hz */
390 + u32 sys_freq; /* System frequency in Hz */
391 + u32 cnt_freq; /* Calculated C0_COUNT frequency */
392 +
393 + u8 wlan0_mac[ETH_ALEN];
394 + u8 enet0_mac[ETH_ALEN];
395 + u8 enet1_mac[ETH_ALEN];
396 +
397 + u16 pci_id; /* Pseudo PCIID for common code */
398 + u16 mem_cap; /* cap bank1 in MB */
399 +
400 + /* version 3 */
401 + u8 wlan1_mac[ETH_ALEN]; /* (ar5212) */
402 +};
403 +
404 +#define BOARD_CONFIG_BUFSZ 0x1000
405 +
406 +/*
407 + * Platform device information for the Wireless MAC
408 + */
409 +struct ar231x_board_config {
410 + u16 devid;
411 +
412 + /* board config data */
413 + struct ath25_boarddata *config;
414 +
415 + /* radio calibration data */
416 + const char *radio;
417 +};
418 +
419 +#endif /* __ASM_MACH_ATH25_PLATFORM_H */
420 --- /dev/null
421 +++ b/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h
422 @@ -0,0 +1,64 @@
423 +/*
424 + * Atheros AR231x/AR531x SoC specific CPU feature overrides
425 + *
426 + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
427 + *
428 + * This file was derived from: include/asm-mips/cpu-features.h
429 + * Copyright (C) 2003, 2004 Ralf Baechle
430 + * Copyright (C) 2004 Maciej W. Rozycki
431 + *
432 + * This program is free software; you can redistribute it and/or modify it
433 + * under the terms of the GNU General Public License version 2 as published
434 + * by the Free Software Foundation.
435 + *
436 + */
437 +#ifndef __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
438 +#define __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
439 +
440 +/*
441 + * The Atheros AR531x/AR231x SoCs have MIPS 4Kc/4KEc core.
442 + */
443 +#define cpu_has_tlb 1
444 +#define cpu_has_4kex 1
445 +#define cpu_has_3k_cache 0
446 +#define cpu_has_4k_cache 1
447 +#define cpu_has_tx39_cache 0
448 +#define cpu_has_sb1_cache 0
449 +#define cpu_has_fpu 0
450 +#define cpu_has_32fpr 0
451 +#define cpu_has_counter 1
452 +#define cpu_has_ejtag 1
453 +
454 +#if !defined(CONFIG_SOC_AR5312)
455 +# define cpu_has_llsc 1
456 +#else
457 +/*
458 + * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
459 + * ll/sc instructions.
460 + */
461 +# define cpu_has_llsc 0
462 +#endif
463 +
464 +#define cpu_has_mips16 0
465 +#define cpu_has_mdmx 0
466 +#define cpu_has_mips3d 0
467 +#define cpu_has_smartmips 0
468 +
469 +#define cpu_has_mips32r1 1
470 +
471 +#if !defined(CONFIG_SOC_AR5312)
472 +# define cpu_has_mips32r2 1
473 +#endif
474 +
475 +#define cpu_has_mips64r1 0
476 +#define cpu_has_mips64r2 0
477 +
478 +#define cpu_has_dsp 0
479 +#define cpu_has_mipsmt 0
480 +
481 +#define cpu_has_64bits 0
482 +#define cpu_has_64bit_zero_reg 0
483 +#define cpu_has_64bit_gp_regs 0
484 +#define cpu_has_64bit_addresses 0
485 +
486 +#endif /* __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H */
487 --- /dev/null
488 +++ b/arch/mips/include/asm/mach-ath25/dma-coherence.h
489 @@ -0,0 +1,82 @@
490 +/*
491 + * This file is subject to the terms and conditions of the GNU General Public
492 + * License. See the file "COPYING" in the main directory of this archive
493 + * for more details.
494 + *
495 + * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
496 + * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
497 + *
498 + */
499 +#ifndef __ASM_MACH_ATH25_DMA_COHERENCE_H
500 +#define __ASM_MACH_ATH25_DMA_COHERENCE_H
501 +
502 +#include <linux/device.h>
503 +
504 +/*
505 + * We need some arbitrary non-zero value to be programmed to the BAR1 register
506 + * of PCI host controller to enable DMA. The same value should be used as the
507 + * offset to calculate the physical address of DMA buffer for PCI devices.
508 + */
509 +#define AR2315_PCI_HOST_SDRAM_BASEADDR 0x20000000
510 +
511 +static inline dma_addr_t ath25_dev_offset(struct device *dev)
512 +{
513 +#ifdef CONFIG_PCI
514 + extern struct bus_type pci_bus_type;
515 +
516 + if (dev && dev->bus == &pci_bus_type)
517 + return AR2315_PCI_HOST_SDRAM_BASEADDR;
518 +#endif
519 + return 0;
520 +}
521 +
522 +static inline dma_addr_t
523 +plat_map_dma_mem(struct device *dev, void *addr, size_t size)
524 +{
525 + return virt_to_phys(addr) + ath25_dev_offset(dev);
526 +}
527 +
528 +static inline dma_addr_t
529 +plat_map_dma_mem_page(struct device *dev, struct page *page)
530 +{
531 + return page_to_phys(page) + ath25_dev_offset(dev);
532 +}
533 +
534 +static inline unsigned long
535 +plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
536 +{
537 + return dma_addr - ath25_dev_offset(dev);
538 +}
539 +
540 +static inline void
541 +plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, size_t size,
542 + enum dma_data_direction direction)
543 +{
544 +}
545 +
546 +static inline int plat_dma_supported(struct device *dev, u64 mask)
547 +{
548 + return 1;
549 +}
550 +
551 +static inline void plat_extra_sync_for_device(struct device *dev)
552 +{
553 +}
554 +
555 +static inline int plat_dma_mapping_error(struct device *dev,
556 + dma_addr_t dma_addr)
557 +{
558 + return 0;
559 +}
560 +
561 +static inline int plat_device_is_coherent(struct device *dev)
562 +{
563 +#ifdef CONFIG_DMA_COHERENT
564 + return 1;
565 +#endif
566 +#ifdef CONFIG_DMA_NONCOHERENT
567 + return 0;
568 +#endif
569 +}
570 +
571 +#endif /* __ASM_MACH_ATH25_DMA_COHERENCE_H */
572 --- /dev/null
573 +++ b/arch/mips/include/asm/mach-ath25/gpio.h
574 @@ -0,0 +1,16 @@
575 +#ifndef __ASM_MACH_ATH25_GPIO_H
576 +#define __ASM_MACH_ATH25_GPIO_H
577 +
578 +#include <asm-generic/gpio.h>
579 +
580 +#define gpio_get_value __gpio_get_value
581 +#define gpio_set_value __gpio_set_value
582 +#define gpio_cansleep __gpio_cansleep
583 +#define gpio_to_irq __gpio_to_irq
584 +
585 +static inline int irq_to_gpio(unsigned irq)
586 +{
587 + return -EINVAL;
588 +}
589 +
590 +#endif /* __ASM_MACH_ATH25_GPIO_H */
591 --- /dev/null
592 +++ b/arch/mips/include/asm/mach-ath25/war.h
593 @@ -0,0 +1,25 @@
594 +/*
595 + * This file is subject to the terms and conditions of the GNU General Public
596 + * License. See the file "COPYING" in the main directory of this archive
597 + * for more details.
598 + *
599 + * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
600 + */
601 +#ifndef __ASM_MACH_ATH25_WAR_H
602 +#define __ASM_MACH_ATH25_WAR_H
603 +
604 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
605 +#define R4600_V1_HIT_CACHEOP_WAR 0
606 +#define R4600_V2_HIT_CACHEOP_WAR 0
607 +#define R5432_CP0_INTERRUPT_WAR 0
608 +#define BCM1250_M3_WAR 0
609 +#define SIBYTE_1956_WAR 0
610 +#define MIPS4K_ICACHE_REFILL_WAR 0
611 +#define MIPS_CACHE_SYNC_WAR 0
612 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
613 +#define RM9000_CDEX_SMP_WAR 0
614 +#define ICACHE_REFILLS_WORKAROUND_WAR 0
615 +#define R10000_LLSC_WAR 0
616 +#define MIPS34K_MISSED_ITLB_WAR 0
617 +
618 +#endif /* __ASM_MACH_ATH25_WAR_H */
619 --- /dev/null
620 +++ b/arch/mips/ath25/ar2315_regs.h
621 @@ -0,0 +1,410 @@
622 +/*
623 + * Register definitions for AR2315+
624 + *
625 + * This file is subject to the terms and conditions of the GNU General Public
626 + * License. See the file "COPYING" in the main directory of this archive
627 + * for more details.
628 + *
629 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
630 + * Copyright (C) 2006 FON Technology, SL.
631 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
632 + * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
633 + */
634 +
635 +#ifndef __ASM_MACH_ATH25_AR2315_REGS_H
636 +#define __ASM_MACH_ATH25_AR2315_REGS_H
637 +
638 +/*
639 + * IRQs
640 + */
641 +#define AR2315_IRQ_MISC (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */
642 +#define AR2315_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */
643 +#define AR2315_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */
644 +#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */
645 +#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
646 +
647 +/*
648 + * Miscellaneous interrupts, which share IP2.
649 + */
650 +#define AR2315_MISC_IRQ_UART0 0
651 +#define AR2315_MISC_IRQ_I2C_RSVD 1
652 +#define AR2315_MISC_IRQ_SPI 2
653 +#define AR2315_MISC_IRQ_AHB 3
654 +#define AR2315_MISC_IRQ_APB 4
655 +#define AR2315_MISC_IRQ_TIMER 5
656 +#define AR2315_MISC_IRQ_GPIO 6
657 +#define AR2315_MISC_IRQ_WATCHDOG 7
658 +#define AR2315_MISC_IRQ_IR_RSVD 8
659 +#define AR2315_MISC_IRQ_COUNT 9
660 +
661 +/*
662 + * Address map
663 + */
664 +#define AR2315_SPI_READ_BASE 0x08000000 /* SPI flash */
665 +#define AR2315_SPI_READ_SIZE 0x01000000
666 +#define AR2315_WLAN0_BASE 0x10000000 /* Wireless MMR */
667 +#define AR2315_PCI_BASE 0x10100000 /* PCI MMR */
668 +#define AR2315_PCI_SIZE 0x00001000
669 +#define AR2315_SDRAMCTL_BASE 0x10300000 /* SDRAM MMR */
670 +#define AR2315_SDRAMCTL_SIZE 0x00000020
671 +#define AR2315_LOCAL_BASE 0x10400000 /* Local bus MMR */
672 +#define AR2315_ENET0_BASE 0x10500000 /* Ethernet MMR */
673 +#define AR2315_RST_BASE 0x11000000 /* Reset control MMR */
674 +#define AR2315_RST_SIZE 0x00000100
675 +#define AR2315_UART0_BASE 0x11100000 /* UART MMR */
676 +#define AR2315_SPI_MMR_BASE 0x11300000 /* SPI flash MMR */
677 +#define AR2315_SPI_MMR_SIZE 0x00000010
678 +#define AR2315_PCI_EXT_BASE 0x80000000 /* PCI external */
679 +#define AR2315_PCI_EXT_SIZE 0x40000000
680 +
681 +/*
682 + * Configuration registers
683 + */
684 +
685 +/* Cold reset register */
686 +#define AR2315_COLD_RESET 0x0000
687 +
688 +#define AR2315_RESET_COLD_AHB 0x00000001
689 +#define AR2315_RESET_COLD_APB 0x00000002
690 +#define AR2315_RESET_COLD_CPU 0x00000004
691 +#define AR2315_RESET_COLD_CPUWARM 0x00000008
692 +#define AR2315_RESET_SYSTEM (RESET_COLD_CPU |\
693 + RESET_COLD_APB |\
694 + RESET_COLD_AHB) /* full system */
695 +#define AR2317_RESET_SYSTEM 0x00000010
696 +
697 +/* Reset register */
698 +#define AR2315_RESET 0x0004
699 +
700 +#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001 /* warm reset WLAN0 MAC */
701 +#define AR2315_RESET_WARM_WLAN0_BB 0x00000002 /* warm reset WLAN0 BB */
702 +#define AR2315_RESET_MPEGTS_RSVD 0x00000004 /* warm reset MPEG-TS */
703 +#define AR2315_RESET_PCIDMA 0x00000008 /* warm reset PCI ahb/dma */
704 +#define AR2315_RESET_MEMCTL 0x00000010 /* warm reset mem control */
705 +#define AR2315_RESET_LOCAL 0x00000020 /* warm reset local bus */
706 +#define AR2315_RESET_I2C_RSVD 0x00000040 /* warm reset I2C bus */
707 +#define AR2315_RESET_SPI 0x00000080 /* warm reset SPI iface */
708 +#define AR2315_RESET_UART0 0x00000100 /* warm reset UART0 */
709 +#define AR2315_RESET_IR_RSVD 0x00000200 /* warm reset IR iface */
710 +#define AR2315_RESET_EPHY0 0x00000400 /* cold reset ENET0 phy */
711 +#define AR2315_RESET_ENET0 0x00000800 /* cold reset ENET0 MAC */
712 +
713 +/* AHB master arbitration control */
714 +#define AR2315_AHB_ARB_CTL 0x0008
715 +
716 +#define AR2315_ARB_CPU 0x00000001 /* CPU, default */
717 +#define AR2315_ARB_WLAN 0x00000002 /* WLAN */
718 +#define AR2315_ARB_MPEGTS_RSVD 0x00000004 /* MPEG-TS */
719 +#define AR2315_ARB_LOCAL 0x00000008 /* Local bus */
720 +#define AR2315_ARB_PCI 0x00000010 /* PCI bus */
721 +#define AR2315_ARB_ETHERNET 0x00000020 /* Ethernet */
722 +#define AR2315_ARB_RETRY 0x00000100 /* Retry policy (debug) */
723 +
724 +/* Config Register */
725 +#define AR2315_ENDIAN_CTL 0x000c
726 +
727 +#define AR2315_CONFIG_AHB 0x00000001 /* EC-AHB bridge endian */
728 +#define AR2315_CONFIG_WLAN 0x00000002 /* WLAN byteswap */
729 +#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004 /* MPEG-TS byteswap */
730 +#define AR2315_CONFIG_PCI 0x00000008 /* PCI byteswap */
731 +#define AR2315_CONFIG_MEMCTL 0x00000010 /* Mem controller endian */
732 +#define AR2315_CONFIG_LOCAL 0x00000020 /* Local bus byteswap */
733 +#define AR2315_CONFIG_ETHERNET 0x00000040 /* Ethernet byteswap */
734 +#define AR2315_CONFIG_MERGE 0x00000200 /* CPU write buffer merge */
735 +#define AR2315_CONFIG_CPU 0x00000400 /* CPU big endian */
736 +#define AR2315_CONFIG_BIG 0x00000400
737 +#define AR2315_CONFIG_PCIAHB 0x00000800
738 +#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
739 +#define AR2315_CONFIG_SPI 0x00008000 /* SPI byteswap */
740 +#define AR2315_CONFIG_CPU_DRAM 0x00010000
741 +#define AR2315_CONFIG_CPU_PCI 0x00020000
742 +#define AR2315_CONFIG_CPU_MMR 0x00040000
743 +
744 +/* NMI control */
745 +#define AR2315_NMI_CTL 0x0010
746 +
747 +#define AR2315_NMI_EN 1
748 +
749 +/* Revision Register - Initial value is 0x3010 (WMAC 3.0, AR231X 1.0). */
750 +#define AR2315_SREV 0x0014
751 +
752 +#define AR2315_REV_MAJ 0x000000f0
753 +#define AR2315_REV_MAJ_S 4
754 +#define AR2315_REV_MIN 0x0000000f
755 +#define AR2315_REV_MIN_S 0
756 +#define AR2315_REV_CHIP (AR2315_REV_MAJ | AR2315_REV_MIN)
757 +
758 +/* Interface Enable */
759 +#define AR2315_IF_CTL 0x0018
760 +
761 +#define AR2315_IF_MASK 0x00000007
762 +#define AR2315_IF_DISABLED 0 /* Disable all */
763 +#define AR2315_IF_PCI 1 /* PCI */
764 +#define AR2315_IF_TS_LOCAL 2 /* Local bus */
765 +#define AR2315_IF_ALL 3 /* Emulation only */
766 +#define AR2315_IF_LOCAL_HOST 0x00000008
767 +#define AR2315_IF_PCI_HOST 0x00000010
768 +#define AR2315_IF_PCI_INTR 0x00000020
769 +#define AR2315_IF_PCI_CLK_MASK 0x00030000
770 +#define AR2315_IF_PCI_CLK_INPUT 0
771 +#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
772 +#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
773 +#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
774 +#define AR2315_IF_PCI_CLK_SHIFT 16
775 +
776 +/* APB Interrupt control */
777 +#define AR2315_ISR 0x0020
778 +#define AR2315_IMR 0x0024
779 +#define AR2315_GISR 0x0028
780 +
781 +#define AR2315_ISR_UART0 0x00000001 /* high speed UART */
782 +#define AR2315_ISR_I2C_RSVD 0x00000002 /* I2C bus */
783 +#define AR2315_ISR_SPI 0x00000004 /* SPI bus */
784 +#define AR2315_ISR_AHB 0x00000008 /* AHB error */
785 +#define AR2315_ISR_APB 0x00000010 /* APB error */
786 +#define AR2315_ISR_TIMER 0x00000020 /* Timer */
787 +#define AR2315_ISR_GPIO 0x00000040 /* GPIO */
788 +#define AR2315_ISR_WD 0x00000080 /* Watchdog */
789 +#define AR2315_ISR_IR_RSVD 0x00000100 /* IR */
790 +
791 +#define AR2315_GISR_MISC 0x00000001 /* Misc */
792 +#define AR2315_GISR_WLAN0 0x00000002 /* WLAN0 */
793 +#define AR2315_GISR_MPEGTS_RSVD 0x00000004 /* MPEG-TS */
794 +#define AR2315_GISR_LOCALPCI 0x00000008 /* Local/PCI bus */
795 +#define AR2315_GISR_WMACPOLL 0x00000010
796 +#define AR2315_GISR_TIMER 0x00000020
797 +#define AR2315_GISR_ETHERNET 0x00000040 /* Ethernet */
798 +
799 +/* Generic timer */
800 +#define AR2315_TIMER 0x0030
801 +#define AR2315_RELOAD 0x0034
802 +
803 +/* Watchdog timer */
804 +#define AR2315_WDT_TIMER 0x0038
805 +#define AR2315_WDT_CTRL 0x003c
806 +
807 +#define AR2315_WDT_CTRL_IGNORE 0x00000000 /* ignore expiration */
808 +#define AR2315_WDT_CTRL_NMI 0x00000001 /* NMI on watchdog */
809 +#define AR2315_WDT_CTRL_RESET 0x00000002 /* reset on watchdog */
810 +
811 +/* CPU Performance Counters */
812 +#define AR2315_PERFCNT0 0x0048
813 +#define AR2315_PERFCNT1 0x004c
814 +
815 +#define AR2315_PERF0_DATAHIT 0x00000001 /* Count Data Cache Hits */
816 +#define AR2315_PERF0_DATAMISS 0x00000002 /* Count Data Cache Misses */
817 +#define AR2315_PERF0_INSTHIT 0x00000004 /* Count Instruction Cache Hits */
818 +#define AR2315_PERF0_INSTMISS 0x00000008 /* Count Instruction Cache Misses */
819 +#define AR2315_PERF0_ACTIVE 0x00000010 /* Count Active Processor Cycles */
820 +#define AR2315_PERF0_WBHIT 0x00000020 /* Count CPU Write Buffer Hits */
821 +#define AR2315_PERF0_WBMISS 0x00000040 /* Count CPU Write Buffer Misses */
822 +
823 +#define AR2315_PERF1_EB_ARDY 0x00000001 /* Count EB_ARdy signal */
824 +#define AR2315_PERF1_EB_AVALID 0x00000002 /* Count EB_AValid signal */
825 +#define AR2315_PERF1_EB_WDRDY 0x00000004 /* Count EB_WDRdy signal */
826 +#define AR2315_PERF1_EB_RDVAL 0x00000008 /* Count EB_RdVal signal */
827 +#define AR2315_PERF1_VRADDR 0x00000010 /* Count valid read address cycles*/
828 +#define AR2315_PERF1_VWADDR 0x00000020 /* Count valid write address cycl.*/
829 +#define AR2315_PERF1_VWDATA 0x00000040 /* Count valid write data cycles */
830 +
831 +/* AHB Error Reporting */
832 +#define AR2315_AHB_ERR0 0x0050 /* error */
833 +#define AR2315_AHB_ERR1 0x0054 /* haddr */
834 +#define AR2315_AHB_ERR2 0x0058 /* hwdata */
835 +#define AR2315_AHB_ERR3 0x005c /* hrdata */
836 +#define AR2315_AHB_ERR4 0x0060 /* status */
837 +
838 +#define AR2315_AHB_ERROR_DET 1 /* AHB Error has been detected, */
839 + /* write 1 to clear all bits in ERR0 */
840 +#define AR2315_AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
841 +#define AR2315_AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
842 +
843 +#define AR2315_PROCERR_HMAST 0x0000000f
844 +#define AR2315_PROCERR_HMAST_DFLT 0
845 +#define AR2315_PROCERR_HMAST_WMAC 1
846 +#define AR2315_PROCERR_HMAST_ENET 2
847 +#define AR2315_PROCERR_HMAST_PCIENDPT 3
848 +#define AR2315_PROCERR_HMAST_LOCAL 4
849 +#define AR2315_PROCERR_HMAST_CPU 5
850 +#define AR2315_PROCERR_HMAST_PCITGT 6
851 +#define AR2315_PROCERR_HMAST_S 0
852 +#define AR2315_PROCERR_HWRITE 0x00000010
853 +#define AR2315_PROCERR_HSIZE 0x00000060
854 +#define AR2315_PROCERR_HSIZE_S 5
855 +#define AR2315_PROCERR_HTRANS 0x00000180
856 +#define AR2315_PROCERR_HTRANS_S 7
857 +#define AR2315_PROCERR_HBURST 0x00000e00
858 +#define AR2315_PROCERR_HBURST_S 9
859 +
860 +/* Clock Control */
861 +#define AR2315_PLLC_CTL 0x0064
862 +#define AR2315_PLLV_CTL 0x0068
863 +#define AR2315_CPUCLK 0x006c
864 +#define AR2315_AMBACLK 0x0070
865 +#define AR2315_SYNCCLK 0x0074
866 +#define AR2315_DSL_SLEEP_CTL 0x0080
867 +#define AR2315_DSL_SLEEP_DUR 0x0084
868 +
869 +/* PLLc Control fields */
870 +#define AR2315_PLLC_REF_DIV_M 0x00000003
871 +#define AR2315_PLLC_REF_DIV_S 0
872 +#define AR2315_PLLC_FDBACK_DIV_M 0x0000007c
873 +#define AR2315_PLLC_FDBACK_DIV_S 2
874 +#define AR2315_PLLC_ADD_FDBACK_DIV_M 0x00000080
875 +#define AR2315_PLLC_ADD_FDBACK_DIV_S 7
876 +#define AR2315_PLLC_CLKC_DIV_M 0x0001c000
877 +#define AR2315_PLLC_CLKC_DIV_S 14
878 +#define AR2315_PLLC_CLKM_DIV_M 0x00700000
879 +#define AR2315_PLLC_CLKM_DIV_S 20
880 +
881 +/* CPU CLK Control fields */
882 +#define AR2315_CPUCLK_CLK_SEL_M 0x00000003
883 +#define AR2315_CPUCLK_CLK_SEL_S 0
884 +#define AR2315_CPUCLK_CLK_DIV_M 0x0000000c
885 +#define AR2315_CPUCLK_CLK_DIV_S 2
886 +
887 +/* AMBA CLK Control fields */
888 +#define AR2315_AMBACLK_CLK_SEL_M 0x00000003
889 +#define AR2315_AMBACLK_CLK_SEL_S 0
890 +#define AR2315_AMBACLK_CLK_DIV_M 0x0000000c
891 +#define AR2315_AMBACLK_CLK_DIV_S 2
892 +
893 +/* PCI Clock Control */
894 +#define AR2315_PCICLK 0x00a4
895 +
896 +#define AR2315_PCICLK_INPUT_M 0x00000003
897 +#define AR2315_PCICLK_INPUT_S 0
898 +#define AR2315_PCICLK_PLLC_CLKM 0
899 +#define AR2315_PCICLK_PLLC_CLKM1 1
900 +#define AR2315_PCICLK_PLLC_CLKC 2
901 +#define AR2315_PCICLK_REF_CLK 3
902 +#define AR2315_PCICLK_DIV_M 0x0000000c
903 +#define AR2315_PCICLK_DIV_S 2
904 +#define AR2315_PCICLK_IN_FREQ 0
905 +#define AR2315_PCICLK_IN_FREQ_DIV_6 1
906 +#define AR2315_PCICLK_IN_FREQ_DIV_8 2
907 +#define AR2315_PCICLK_IN_FREQ_DIV_10 3
908 +
909 +/* Observation Control Register */
910 +#define AR2315_OCR 0x00b0
911 +
912 +#define AR2315_OCR_GPIO0_IRIN 0x00000040
913 +#define AR2315_OCR_GPIO1_IROUT 0x00000080
914 +#define AR2315_OCR_GPIO3_RXCLR 0x00000200
915 +
916 +/* General Clock Control */
917 +#define AR2315_MISCCLK 0x00b4
918 +
919 +#define AR2315_MISCCLK_PLLBYPASS_EN 0x00000001
920 +#define AR2315_MISCCLK_PROCREFCLK 0x00000002
921 +
922 +/*
923 + * SDRAM Controller
924 + * - No read or write buffers are included.
925 + */
926 +#define AR2315_MEM_CFG 0x0000
927 +#define AR2315_MEM_CTRL 0x000c
928 +#define AR2315_MEM_REF 0x0010
929 +
930 +#define AR2315_MEM_CFG_DATA_WIDTH_M 0x00006000
931 +#define AR2315_MEM_CFG_DATA_WIDTH_S 13
932 +#define AR2315_MEM_CFG_COL_WIDTH_M 0x00001e00
933 +#define AR2315_MEM_CFG_COL_WIDTH_S 9
934 +#define AR2315_MEM_CFG_ROW_WIDTH_M 0x000001e0
935 +#define AR2315_MEM_CFG_ROW_WIDTH_S 5
936 +#define AR2315_MEM_CFG_BANKADDR_BITS_M 0x00000018
937 +#define AR2315_MEM_CFG_BANKADDR_BITS_S 3
938 +
939 +/*
940 + * Local Bus Interface Registers
941 + */
942 +#define AR2315_LB_CONFIG 0x0000
943 +
944 +#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
945 +#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
946 +#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
947 +#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
948 +#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
949 +#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
950 +#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
951 +#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
952 +#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
953 +#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
954 +#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
955 +#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
956 +#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
957 +#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
958 +#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
959 +#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
960 +#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
961 +#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
962 +#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
963 +#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
964 +#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
965 +#define AR2315_LBCONF_INT_CTR3 0x000c0000 /* GND drive, Vdd drive */
966 +#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
967 +#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
968 +#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
969 +
970 +#define AR2315_LB_CLKSEL 0x0004
971 +
972 +#define AR2315_LBCLK_EXT 0x00000001 /* use external clk for lb */
973 +
974 +#define AR2315_LB_1MS 0x0008
975 +
976 +#define AR2315_LB1MS_MASK 0x0003ffff /* # of AHB clk cycles in 1ms */
977 +
978 +#define AR2315_LB_MISCCFG 0x000c
979 +
980 +#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
981 +#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
982 +#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
983 +#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
984 +#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
985 +#define AR2315_LBM_TIMEOUT_M 0x00ffff80
986 +#define AR2315_LBM_TIMEOUT_S 7
987 +#define AR2315_LBM_PORTMUX 0x07000000
988 +
989 +#define AR2315_LB_RXTSOFF 0x0010
990 +
991 +#define AR2315_LB_TX_CHAIN_EN 0x0100
992 +
993 +#define AR2315_LB_TXEN_0 0x00000001
994 +#define AR2315_LB_TXEN_1 0x00000002
995 +#define AR2315_LB_TXEN_2 0x00000004
996 +#define AR2315_LB_TXEN_3 0x00000008
997 +
998 +#define AR2315_LB_TX_CHAIN_DIS 0x0104
999 +#define AR2315_LB_TX_DESC_PTR 0x0200
1000 +
1001 +#define AR2315_LB_RX_CHAIN_EN 0x0400
1002 +
1003 +#define AR2315_LB_RXEN 0x00000001
1004 +
1005 +#define AR2315_LB_RX_CHAIN_DIS 0x0404
1006 +#define AR2315_LB_RX_DESC_PTR 0x0408
1007 +
1008 +#define AR2315_LB_INT_STATUS 0x0500
1009 +
1010 +#define AR2315_LB_INT_TX_DESC 0x00000001
1011 +#define AR2315_LB_INT_TX_OK 0x00000002
1012 +#define AR2315_LB_INT_TX_ERR 0x00000004
1013 +#define AR2315_LB_INT_TX_EOF 0x00000008
1014 +#define AR2315_LB_INT_RX_DESC 0x00000010
1015 +#define AR2315_LB_INT_RX_OK 0x00000020
1016 +#define AR2315_LB_INT_RX_ERR 0x00000040
1017 +#define AR2315_LB_INT_RX_EOF 0x00000080
1018 +#define AR2315_LB_INT_TX_TRUNC 0x00000100
1019 +#define AR2315_LB_INT_TX_STARVE 0x00000200
1020 +#define AR2315_LB_INT_LB_TIMEOUT 0x00000400
1021 +#define AR2315_LB_INT_LB_ERR 0x00000800
1022 +#define AR2315_LB_INT_MBOX_WR 0x00001000
1023 +#define AR2315_LB_INT_MBOX_RD 0x00002000
1024 +
1025 +/* Bit definitions for INT MASK are the same as INT_STATUS */
1026 +#define AR2315_LB_INT_MASK 0x0504
1027 +
1028 +#define AR2315_LB_INT_EN 0x0508
1029 +#define AR2315_LB_MBOX 0x0600
1030 +
1031 +#endif /* __ASM_MACH_ATH25_AR2315_REGS_H */
1032 --- /dev/null
1033 +++ b/arch/mips/ath25/ar5312_regs.h
1034 @@ -0,0 +1,224 @@
1035 +/*
1036 + * This file is subject to the terms and conditions of the GNU General Public
1037 + * License. See the file "COPYING" in the main directory of this archive
1038 + * for more details.
1039 + *
1040 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1041 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1042 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1043 + */
1044 +
1045 +#ifndef __ASM_MACH_ATH25_AR5312_REGS_H
1046 +#define __ASM_MACH_ATH25_AR5312_REGS_H
1047 +
1048 +/*
1049 + * IRQs
1050 + */
1051 +#define AR5312_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */
1052 +#define AR5312_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */
1053 +#define AR5312_IRQ_ENET1 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */
1054 +#define AR5312_IRQ_WLAN1 (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */
1055 +#define AR5312_IRQ_MISC (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
1056 +
1057 +/*
1058 + * Miscellaneous interrupts, which share IP6.
1059 + */
1060 +#define AR5312_MISC_IRQ_TIMER 0
1061 +#define AR5312_MISC_IRQ_AHB_PROC 1
1062 +#define AR5312_MISC_IRQ_AHB_DMA 2
1063 +#define AR5312_MISC_IRQ_GPIO 3
1064 +#define AR5312_MISC_IRQ_UART0 4
1065 +#define AR5312_MISC_IRQ_UART0_DMA 5
1066 +#define AR5312_MISC_IRQ_WATCHDOG 6
1067 +#define AR5312_MISC_IRQ_LOCAL 7
1068 +#define AR5312_MISC_IRQ_SPI 8
1069 +#define AR5312_MISC_IRQ_COUNT 9
1070 +
1071 +/*
1072 + * Address Map
1073 + *
1074 + * The AR5312 supports 2 enet MACS, even though many reference boards only
1075 + * actually use 1 of them (i.e. Only MAC 0 is actually connected to an enet
1076 + * PHY or PHY switch. The AR2312 supports 1 enet MAC.
1077 + */
1078 +#define AR5312_WLAN0_BASE 0x18000000
1079 +#define AR5312_ENET0_BASE 0x18100000
1080 +#define AR5312_ENET1_BASE 0x18200000
1081 +#define AR5312_SDRAMCTL_BASE 0x18300000
1082 +#define AR5312_SDRAMCTL_SIZE 0x00000010
1083 +#define AR5312_FLASHCTL_BASE 0x18400000
1084 +#define AR5312_FLASHCTL_SIZE 0x00000010
1085 +#define AR5312_WLAN1_BASE 0x18500000
1086 +#define AR5312_UART0_BASE 0x1c000000 /* UART MMR */
1087 +#define AR5312_GPIO_BASE 0x1c002000
1088 +#define AR5312_GPIO_SIZE 0x00000010
1089 +#define AR5312_RST_BASE 0x1c003000
1090 +#define AR5312_RST_SIZE 0x00000100
1091 +#define AR5312_FLASH_BASE 0x1e000000
1092 +#define AR5312_FLASH_SIZE 0x00800000
1093 +
1094 +/*
1095 + * Need these defines to determine true number of ethernet MACs
1096 + */
1097 +#define AR5312_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
1098 +#define AR5312_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
1099 +#define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
1100 +
1101 +/* Reset/Timer Block Address Map */
1102 +#define AR5312_TIMER 0x0000 /* countdown timer */
1103 +#define AR5312_RELOAD 0x0004 /* timer reload value */
1104 +#define AR5312_WDT_CTRL 0x0008 /* watchdog cntrl */
1105 +#define AR5312_WDT_TIMER 0x000c /* watchdog timer */
1106 +#define AR5312_ISR 0x0010 /* Intr Status Reg */
1107 +#define AR5312_IMR 0x0014 /* Intr Mask Reg */
1108 +#define AR5312_RESET 0x0020
1109 +#define AR5312_CLOCKCTL1 0x0064
1110 +#define AR5312_SCRATCH 0x006c
1111 +#define AR5312_PROCADDR 0x0070
1112 +#define AR5312_PROC1 0x0074
1113 +#define AR5312_DMAADDR 0x0078
1114 +#define AR5312_DMA1 0x007c
1115 +#define AR5312_ENABLE 0x0080 /* interface enb */
1116 +#define AR5312_REV 0x0090 /* revision */
1117 +
1118 +/* AR5312_WDT_CTRL register bit field definitions */
1119 +#define AR5312_WDT_CTRL_IGNORE 0x00000000 /* ignore expiration */
1120 +#define AR5312_WDT_CTRL_NMI 0x00000001
1121 +#define AR5312_WDT_CTRL_RESET 0x00000002
1122 +
1123 +/* AR5312_ISR register bit field definitions */
1124 +#define AR5312_ISR_TIMER 0x00000001
1125 +#define AR5312_ISR_AHBPROC 0x00000002
1126 +#define AR5312_ISR_AHBDMA 0x00000004
1127 +#define AR5312_ISR_GPIO 0x00000008
1128 +#define AR5312_ISR_UART0 0x00000010
1129 +#define AR5312_ISR_UART0DMA 0x00000020
1130 +#define AR5312_ISR_WD 0x00000040
1131 +#define AR5312_ISR_LOCAL 0x00000080
1132 +
1133 +/* AR5312_RESET register bit field definitions */
1134 +#define AR5312_RESET_SYSTEM 0x00000001 /* cold reset full system */
1135 +#define AR5312_RESET_PROC 0x00000002 /* cold reset MIPS core */
1136 +#define AR5312_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC/BB */
1137 +#define AR5312_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
1138 +#define AR5312_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
1139 +#define AR5312_RESET_ENET0 0x00000020 /* cold reset ENET0 MAC */
1140 +#define AR5312_RESET_ENET1 0x00000040 /* cold reset ENET1 MAC */
1141 +#define AR5312_RESET_UART0 0x00000100 /* cold reset UART0 */
1142 +#define AR5312_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
1143 +#define AR5312_RESET_APB 0x00000400 /* cold reset APB ar5312 */
1144 +#define AR5312_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
1145 +#define AR5312_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
1146 +#define AR5312_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BB */
1147 +#define AR5312_RESET_NMI 0x00010000 /* send an NMI to the CPU */
1148 +#define AR5312_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 MAC */
1149 +#define AR5312_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 BB */
1150 +#define AR5312_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
1151 +#define AR5312_RESET_WDOG 0x00100000 /* last reset was a wdt */
1152 +
1153 +#define AR5312_RESET_WMAC0_BITS (AR5312_RESET_WLAN0 |\
1154 + AR5312_RESET_WARM_WLAN0_MAC |\
1155 + AR5312_RESET_WARM_WLAN0_BB)
1156 +
1157 +#define AR5312_RESET_WMAC1_BITS (AR5312_RESET_WLAN1 |\
1158 + AR5312_RESET_WARM_WLAN1_MAC |\
1159 + AR5312_RESET_WARM_WLAN1_BB)
1160 +
1161 +/* AR5312_CLOCKCTL1 register bit field definitions */
1162 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1163 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1164 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1165 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1166 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1167 +
1168 +/* Valid for AR5312 and AR2312 */
1169 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1170 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1171 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1172 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1173 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1174 +
1175 +/* Valid for AR2313 */
1176 +#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
1177 +#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
1178 +#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
1179 +#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
1180 +#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
1181 +
1182 +/* AR5312_ENABLE register bit field definitions */
1183 +#define AR5312_ENABLE_WLAN0 0x00000001
1184 +#define AR5312_ENABLE_ENET0 0x00000002
1185 +#define AR5312_ENABLE_ENET1 0x00000004
1186 +#define AR5312_ENABLE_UART_AND_WLAN1_PIO 0x00000008/* UART & WLAN1 PIO */
1187 +#define AR5312_ENABLE_WLAN1_DMA 0x00000010/* WLAN1 DMAs */
1188 +#define AR5312_ENABLE_WLAN1 (AR5312_ENABLE_UART_AND_WLAN1_PIO |\
1189 + AR5312_ENABLE_WLAN1_DMA)
1190 +
1191 +/* AR5312_REV register bit field definitions */
1192 +#define AR5312_REV_WMAC_MAJ 0x0000f000
1193 +#define AR5312_REV_WMAC_MAJ_S 12
1194 +#define AR5312_REV_WMAC_MIN 0x00000f00
1195 +#define AR5312_REV_WMAC_MIN_S 8
1196 +#define AR5312_REV_MAJ 0x000000f0
1197 +#define AR5312_REV_MAJ_S 4
1198 +#define AR5312_REV_MIN 0x0000000f
1199 +#define AR5312_REV_MIN_S 0
1200 +#define AR5312_REV_CHIP (AR5312_REV_MAJ|AR5312_REV_MIN)
1201 +
1202 +/* Major revision numbers, bits 7..4 of Revision ID register */
1203 +#define AR5312_REV_MAJ_AR5312 0x4
1204 +#define AR5312_REV_MAJ_AR2313 0x5
1205 +
1206 +/* Minor revision numbers, bits 3..0 of Revision ID register */
1207 +#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
1208 +#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
1209 +
1210 +/*
1211 + * ARM Flash Controller -- 3 flash banks with either x8 or x16 devices
1212 + */
1213 +#define AR5312_FLASHCTL0 0x0000
1214 +#define AR5312_FLASHCTL1 0x0004
1215 +#define AR5312_FLASHCTL2 0x0008
1216 +
1217 +/* AR5312_FLASHCTL register bit field definitions */
1218 +#define AR5312_FLASHCTL_IDCY 0x0000000f /* Idle cycle turnaround time */
1219 +#define AR5312_FLASHCTL_IDCY_S 0
1220 +#define AR5312_FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
1221 +#define AR5312_FLASHCTL_WST1_S 5
1222 +#define AR5312_FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
1223 +#define AR5312_FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
1224 +#define AR5312_FLASHCTL_WST2_S 11
1225 +#define AR5312_FLASHCTL_AC 0x00070000 /* Flash addr check (added) */
1226 +#define AR5312_FLASHCTL_AC_S 16
1227 +#define AR5312_FLASHCTL_AC_128K 0x00000000
1228 +#define AR5312_FLASHCTL_AC_256K 0x00010000
1229 +#define AR5312_FLASHCTL_AC_512K 0x00020000
1230 +#define AR5312_FLASHCTL_AC_1M 0x00030000
1231 +#define AR5312_FLASHCTL_AC_2M 0x00040000
1232 +#define AR5312_FLASHCTL_AC_4M 0x00050000
1233 +#define AR5312_FLASHCTL_AC_8M 0x00060000
1234 +#define AR5312_FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
1235 +#define AR5312_FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
1236 +#define AR5312_FLASHCTL_BUSERR 0x01000000 /* Bus transfer error flag */
1237 +#define AR5312_FLASHCTL_WPERR 0x02000000 /* Write protect error flag */
1238 +#define AR5312_FLASHCTL_WP 0x04000000 /* Write protect */
1239 +#define AR5312_FLASHCTL_BM 0x08000000 /* Burst mode */
1240 +#define AR5312_FLASHCTL_MW 0x30000000 /* Mem width */
1241 +#define AR5312_FLASHCTL_MW8 0x00000000 /* Mem width x8 */
1242 +#define AR5312_FLASHCTL_MW16 0x10000000 /* Mem width x16 */
1243 +#define AR5312_FLASHCTL_MW32 0x20000000 /* Mem width x32 (not supp) */
1244 +#define AR5312_FLASHCTL_ATNR 0x00000000 /* Access == no retry */
1245 +#define AR5312_FLASHCTL_ATR 0x80000000 /* Access == retry every */
1246 +#define AR5312_FLASHCTL_ATR4 0xc0000000 /* Access == retry every 4 */
1247 +
1248 +/*
1249 + * ARM SDRAM Controller -- just enough to determine memory size
1250 + */
1251 +#define AR5312_MEM_CFG1 0x0004
1252 +
1253 +#define AR5312_MEM_CFG1_AC0_M 0x00000700 /* bank 0: SDRAM addr check */
1254 +#define AR5312_MEM_CFG1_AC0_S 8
1255 +#define AR5312_MEM_CFG1_AC1_M 0x00007000 /* bank 1: SDRAM addr check */
1256 +#define AR5312_MEM_CFG1_AC1_S 12
1257 +
1258 +#endif /* __ASM_MACH_ATH25_AR5312_REGS_H */
1259 --- /dev/null
1260 +++ b/arch/mips/ath25/ar5312.c
1261 @@ -0,0 +1,393 @@
1262 +/*
1263 + * This file is subject to the terms and conditions of the GNU General Public
1264 + * License. See the file "COPYING" in the main directory of this archive
1265 + * for more details.
1266 + *
1267 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1268 + * Copyright (C) 2006 FON Technology, SL.
1269 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1270 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1271 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1272 + */
1273 +
1274 +/*
1275 + * Platform devices for Atheros AR5312 SoCs
1276 + */
1277 +
1278 +#include <linux/init.h>
1279 +#include <linux/kernel.h>
1280 +#include <linux/bitops.h>
1281 +#include <linux/irqdomain.h>
1282 +#include <linux/interrupt.h>
1283 +#include <linux/platform_device.h>
1284 +#include <linux/mtd/physmap.h>
1285 +#include <linux/reboot.h>
1286 +#include <asm/bootinfo.h>
1287 +#include <asm/reboot.h>
1288 +#include <asm/time.h>
1289 +
1290 +#include <ath25_platform.h>
1291 +
1292 +#include "devices.h"
1293 +#include "ar5312.h"
1294 +#include "ar5312_regs.h"
1295 +
1296 +static void __iomem *ar5312_rst_base;
1297 +static struct irq_domain *ar5312_misc_irq_domain;
1298 +
1299 +static inline u32 ar5312_rst_reg_read(u32 reg)
1300 +{
1301 + return __raw_readl(ar5312_rst_base + reg);
1302 +}
1303 +
1304 +static inline void ar5312_rst_reg_write(u32 reg, u32 val)
1305 +{
1306 + __raw_writel(val, ar5312_rst_base + reg);
1307 +}
1308 +
1309 +static inline void ar5312_rst_reg_mask(u32 reg, u32 mask, u32 val)
1310 +{
1311 + u32 ret = ar5312_rst_reg_read(reg);
1312 +
1313 + ret &= ~mask;
1314 + ret |= val;
1315 + ar5312_rst_reg_write(reg, ret);
1316 +}
1317 +
1318 +static irqreturn_t ar5312_ahb_err_handler(int cpl, void *dev_id)
1319 +{
1320 + u32 proc1 = ar5312_rst_reg_read(AR5312_PROC1);
1321 + u32 proc_addr = ar5312_rst_reg_read(AR5312_PROCADDR); /* clears error */
1322 + u32 dma1 = ar5312_rst_reg_read(AR5312_DMA1);
1323 + u32 dma_addr = ar5312_rst_reg_read(AR5312_DMAADDR); /* clears error */
1324 +
1325 + pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
1326 + proc_addr, proc1, dma_addr, dma1);
1327 +
1328 + machine_restart("AHB error"); /* Catastrophic failure */
1329 + return IRQ_HANDLED;
1330 +}
1331 +
1332 +static struct irqaction ar5312_ahb_err_interrupt = {
1333 + .handler = ar5312_ahb_err_handler,
1334 + .name = "ar5312-ahb-error",
1335 +};
1336 +
1337 +static void ar5312_misc_irq_handler(unsigned irq, struct irq_desc *desc)
1338 +{
1339 + u32 pending = ar5312_rst_reg_read(AR5312_ISR) &
1340 + ar5312_rst_reg_read(AR5312_IMR);
1341 + unsigned nr, misc_irq = 0;
1342 +
1343 + if (pending) {
1344 + struct irq_domain *domain = irq_get_handler_data(irq);
1345 +
1346 + nr = __ffs(pending);
1347 + misc_irq = irq_find_mapping(domain, nr);
1348 + }
1349 +
1350 + if (misc_irq) {
1351 + generic_handle_irq(misc_irq);
1352 + if (nr == AR5312_MISC_IRQ_TIMER)
1353 + ar5312_rst_reg_read(AR5312_TIMER);
1354 + } else {
1355 + spurious_interrupt();
1356 + }
1357 +}
1358 +
1359 +/* Enable the specified AR5312_MISC_IRQ interrupt */
1360 +static void ar5312_misc_irq_unmask(struct irq_data *d)
1361 +{
1362 + ar5312_rst_reg_mask(AR5312_IMR, 0, BIT(d->hwirq));
1363 +}
1364 +
1365 +/* Disable the specified AR5312_MISC_IRQ interrupt */
1366 +static void ar5312_misc_irq_mask(struct irq_data *d)
1367 +{
1368 + ar5312_rst_reg_mask(AR5312_IMR, BIT(d->hwirq), 0);
1369 + ar5312_rst_reg_read(AR5312_IMR); /* flush write buffer */
1370 +}
1371 +
1372 +static struct irq_chip ar5312_misc_irq_chip = {
1373 + .name = "ar5312-misc",
1374 + .irq_unmask = ar5312_misc_irq_unmask,
1375 + .irq_mask = ar5312_misc_irq_mask,
1376 +};
1377 +
1378 +static int ar5312_misc_irq_map(struct irq_domain *d, unsigned irq,
1379 + irq_hw_number_t hw)
1380 +{
1381 + irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip, handle_level_irq);
1382 + return 0;
1383 +}
1384 +
1385 +static struct irq_domain_ops ar5312_misc_irq_domain_ops = {
1386 + .map = ar5312_misc_irq_map,
1387 +};
1388 +
1389 +static void ar5312_irq_dispatch(void)
1390 +{
1391 + u32 pending = read_c0_status() & read_c0_cause();
1392 +
1393 + if (pending & CAUSEF_IP2)
1394 + do_IRQ(AR5312_IRQ_WLAN0);
1395 + else if (pending & CAUSEF_IP5)
1396 + do_IRQ(AR5312_IRQ_WLAN1);
1397 + else if (pending & CAUSEF_IP6)
1398 + do_IRQ(AR5312_IRQ_MISC);
1399 + else if (pending & CAUSEF_IP7)
1400 + do_IRQ(ATH25_IRQ_CPU_CLOCK);
1401 + else
1402 + spurious_interrupt();
1403 +}
1404 +
1405 +void __init ar5312_arch_init_irq(void)
1406 +{
1407 + struct irq_domain *domain;
1408 + unsigned irq;
1409 +
1410 + ath25_irq_dispatch = ar5312_irq_dispatch;
1411 +
1412 + domain = irq_domain_add_linear(NULL, AR5312_MISC_IRQ_COUNT,
1413 + &ar5312_misc_irq_domain_ops, NULL);
1414 + if (!domain)
1415 + panic("Failed to add IRQ domain");
1416 +
1417 + irq = irq_create_mapping(domain, AR5312_MISC_IRQ_AHB_PROC);
1418 + setup_irq(irq, &ar5312_ahb_err_interrupt);
1419 +
1420 + irq_set_chained_handler(AR5312_IRQ_MISC, ar5312_misc_irq_handler);
1421 + irq_set_handler_data(AR5312_IRQ_MISC, domain);
1422 +
1423 + ar5312_misc_irq_domain = domain;
1424 +}
1425 +
1426 +static struct physmap_flash_data ar5312_flash_data = {
1427 + .width = 2,
1428 +};
1429 +
1430 +static struct resource ar5312_flash_resource = {
1431 + .start = AR5312_FLASH_BASE,
1432 + .end = AR5312_FLASH_BASE + AR5312_FLASH_SIZE - 1,
1433 + .flags = IORESOURCE_MEM,
1434 +};
1435 +
1436 +static struct platform_device ar5312_physmap_flash = {
1437 + .name = "physmap-flash",
1438 + .id = 0,
1439 + .dev.platform_data = &ar5312_flash_data,
1440 + .resource = &ar5312_flash_resource,
1441 + .num_resources = 1,
1442 +};
1443 +
1444 +static void __init ar5312_flash_init(void)
1445 +{
1446 + void __iomem *flashctl_base;
1447 + u32 ctl;
1448 +
1449 + flashctl_base = ioremap_nocache(AR5312_FLASHCTL_BASE,
1450 + AR5312_FLASHCTL_SIZE);
1451 +
1452 + ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL0);
1453 + ctl &= AR5312_FLASHCTL_MW;
1454 +
1455 + /* fixup flash width */
1456 + switch (ctl) {
1457 + case AR5312_FLASHCTL_MW16:
1458 + ar5312_flash_data.width = 2;
1459 + break;
1460 + case AR5312_FLASHCTL_MW8:
1461 + default:
1462 + ar5312_flash_data.width = 1;
1463 + break;
1464 + }
1465 +
1466 + /*
1467 + * Configure flash bank 0.
1468 + * Assume 8M window size. Flash will be aliased if it's smaller
1469 + */
1470 + ctl |= AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC_8M | AR5312_FLASHCTL_RBLE;
1471 + ctl |= 0x01 << AR5312_FLASHCTL_IDCY_S;
1472 + ctl |= 0x07 << AR5312_FLASHCTL_WST1_S;
1473 + ctl |= 0x07 << AR5312_FLASHCTL_WST2_S;
1474 + __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL0);
1475 +
1476 + /* Disable other flash banks */
1477 + ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL1);
1478 + ctl &= ~(AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC);
1479 + __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL1);
1480 + ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL2);
1481 + ctl &= ~(AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC);
1482 + __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL2);
1483 +
1484 + iounmap(flashctl_base);
1485 +}
1486 +
1487 +void __init ar5312_init_devices(void)
1488 +{
1489 + struct ath25_boarddata *config;
1490 +
1491 + ar5312_flash_init();
1492 +
1493 + /* Locate board/radio config data */
1494 + ath25_find_config(AR5312_FLASH_BASE, AR5312_FLASH_SIZE);
1495 + config = ath25_board.config;
1496 +
1497 + /* AR2313 has CPU minor rev. 10 */
1498 + if ((current_cpu_data.processor_id & 0xff) == 0x0a)
1499 + ath25_soc = ATH25_SOC_AR2313;
1500 +
1501 + /* AR2312 shares the same Silicon ID as AR5312 */
1502 + else if (config->flags & BD_ISCASPER)
1503 + ath25_soc = ATH25_SOC_AR2312;
1504 +
1505 + /* Everything else is probably AR5312 or compatible */
1506 + else
1507 + ath25_soc = ATH25_SOC_AR5312;
1508 +
1509 + platform_device_register(&ar5312_physmap_flash);
1510 +
1511 + switch (ath25_soc) {
1512 + case ATH25_SOC_AR5312:
1513 + if (!ath25_board.radio)
1514 + return;
1515 +
1516 + if (!(config->flags & BD_WLAN0))
1517 + break;
1518 +
1519 + ath25_add_wmac(0, AR5312_WLAN0_BASE, AR5312_IRQ_WLAN0);
1520 + break;
1521 + case ATH25_SOC_AR2312:
1522 + case ATH25_SOC_AR2313:
1523 + if (!ath25_board.radio)
1524 + return;
1525 + break;
1526 + default:
1527 + break;
1528 + }
1529 +
1530 + if (config->flags & BD_WLAN1)
1531 + ath25_add_wmac(1, AR5312_WLAN1_BASE, AR5312_IRQ_WLAN1);
1532 +}
1533 +
1534 +static void ar5312_restart(char *command)
1535 +{
1536 + /* reset the system */
1537 + local_irq_disable();
1538 + while (1)
1539 + ar5312_rst_reg_write(AR5312_RESET, AR5312_RESET_SYSTEM);
1540 +}
1541 +
1542 +/*
1543 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
1544 + * to determine the predevisor value.
1545 + */
1546 +static unsigned clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
1547 +
1548 +static unsigned __init ar5312_cpu_frequency(void)
1549 +{
1550 + u32 scratch, devid, clock_ctl1;
1551 + u32 predivide_mask, multiplier_mask, doubler_mask;
1552 + unsigned predivide_shift, multiplier_shift;
1553 + unsigned predivide_select, predivisor, multiplier;
1554 +
1555 + /* Trust the bootrom's idea of cpu frequency. */
1556 + scratch = ar5312_rst_reg_read(AR5312_SCRATCH);
1557 + if (scratch)
1558 + return scratch;
1559 +
1560 + devid = ar5312_rst_reg_read(AR5312_REV);
1561 + devid = (devid & AR5312_REV_MAJ) >> AR5312_REV_MAJ_S;
1562 + if (devid == AR5312_REV_MAJ_AR2313) {
1563 + predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
1564 + predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
1565 + multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
1566 + multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
1567 + doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
1568 + } else { /* AR5312 and AR2312 */
1569 + predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
1570 + predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
1571 + multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
1572 + multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
1573 + doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
1574 + }
1575 +
1576 + /*
1577 + * Clocking is derived from a fixed 40MHz input clock.
1578 + *
1579 + * cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
1580 + * sys_freq = cpu_freq / 4 (used for APB clock, serial,
1581 + * flash, Timer, Watchdog Timer)
1582 + *
1583 + * cnt_freq = cpu_freq / 2 (use for CPU count/compare)
1584 + *
1585 + * So, for example, with a PLL multiplier of 5, we have
1586 + *
1587 + * cpu_freq = 200MHz
1588 + * sys_freq = 50MHz
1589 + * cnt_freq = 100MHz
1590 + *
1591 + * We compute the CPU frequency, based on PLL settings.
1592 + */
1593 +
1594 + clock_ctl1 = ar5312_rst_reg_read(AR5312_CLOCKCTL1);
1595 + predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
1596 + predivisor = clockctl1_predivide_table[predivide_select];
1597 + multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
1598 +
1599 + if (clock_ctl1 & doubler_mask)
1600 + multiplier <<= 1;
1601 +
1602 + return (40000000 / predivisor) * multiplier;
1603 +}
1604 +
1605 +static inline unsigned ar5312_sys_frequency(void)
1606 +{
1607 + return ar5312_cpu_frequency() / 4;
1608 +}
1609 +
1610 +void __init ar5312_plat_time_init(void)
1611 +{
1612 + mips_hpt_frequency = ar5312_cpu_frequency() / 2;
1613 +}
1614 +
1615 +void __init ar5312_plat_mem_setup(void)
1616 +{
1617 + void __iomem *sdram_base;
1618 + u32 memsize, memcfg, bank0_ac, bank1_ac;
1619 + u32 devid;
1620 +
1621 + /* Detect memory size */
1622 + sdram_base = ioremap_nocache(AR5312_SDRAMCTL_BASE,
1623 + AR5312_SDRAMCTL_SIZE);
1624 + memcfg = __raw_readl(sdram_base + AR5312_MEM_CFG1);
1625 + bank0_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC0);
1626 + bank1_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC1);
1627 + memsize = (bank0_ac ? (1 << (bank0_ac + 1)) : 0) +
1628 + (bank1_ac ? (1 << (bank1_ac + 1)) : 0);
1629 + memsize <<= 20;
1630 + add_memory_region(0, memsize, BOOT_MEM_RAM);
1631 + iounmap(sdram_base);
1632 +
1633 + ar5312_rst_base = ioremap_nocache(AR5312_RST_BASE, AR5312_RST_SIZE);
1634 +
1635 + devid = ar5312_rst_reg_read(AR5312_REV);
1636 + devid >>= AR5312_REV_WMAC_MIN_S;
1637 + devid &= AR5312_REV_CHIP;
1638 + ath25_board.devid = (u16)devid;
1639 +
1640 + /* Clear any lingering AHB errors */
1641 + ar5312_rst_reg_read(AR5312_PROCADDR);
1642 + ar5312_rst_reg_read(AR5312_DMAADDR);
1643 + ar5312_rst_reg_write(AR5312_WDT_CTRL, AR5312_WDT_CTRL_IGNORE);
1644 +
1645 + _machine_restart = ar5312_restart;
1646 +}
1647 +
1648 +void __init ar5312_arch_init(void)
1649 +{
1650 + unsigned irq = irq_create_mapping(ar5312_misc_irq_domain,
1651 + AR5312_MISC_IRQ_UART0);
1652 +
1653 + ath25_serial_setup(AR5312_UART0_BASE, irq, ar5312_sys_frequency());
1654 +}
1655 --- /dev/null
1656 +++ b/arch/mips/ath25/ar2315.c
1657 @@ -0,0 +1,308 @@
1658 +/*
1659 + * This file is subject to the terms and conditions of the GNU General Public
1660 + * License. See the file "COPYING" in the main directory of this archive
1661 + * for more details.
1662 + *
1663 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1664 + * Copyright (C) 2006 FON Technology, SL.
1665 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1666 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1667 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1668 + */
1669 +
1670 +/*
1671 + * Platform devices for Atheros AR2315 SoCs
1672 + */
1673 +
1674 +#include <linux/init.h>
1675 +#include <linux/kernel.h>
1676 +#include <linux/bitops.h>
1677 +#include <linux/irqdomain.h>
1678 +#include <linux/interrupt.h>
1679 +#include <linux/platform_device.h>
1680 +#include <linux/reboot.h>
1681 +#include <asm/bootinfo.h>
1682 +#include <asm/reboot.h>
1683 +#include <asm/time.h>
1684 +
1685 +#include <ath25_platform.h>
1686 +
1687 +#include "devices.h"
1688 +#include "ar2315.h"
1689 +#include "ar2315_regs.h"
1690 +
1691 +static void __iomem *ar2315_rst_base;
1692 +static struct irq_domain *ar2315_misc_irq_domain;
1693 +
1694 +static inline u32 ar2315_rst_reg_read(u32 reg)
1695 +{
1696 + return __raw_readl(ar2315_rst_base + reg);
1697 +}
1698 +
1699 +static inline void ar2315_rst_reg_write(u32 reg, u32 val)
1700 +{
1701 + __raw_writel(val, ar2315_rst_base + reg);
1702 +}
1703 +
1704 +static inline void ar2315_rst_reg_mask(u32 reg, u32 mask, u32 val)
1705 +{
1706 + u32 ret = ar2315_rst_reg_read(reg);
1707 +
1708 + ret &= ~mask;
1709 + ret |= val;
1710 + ar2315_rst_reg_write(reg, ret);
1711 +}
1712 +
1713 +static irqreturn_t ar2315_ahb_err_handler(int cpl, void *dev_id)
1714 +{
1715 + ar2315_rst_reg_write(AR2315_AHB_ERR0, AR2315_AHB_ERROR_DET);
1716 + ar2315_rst_reg_read(AR2315_AHB_ERR1);
1717 +
1718 + pr_emerg("AHB fatal error\n");
1719 + machine_restart("AHB error"); /* Catastrophic failure */
1720 +
1721 + return IRQ_HANDLED;
1722 +}
1723 +
1724 +static struct irqaction ar2315_ahb_err_interrupt = {
1725 + .handler = ar2315_ahb_err_handler,
1726 + .name = "ar2315-ahb-error",
1727 +};
1728 +
1729 +static void ar2315_misc_irq_handler(unsigned irq, struct irq_desc *desc)
1730 +{
1731 + u32 pending = ar2315_rst_reg_read(AR2315_ISR) &
1732 + ar2315_rst_reg_read(AR2315_IMR);
1733 + unsigned nr, misc_irq = 0;
1734 +
1735 + if (pending) {
1736 + struct irq_domain *domain = irq_get_handler_data(irq);
1737 +
1738 + nr = __ffs(pending);
1739 + misc_irq = irq_find_mapping(domain, nr);
1740 + }
1741 +
1742 + if (misc_irq) {
1743 + if (nr == AR2315_MISC_IRQ_GPIO)
1744 + ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_GPIO);
1745 + else if (nr == AR2315_MISC_IRQ_WATCHDOG)
1746 + ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_WD);
1747 + generic_handle_irq(misc_irq);
1748 + } else {
1749 + spurious_interrupt();
1750 + }
1751 +}
1752 +
1753 +static void ar2315_misc_irq_unmask(struct irq_data *d)
1754 +{
1755 + ar2315_rst_reg_mask(AR2315_IMR, 0, BIT(d->hwirq));
1756 +}
1757 +
1758 +static void ar2315_misc_irq_mask(struct irq_data *d)
1759 +{
1760 + ar2315_rst_reg_mask(AR2315_IMR, BIT(d->hwirq), 0);
1761 +}
1762 +
1763 +static struct irq_chip ar2315_misc_irq_chip = {
1764 + .name = "ar2315-misc",
1765 + .irq_unmask = ar2315_misc_irq_unmask,
1766 + .irq_mask = ar2315_misc_irq_mask,
1767 +};
1768 +
1769 +static int ar2315_misc_irq_map(struct irq_domain *d, unsigned irq,
1770 + irq_hw_number_t hw)
1771 +{
1772 + irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip, handle_level_irq);
1773 + return 0;
1774 +}
1775 +
1776 +static struct irq_domain_ops ar2315_misc_irq_domain_ops = {
1777 + .map = ar2315_misc_irq_map,
1778 +};
1779 +
1780 +/*
1781 + * Called when an interrupt is received, this function
1782 + * determines exactly which interrupt it was, and it
1783 + * invokes the appropriate handler.
1784 + *
1785 + * Implicitly, we also define interrupt priority by
1786 + * choosing which to dispatch first.
1787 + */
1788 +static void ar2315_irq_dispatch(void)
1789 +{
1790 + u32 pending = read_c0_status() & read_c0_cause();
1791 +
1792 + if (pending & CAUSEF_IP3)
1793 + do_IRQ(AR2315_IRQ_WLAN0);
1794 + else if (pending & CAUSEF_IP2)
1795 + do_IRQ(AR2315_IRQ_MISC);
1796 + else if (pending & CAUSEF_IP7)
1797 + do_IRQ(ATH25_IRQ_CPU_CLOCK);
1798 + else
1799 + spurious_interrupt();
1800 +}
1801 +
1802 +void __init ar2315_arch_init_irq(void)
1803 +{
1804 + struct irq_domain *domain;
1805 + unsigned irq;
1806 +
1807 + ath25_irq_dispatch = ar2315_irq_dispatch;
1808 +
1809 + domain = irq_domain_add_linear(NULL, AR2315_MISC_IRQ_COUNT,
1810 + &ar2315_misc_irq_domain_ops, NULL);
1811 + if (!domain)
1812 + panic("Failed to add IRQ domain");
1813 +
1814 + irq = irq_create_mapping(domain, AR2315_MISC_IRQ_AHB);
1815 + setup_irq(irq, &ar2315_ahb_err_interrupt);
1816 +
1817 + irq_set_chained_handler(AR2315_IRQ_MISC, ar2315_misc_irq_handler);
1818 + irq_set_handler_data(AR2315_IRQ_MISC, domain);
1819 +
1820 + ar2315_misc_irq_domain = domain;
1821 +}
1822 +
1823 +void __init ar2315_init_devices(void)
1824 +{
1825 + /* Find board configuration */
1826 + ath25_find_config(AR2315_SPI_READ_BASE, AR2315_SPI_READ_SIZE);
1827 +
1828 + ath25_add_wmac(0, AR2315_WLAN0_BASE, AR2315_IRQ_WLAN0);
1829 +}
1830 +
1831 +static void ar2315_restart(char *command)
1832 +{
1833 + void (*mips_reset_vec)(void) = (void *)0xbfc00000;
1834 +
1835 + local_irq_disable();
1836 +
1837 + /* try reset the system via reset control */
1838 + ar2315_rst_reg_write(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
1839 +
1840 + /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
1841 + * a workaround. Give it some time to attempt a gpio based hardware
1842 + * reset (atheros reference design workaround) */
1843 +
1844 + /* TODO: implement the GPIO reset workaround */
1845 +
1846 + /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
1847 + * workaround. Attempt to jump to the mips reset location -
1848 + * the boot loader itself might be able to recover the system */
1849 + mips_reset_vec();
1850 +}
1851 +
1852 +/*
1853 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
1854 + * to determine the predevisor value.
1855 + */
1856 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
1857 +static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
1858 +
1859 +static unsigned __init ar2315_sys_clk(u32 clock_ctl)
1860 +{
1861 + unsigned int pllc_ctrl, cpu_div;
1862 + unsigned int pllc_out, refdiv, fdiv, divby2;
1863 + unsigned int clk_div;
1864 +
1865 + pllc_ctrl = ar2315_rst_reg_read(AR2315_PLLC_CTL);
1866 + refdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_REF_DIV);
1867 + refdiv = clockctl1_predivide_table[refdiv];
1868 + fdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_FDBACK_DIV);
1869 + divby2 = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_ADD_FDBACK_DIV) + 1;
1870 + pllc_out = (40000000 / refdiv) * (2 * divby2) * fdiv;
1871 +
1872 + /* clkm input selected */
1873 + switch (clock_ctl & AR2315_CPUCLK_CLK_SEL_M) {
1874 + case 0:
1875 + case 1:
1876 + clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKM_DIV);
1877 + clk_div = pllc_divide_table[clk_div];
1878 + break;
1879 + case 2:
1880 + clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKC_DIV);
1881 + clk_div = pllc_divide_table[clk_div];
1882 + break;
1883 + default:
1884 + pllc_out = 40000000;
1885 + clk_div = 1;
1886 + break;
1887 + }
1888 +
1889 + cpu_div = ATH25_REG_MS(clock_ctl, AR2315_CPUCLK_CLK_DIV);
1890 + cpu_div = cpu_div * 2 ?: 1;
1891 +
1892 + return pllc_out / (clk_div * cpu_div);
1893 +}
1894 +
1895 +static inline unsigned ar2315_cpu_frequency(void)
1896 +{
1897 + return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_CPUCLK));
1898 +}
1899 +
1900 +static inline unsigned ar2315_apb_frequency(void)
1901 +{
1902 + return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_AMBACLK));
1903 +}
1904 +
1905 +void __init ar2315_plat_time_init(void)
1906 +{
1907 + mips_hpt_frequency = ar2315_cpu_frequency() / 2;
1908 +}
1909 +
1910 +void __init ar2315_plat_mem_setup(void)
1911 +{
1912 + void __iomem *sdram_base;
1913 + u32 memsize, memcfg;
1914 + u32 devid;
1915 + u32 config;
1916 +
1917 + /* Detect memory size */
1918 + sdram_base = ioremap_nocache(AR2315_SDRAMCTL_BASE,
1919 + AR2315_SDRAMCTL_SIZE);
1920 + memcfg = __raw_readl(sdram_base + AR2315_MEM_CFG);
1921 + memsize = 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_DATA_WIDTH);
1922 + memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_COL_WIDTH);
1923 + memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_ROW_WIDTH);
1924 + memsize <<= 3;
1925 + add_memory_region(0, memsize, BOOT_MEM_RAM);
1926 + iounmap(sdram_base);
1927 +
1928 + ar2315_rst_base = ioremap_nocache(AR2315_RST_BASE, AR2315_RST_SIZE);
1929 +
1930 + /* Detect the hardware based on the device ID */
1931 + devid = ar2315_rst_reg_read(AR2315_SREV) & AR2315_REV_CHIP;
1932 + switch (devid) {
1933 + case 0x91: /* Need to check */
1934 + ath25_soc = ATH25_SOC_AR2318;
1935 + break;
1936 + case 0x90:
1937 + ath25_soc = ATH25_SOC_AR2317;
1938 + break;
1939 + case 0x87:
1940 + ath25_soc = ATH25_SOC_AR2316;
1941 + break;
1942 + case 0x86:
1943 + default:
1944 + ath25_soc = ATH25_SOC_AR2315;
1945 + break;
1946 + }
1947 + ath25_board.devid = devid;
1948 +
1949 + /* Clear any lingering AHB errors */
1950 + config = read_c0_config();
1951 + write_c0_config(config & ~0x3);
1952 + ar2315_rst_reg_write(AR2315_AHB_ERR0, AR2315_AHB_ERROR_DET);
1953 + ar2315_rst_reg_read(AR2315_AHB_ERR1);
1954 + ar2315_rst_reg_write(AR2315_WDT_CTRL, AR2315_WDT_CTRL_IGNORE);
1955 +
1956 + _machine_restart = ar2315_restart;
1957 +}
1958 +
1959 +void __init ar2315_arch_init(void)
1960 +{
1961 + unsigned irq = irq_create_mapping(ar2315_misc_irq_domain,
1962 + AR2315_MISC_IRQ_UART0);
1963 +
1964 + ath25_serial_setup(AR2315_UART0_BASE, irq, ar2315_apb_frequency());
1965 +}
1966 --- /dev/null
1967 +++ b/arch/mips/ath25/ar2315.h
1968 @@ -0,0 +1,22 @@
1969 +#ifndef __AR2315_H
1970 +#define __AR2315_H
1971 +
1972 +#ifdef CONFIG_SOC_AR2315
1973 +
1974 +void ar2315_arch_init_irq(void);
1975 +void ar2315_init_devices(void);
1976 +void ar2315_plat_time_init(void);
1977 +void ar2315_plat_mem_setup(void);
1978 +void ar2315_arch_init(void);
1979 +
1980 +#else
1981 +
1982 +static inline void ar2315_arch_init_irq(void) {}
1983 +static inline void ar2315_init_devices(void) {}
1984 +static inline void ar2315_plat_time_init(void) {}
1985 +static inline void ar2315_plat_mem_setup(void) {}
1986 +static inline void ar2315_arch_init(void) {}
1987 +
1988 +#endif
1989 +
1990 +#endif /* __AR2315_H */
1991 --- /dev/null
1992 +++ b/arch/mips/ath25/ar5312.h
1993 @@ -0,0 +1,22 @@
1994 +#ifndef __AR5312_H
1995 +#define __AR5312_H
1996 +
1997 +#ifdef CONFIG_SOC_AR5312
1998 +
1999 +void ar5312_arch_init_irq(void);
2000 +void ar5312_init_devices(void);
2001 +void ar5312_plat_time_init(void);
2002 +void ar5312_plat_mem_setup(void);
2003 +void ar5312_arch_init(void);
2004 +
2005 +#else
2006 +
2007 +static inline void ar5312_arch_init_irq(void) {}
2008 +static inline void ar5312_init_devices(void) {}
2009 +static inline void ar5312_plat_time_init(void) {}
2010 +static inline void ar5312_plat_mem_setup(void) {}
2011 +static inline void ar5312_arch_init(void) {}
2012 +
2013 +#endif
2014 +
2015 +#endif /* __AR5312_H */
2016 --- /dev/null
2017 +++ b/arch/mips/ath25/devices.h
2018 @@ -0,0 +1,43 @@
2019 +#ifndef __ATH25_DEVICES_H
2020 +#define __ATH25_DEVICES_H
2021 +
2022 +#include <linux/cpu.h>
2023 +
2024 +#define ATH25_REG_MS(_val, _field) (((_val) & _field##_M) >> _field##_S)
2025 +
2026 +#define ATH25_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE + 7) /* C0_CAUSE: 0x8000 */
2027 +
2028 +enum ath25_soc_type {
2029 + /* handled by ar5312.c */
2030 + ATH25_SOC_AR2312,
2031 + ATH25_SOC_AR2313,
2032 + ATH25_SOC_AR5312,
2033 +
2034 + /* handled by ar2315.c */
2035 + ATH25_SOC_AR2315,
2036 + ATH25_SOC_AR2316,
2037 + ATH25_SOC_AR2317,
2038 + ATH25_SOC_AR2318,
2039 +
2040 + ATH25_SOC_UNKNOWN
2041 +};
2042 +
2043 +extern enum ath25_soc_type ath25_soc;
2044 +extern struct ar231x_board_config ath25_board;
2045 +extern void (*ath25_irq_dispatch)(void);
2046 +
2047 +int ath25_find_config(phys_addr_t offset, unsigned long size);
2048 +void ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk);
2049 +int ath25_add_wmac(int nr, u32 base, int irq);
2050 +
2051 +static inline bool is_ar2315(void)
2052 +{
2053 + return (current_cpu_data.cputype == CPU_4KEC);
2054 +}
2055 +
2056 +static inline bool is_ar5312(void)
2057 +{
2058 + return !is_ar2315();
2059 +}
2060 +
2061 +#endif
2062 --- /dev/null
2063 +++ b/arch/mips/ath25/devices.c
2064 @@ -0,0 +1,125 @@
2065 +#include <linux/kernel.h>
2066 +#include <linux/init.h>
2067 +#include <linux/serial_8250.h>
2068 +#include <linux/platform_device.h>
2069 +#include <asm/bootinfo.h>
2070 +
2071 +#include <ath25_platform.h>
2072 +#include "devices.h"
2073 +#include "ar5312.h"
2074 +#include "ar2315.h"
2075 +
2076 +struct ar231x_board_config ath25_board;
2077 +enum ath25_soc_type ath25_soc = ATH25_SOC_UNKNOWN;
2078 +
2079 +static struct resource ath25_wmac0_res[] = {
2080 + {
2081 + .name = "wmac0_membase",
2082 + .flags = IORESOURCE_MEM,
2083 + },
2084 + {
2085 + .name = "wmac0_irq",
2086 + .flags = IORESOURCE_IRQ,
2087 + }
2088 +};
2089 +
2090 +static struct resource ath25_wmac1_res[] = {
2091 + {
2092 + .name = "wmac1_membase",
2093 + .flags = IORESOURCE_MEM,
2094 + },
2095 + {
2096 + .name = "wmac1_irq",
2097 + .flags = IORESOURCE_IRQ,
2098 + }
2099 +};
2100 +
2101 +static struct platform_device ath25_wmac[] = {
2102 + {
2103 + .id = 0,
2104 + .name = "ar231x-wmac",
2105 + .resource = ath25_wmac0_res,
2106 + .num_resources = ARRAY_SIZE(ath25_wmac0_res),
2107 + .dev.platform_data = &ath25_board,
2108 + },
2109 + {
2110 + .id = 1,
2111 + .name = "ar231x-wmac",
2112 + .resource = ath25_wmac1_res,
2113 + .num_resources = ARRAY_SIZE(ath25_wmac1_res),
2114 + .dev.platform_data = &ath25_board,
2115 + },
2116 +};
2117 +
2118 +static const char * const soc_type_strings[] = {
2119 + [ATH25_SOC_AR5312] = "Atheros AR5312",
2120 + [ATH25_SOC_AR2312] = "Atheros AR2312",
2121 + [ATH25_SOC_AR2313] = "Atheros AR2313",
2122 + [ATH25_SOC_AR2315] = "Atheros AR2315",
2123 + [ATH25_SOC_AR2316] = "Atheros AR2316",
2124 + [ATH25_SOC_AR2317] = "Atheros AR2317",
2125 + [ATH25_SOC_AR2318] = "Atheros AR2318",
2126 + [ATH25_SOC_UNKNOWN] = "Atheros (unknown)",
2127 +};
2128 +
2129 +const char *get_system_type(void)
2130 +{
2131 + if ((ath25_soc >= ARRAY_SIZE(soc_type_strings)) ||
2132 + !soc_type_strings[ath25_soc])
2133 + return soc_type_strings[ATH25_SOC_UNKNOWN];
2134 + return soc_type_strings[ath25_soc];
2135 +}
2136 +
2137 +void __init ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk)
2138 +{
2139 + struct uart_port s;
2140 +
2141 + memset(&s, 0, sizeof(s));
2142 +
2143 + s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP;
2144 + s.iotype = UPIO_MEM32;
2145 + s.irq = irq;
2146 + s.regshift = 2;
2147 + s.mapbase = mapbase;
2148 + s.uartclk = uartclk;
2149 +
2150 + early_serial_setup(&s);
2151 +}
2152 +
2153 +int __init ath25_add_wmac(int nr, u32 base, int irq)
2154 +{
2155 + struct resource *res;
2156 +
2157 + ath25_wmac[nr].dev.platform_data = &ath25_board;
2158 + res = &ath25_wmac[nr].resource[0];
2159 + res->start = base;
2160 + res->end = base + 0x10000 - 1;
2161 + res++;
2162 + res->start = irq;
2163 + res->end = irq;
2164 + return platform_device_register(&ath25_wmac[nr]);
2165 +}
2166 +
2167 +static int __init ath25_register_devices(void)
2168 +{
2169 + if (is_ar5312())
2170 + ar5312_init_devices();
2171 + else
2172 + ar2315_init_devices();
2173 +
2174 + return 0;
2175 +}
2176 +
2177 +device_initcall(ath25_register_devices);
2178 +
2179 +static int __init ath25_arch_init(void)
2180 +{
2181 + if (is_ar5312())
2182 + ar5312_arch_init();
2183 + else
2184 + ar2315_arch_init();
2185 +
2186 + return 0;
2187 +}
2188 +
2189 +arch_initcall(ath25_arch_init);
OpenWrt Source Repository