projects / openwrt / openwrt.git / blob
? search:


08b74636dd836c1504c243804a4bbb444b07707c
[openwrt/openwrt.git] / target / linux / ath25 / patches-3.18 / 030-ar2315_pci.patch
1 --- a/arch/mips/pci/Makefile
2 +++ b/arch/mips/pci/Makefile
3 @@ -19,6 +19,7 @@ obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o
4 obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \
5 ops-bcm63xx.o
6 obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o
7 +obj-$(CONFIG_PCI_AR2315) += pci-ar2315.o
8 obj-$(CONFIG_SOC_AR71XX) += pci-ar71xx.o
9 obj-$(CONFIG_PCI_AR724X) += pci-ar724x.o
10 obj-$(CONFIG_MIPS_PCI_VIRTIO) += pci-virtio-guest.o
11 --- /dev/null
12 +++ b/arch/mips/pci/pci-ar2315.c
13 @@ -0,0 +1,511 @@
14 +/*
15 + * This program is free software; you can redistribute it and/or
16 + * modify it under the terms of the GNU General Public License
17 + * as published by the Free Software Foundation; either version 2
18 + * of the License, or (at your option) any later version.
19 + *
20 + * This program is distributed in the hope that it will be useful,
21 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 + * GNU General Public License for more details.
24 + *
25 + * You should have received a copy of the GNU General Public License
26 + * along with this program; if not, see <http://www.gnu.org/licenses/>.
27 + */
28 +
29 +/**
30 + * Both AR2315 and AR2316 chips have PCI interface unit, which supports DMA
31 + * and interrupt. PCI interface supports MMIO access method, but does not
32 + * seem to support I/O ports.
33 + *
34 + * Read/write operation in the region 0x80000000-0xBFFFFFFF causes
35 + * a memory read/write command on the PCI bus. 30 LSBs of address on
36 + * the bus are taken from memory read/write request and 2 MSBs are
37 + * determined by PCI unit configuration.
38 + *
39 + * To work with the configuration space instead of memory is necessary set
40 + * the CFG_SEL bit in the PCI_MISC_CONFIG register.
41 + *
42 + * Devices on the bus can perform DMA requests via chip BAR1. PCI host
43 + * controller BARs are programmend as if an external device is programmed.
44 + * Which means that during configuration, IDSEL pin of the chip should be
45 + * asserted.
46 + *
47 + * We know (and support) only one board that uses the PCI interface -
48 + * Fonera 2.0g (FON2202). It has a USB EHCI controller connected to the
49 + * AR2315 PCI bus. IDSEL pin of USB controller is connected to AD[13] line
50 + * and IDSEL pin of AR2315 is connected to AD[16] line.
51 + */
52 +
53 +#include <linux/types.h>
54 +#include <linux/pci.h>
55 +#include <linux/platform_device.h>
56 +#include <linux/kernel.h>
57 +#include <linux/init.h>
58 +#include <linux/mm.h>
59 +#include <linux/delay.h>
60 +#include <linux/bitops.h>
61 +#include <linux/irq.h>
62 +#include <linux/irqdomain.h>
63 +#include <linux/io.h>
64 +#include <asm/paccess.h>
65 +
66 +/*
67 + * PCI Bus Interface Registers
68 + */
69 +#define AR2315_PCI_1MS_REG 0x0008
70 +
71 +#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
72 +
73 +#define AR2315_PCI_MISC_CONFIG 0x000c
74 +
75 +#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
76 +#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* Mem or Config cycles */
77 +#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
78 +#define AR2315_PCIMISC_RST_MODE 0x00000030
79 +#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
80 +#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
81 +#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
82 +#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
83 +#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
84 +#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
85 +#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
86 +#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache
87 + * disable */
88 +
89 +#define AR2315_PCI_OUT_TSTAMP 0x0010
90 +
91 +#define AR2315_PCI_UNCACHE_CFG 0x0014
92 +
93 +#define AR2315_PCI_IN_EN 0x0100
94 +
95 +#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
96 +#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
97 +#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
98 +#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
99 +
100 +#define AR2315_PCI_IN_DIS 0x0104
101 +
102 +#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
103 +#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
104 +#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
105 +#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
106 +
107 +#define AR2315_PCI_IN_PTR 0x0200
108 +
109 +#define AR2315_PCI_OUT_EN 0x0400
110 +
111 +#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
112 +
113 +#define AR2315_PCI_OUT_DIS 0x0404
114 +
115 +#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
116 +
117 +#define AR2315_PCI_OUT_PTR 0x0408
118 +
119 +/* PCI interrupt status (write one to clear) */
120 +#define AR2315_PCI_ISR 0x0500
121 +
122 +#define AR2315_PCI_INT_TX 0x00000001 /* Desc In Completed */
123 +#define AR2315_PCI_INT_TXOK 0x00000002 /* Desc In OK */
124 +#define AR2315_PCI_INT_TXERR 0x00000004 /* Desc In ERR */
125 +#define AR2315_PCI_INT_TXEOL 0x00000008 /* Desc In End-of-List */
126 +#define AR2315_PCI_INT_RX 0x00000010 /* Desc Out Completed */
127 +#define AR2315_PCI_INT_RXOK 0x00000020 /* Desc Out OK */
128 +#define AR2315_PCI_INT_RXERR 0x00000040 /* Desc Out ERR */
129 +#define AR2315_PCI_INT_RXEOL 0x00000080 /* Desc Out EOL */
130 +#define AR2315_PCI_INT_TXOOD 0x00000200 /* Desc In Out-of-Desc */
131 +#define AR2315_PCI_INT_DESCMASK 0x0000FFFF /* Desc Mask */
132 +#define AR2315_PCI_INT_EXT 0x02000000 /* Extern PCI INTA */
133 +#define AR2315_PCI_INT_ABORT 0x04000000 /* PCI bus abort event */
134 +
135 +/* PCI interrupt mask */
136 +#define AR2315_PCI_IMR 0x0504
137 +
138 +/* Global PCI interrupt enable */
139 +#define AR2315_PCI_IER 0x0508
140 +
141 +#define AR2315_PCI_IER_DISABLE 0x00 /* disable pci interrupts */
142 +#define AR2315_PCI_IER_ENABLE 0x01 /* enable pci interrupts */
143 +
144 +#define AR2315_PCI_HOST_IN_EN 0x0800
145 +#define AR2315_PCI_HOST_IN_DIS 0x0804
146 +#define AR2315_PCI_HOST_IN_PTR 0x0810
147 +#define AR2315_PCI_HOST_OUT_EN 0x0900
148 +#define AR2315_PCI_HOST_OUT_DIS 0x0904
149 +#define AR2315_PCI_HOST_OUT_PTR 0x0908
150 +
151 +/*
152 + * PCI interrupts, which share IP5
153 + * Keep ordered according to AR2315_PCI_INT_XXX bits
154 + */
155 +#define AR2315_PCI_IRQ_EXT 25
156 +#define AR2315_PCI_IRQ_ABORT 26
157 +#define AR2315_PCI_IRQ_COUNT 27
158 +
159 +/* Arbitrary size of memory region to access the configuration space */
160 +#define AR2315_PCI_CFG_SIZE 0x00100000
161 +
162 +#define AR2315_PCI_HOST_SLOT 3
163 +#define AR2315_PCI_HOST_DEVID ((0xff18 << 16) | PCI_VENDOR_ID_ATHEROS)
164 +
165 +/* ??? access BAR */
166 +#define AR2315_PCI_HOST_MBAR0 0x10000000
167 +/* RAM access BAR */
168 +#define AR2315_PCI_HOST_MBAR1 AR2315_PCI_HOST_SDRAM_BASEADDR
169 +/* ??? access BAR */
170 +#define AR2315_PCI_HOST_MBAR2 0x30000000
171 +
172 +struct ar2315_pci_ctrl {
173 + void __iomem *cfg_mem;
174 + void __iomem *mmr_mem;
175 + unsigned irq;
176 + unsigned irq_ext;
177 + struct irq_domain *domain;
178 + struct pci_controller pci_ctrl;
179 + struct resource mem_res;
180 + struct resource io_res;
181 +};
182 +
183 +static inline struct ar2315_pci_ctrl *ar2315_pci_bus_to_apc(struct pci_bus *bus)
184 +{
185 + struct pci_controller *hose = bus->sysdata;
186 +
187 + return container_of(hose, struct ar2315_pci_ctrl, pci_ctrl);
188 +}
189 +
190 +static inline u32 ar2315_pci_reg_read(struct ar2315_pci_ctrl *apc, u32 reg)
191 +{
192 + return __raw_readl(apc->mmr_mem + reg);
193 +}
194 +
195 +static inline void ar2315_pci_reg_write(struct ar2315_pci_ctrl *apc, u32 reg,
196 + u32 val)
197 +{
198 + __raw_writel(val, apc->mmr_mem + reg);
199 +}
200 +
201 +static inline void ar2315_pci_reg_mask(struct ar2315_pci_ctrl *apc, u32 reg,
202 + u32 mask, u32 val)
203 +{
204 + u32 ret = ar2315_pci_reg_read(apc, reg);
205 +
206 + ret &= ~mask;
207 + ret |= val;
208 + ar2315_pci_reg_write(apc, reg, ret);
209 +}
210 +
211 +static int ar2315_pci_cfg_access(struct ar2315_pci_ctrl *apc, unsigned devfn,
212 + int where, int size, u32 *ptr, bool write)
213 +{
214 + int func = PCI_FUNC(devfn);
215 + int dev = PCI_SLOT(devfn);
216 + u32 addr = (1 << (13 + dev)) | (func << 8) | (where & ~3);
217 + u32 mask = 0xffffffff >> 8 * (4 - size);
218 + u32 sh = (where & 3) * 8;
219 + u32 value, isr;
220 +
221 + /* Prevent access past the remapped area */
222 + if (addr >= AR2315_PCI_CFG_SIZE || dev > 18)
223 + return PCIBIOS_DEVICE_NOT_FOUND;
224 +
225 + /* Clear pending errors */
226 + ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
227 + /* Select Configuration access */
228 + ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG, 0,
229 + AR2315_PCIMISC_CFG_SEL);
230 +
231 + mb(); /* PCI must see space change before we begin */
232 +
233 + value = __raw_readl(apc->cfg_mem + addr);
234 +
235 + isr = ar2315_pci_reg_read(apc, AR2315_PCI_ISR);
236 +
237 + if (isr & AR2315_PCI_INT_ABORT)
238 + goto exit_err;
239 +
240 + if (write) {
241 + value = (value & ~(mask << sh)) | *ptr << sh;
242 + __raw_writel(value, apc->cfg_mem + addr);
243 + isr = ar2315_pci_reg_read(apc, AR2315_PCI_ISR);
244 + if (isr & AR2315_PCI_INT_ABORT)
245 + goto exit_err;
246 + } else {
247 + *ptr = (value >> sh) & mask;
248 + }
249 +
250 + goto exit;
251 +
252 +exit_err:
253 + ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
254 + if (!write)
255 + *ptr = 0xffffffff;
256 +
257 +exit:
258 + /* Select Memory access */
259 + ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL,
260 + 0);
261 +
262 + return isr & AR2315_PCI_INT_ABORT ? PCIBIOS_DEVICE_NOT_FOUND :
263 + PCIBIOS_SUCCESSFUL;
264 +}
265 +
266 +static inline int ar2315_pci_local_cfg_rd(struct ar2315_pci_ctrl *apc,
267 + unsigned devfn, int where, u32 *val)
268 +{
269 + return ar2315_pci_cfg_access(apc, devfn, where, sizeof(u32), val,
270 + false);
271 +}
272 +
273 +static inline int ar2315_pci_local_cfg_wr(struct ar2315_pci_ctrl *apc,
274 + unsigned devfn, int where, u32 val)
275 +{
276 + return ar2315_pci_cfg_access(apc, devfn, where, sizeof(u32), &val,
277 + true);
278 +}
279 +
280 +static int ar2315_pci_cfg_read(struct pci_bus *bus, unsigned devfn, int where,
281 + int size, u32 *value)
282 +{
283 + struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(bus);
284 +
285 + if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
286 + return PCIBIOS_DEVICE_NOT_FOUND;
287 +
288 + return ar2315_pci_cfg_access(apc, devfn, where, size, value, false);
289 +}
290 +
291 +static int ar2315_pci_cfg_write(struct pci_bus *bus, unsigned devfn, int where,
292 + int size, u32 value)
293 +{
294 + struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(bus);
295 +
296 + if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
297 + return PCIBIOS_DEVICE_NOT_FOUND;
298 +
299 + return ar2315_pci_cfg_access(apc, devfn, where, size, &value, true);
300 +}
301 +
302 +static struct pci_ops ar2315_pci_ops = {
303 + .read = ar2315_pci_cfg_read,
304 + .write = ar2315_pci_cfg_write,
305 +};
306 +
307 +static int ar2315_pci_host_setup(struct ar2315_pci_ctrl *apc)
308 +{
309 + unsigned devfn = PCI_DEVFN(AR2315_PCI_HOST_SLOT, 0);
310 + int res;
311 + u32 id;
312 +
313 + res = ar2315_pci_local_cfg_rd(apc, devfn, PCI_VENDOR_ID, &id);
314 + if (res != PCIBIOS_SUCCESSFUL || id != AR2315_PCI_HOST_DEVID)
315 + return -ENODEV;
316 +
317 + /* Program MBARs */
318 + ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_0,
319 + AR2315_PCI_HOST_MBAR0);
320 + ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_1,
321 + AR2315_PCI_HOST_MBAR1);
322 + ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_2,
323 + AR2315_PCI_HOST_MBAR2);
324 +
325 + /* Run */
326 + ar2315_pci_local_cfg_wr(apc, devfn, PCI_COMMAND, PCI_COMMAND_MEMORY |
327 + PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
328 + PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY |
329 + PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK);
330 +
331 + return 0;
332 +}
333 +
334 +static void ar2315_pci_irq_handler(unsigned irq, struct irq_desc *desc)
335 +{
336 + struct ar2315_pci_ctrl *apc = irq_get_handler_data(irq);
337 + u32 pending = ar2315_pci_reg_read(apc, AR2315_PCI_ISR) &
338 + ar2315_pci_reg_read(apc, AR2315_PCI_IMR);
339 + unsigned pci_irq = 0;
340 +
341 + if (pending)
342 + pci_irq = irq_find_mapping(apc->domain, __ffs(pending));
343 +
344 + if (pci_irq)
345 + generic_handle_irq(pci_irq);
346 + else
347 + spurious_interrupt();
348 +}
349 +
350 +static void ar2315_pci_irq_mask(struct irq_data *d)
351 +{
352 + struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
353 +
354 + ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, BIT(d->hwirq), 0);
355 +}
356 +
357 +static void ar2315_pci_irq_mask_ack(struct irq_data *d)
358 +{
359 + struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
360 + u32 m = BIT(d->hwirq);
361 +
362 + ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, m, 0);
363 + ar2315_pci_reg_write(apc, AR2315_PCI_ISR, m);
364 +}
365 +
366 +static void ar2315_pci_irq_unmask(struct irq_data *d)
367 +{
368 + struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
369 +
370 + ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, 0, BIT(d->hwirq));
371 +}
372 +
373 +static struct irq_chip ar2315_pci_irq_chip = {
374 + .name = "AR2315-PCI",
375 + .irq_mask = ar2315_pci_irq_mask,
376 + .irq_mask_ack = ar2315_pci_irq_mask_ack,
377 + .irq_unmask = ar2315_pci_irq_unmask,
378 +};
379 +
380 +static int ar2315_pci_irq_map(struct irq_domain *d, unsigned irq,
381 + irq_hw_number_t hw)
382 +{
383 + irq_set_chip_and_handler(irq, &ar2315_pci_irq_chip, handle_level_irq);
384 + irq_set_chip_data(irq, d->host_data);
385 + return 0;
386 +}
387 +
388 +static struct irq_domain_ops ar2315_pci_irq_domain_ops = {
389 + .map = ar2315_pci_irq_map,
390 +};
391 +
392 +static void ar2315_pci_irq_init(struct ar2315_pci_ctrl *apc)
393 +{
394 + ar2315_pci_reg_mask(apc, AR2315_PCI_IER, AR2315_PCI_IER_ENABLE, 0);
395 + ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, (AR2315_PCI_INT_ABORT |
396 + AR2315_PCI_INT_EXT), 0);
397 +
398 + apc->irq_ext = irq_create_mapping(apc->domain, AR2315_PCI_IRQ_EXT);
399 +
400 + irq_set_chained_handler(apc->irq, ar2315_pci_irq_handler);
401 + irq_set_handler_data(apc->irq, apc);
402 +
403 + /* Clear any pending Abort or external Interrupts
404 + * and enable interrupt processing */
405 + ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT |
406 + AR2315_PCI_INT_EXT);
407 + ar2315_pci_reg_mask(apc, AR2315_PCI_IER, 0, AR2315_PCI_IER_ENABLE);
408 +}
409 +
410 +static int ar2315_pci_probe(struct platform_device *pdev)
411 +{
412 + struct ar2315_pci_ctrl *apc;
413 + struct device *dev = &pdev->dev;
414 + struct resource *res;
415 + int irq, err;
416 +
417 + apc = devm_kzalloc(dev, sizeof(*apc), GFP_KERNEL);
418 + if (!apc)
419 + return -ENOMEM;
420 +
421 + irq = platform_get_irq(pdev, 0);
422 + if (irq < 0)
423 + return -EINVAL;
424 + apc->irq = irq;
425 +
426 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
427 + "ar2315-pci-ctrl");
428 + apc->mmr_mem = devm_ioremap_resource(dev, res);
429 + if (IS_ERR(apc->mmr_mem))
430 + return PTR_ERR(apc->mmr_mem);
431 +
432 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
433 + "ar2315-pci-ext");
434 + if (!res)
435 + return -EINVAL;
436 +
437 + apc->mem_res.name = "AR2315 PCI mem space";
438 + apc->mem_res.parent = res;
439 + apc->mem_res.start = res->start;
440 + apc->mem_res.end = res->end;
441 + apc->mem_res.flags = IORESOURCE_MEM;
442 +
443 + /* Remap PCI config space */
444 + apc->cfg_mem = devm_ioremap_nocache(dev, res->start,
445 + AR2315_PCI_CFG_SIZE);
446 + if (!apc->cfg_mem) {
447 + dev_err(dev, "failed to remap PCI config space\n");
448 + return -ENOMEM;
449 + }
450 +
451 + /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */
452 + ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG,
453 + AR2315_PCIMISC_RST_MODE,
454 + AR2315_PCIRST_LOW);
455 + msleep(100);
456 +
457 + /* Bring the PCI out of reset */
458 + ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG,
459 + AR2315_PCIMISC_RST_MODE,
460 + AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8);
461 +
462 + ar2315_pci_reg_write(apc, AR2315_PCI_UNCACHE_CFG,
463 + 0x1E | /* 1GB uncached */
464 + (1 << 5) | /* Enable uncached */
465 + (0x2 << 30) /* Base: 0x80000000 */);
466 + ar2315_pci_reg_read(apc, AR2315_PCI_UNCACHE_CFG);
467 +
468 + msleep(500);
469 +
470 + err = ar2315_pci_host_setup(apc);
471 + if (err)
472 + return err;
473 +
474 + apc->domain = irq_domain_add_linear(NULL, AR2315_PCI_IRQ_COUNT,
475 + &ar2315_pci_irq_domain_ops, apc);
476 + if (!apc->domain) {
477 + dev_err(dev, "failed to add IRQ domain\n");
478 + return -ENOMEM;
479 + }
480 +
481 + ar2315_pci_irq_init(apc);
482 +
483 + /* PCI controller does not support I/O ports */
484 + apc->io_res.name = "AR2315 IO space";
485 + apc->io_res.start = 0;
486 + apc->io_res.end = 0;
487 + apc->io_res.flags = IORESOURCE_IO,
488 +
489 + apc->pci_ctrl.pci_ops = &ar2315_pci_ops;
490 + apc->pci_ctrl.mem_resource = &apc->mem_res,
491 + apc->pci_ctrl.io_resource = &apc->io_res,
492 +
493 + register_pci_controller(&apc->pci_ctrl);
494 +
495 + dev_info(dev, "register PCI controller\n");
496 +
497 + return 0;
498 +}
499 +
500 +static struct platform_driver ar2315_pci_driver = {
501 + .probe = ar2315_pci_probe,
502 + .driver = {
503 + .name = "ar2315-pci",
504 + .owner = THIS_MODULE,
505 + },
506 +};
507 +
508 +static int __init ar2315_pci_init(void)
509 +{
510 + return platform_driver_register(&ar2315_pci_driver);
511 +}
512 +arch_initcall(ar2315_pci_init);
513 +
514 +int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
515 +{
516 + struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(dev->bus);
517 +
518 + return slot ? 0 : apc->irq_ext;
519 +}
520 +
521 +int pcibios_plat_dev_init(struct pci_dev *dev)
522 +{
523 + return 0;
524 +}
525 --- a/arch/mips/ath25/Kconfig
526 +++ b/arch/mips/ath25/Kconfig
527 @@ -7,3 +7,10 @@ config SOC_AR2315
528 bool "Atheros AR2315+ SoC support"
529 depends on ATH25
530 default y
531 +
532 +config PCI_AR2315
533 + bool "Atheros AR2315 PCI controller support"
534 + depends on SOC_AR2315
535 + select HW_HAS_PCI
536 + select PCI
537 + default y
538 --- a/arch/mips/ath25/ar2315.c
539 +++ b/arch/mips/ath25/ar2315.c
540 @@ -134,6 +134,10 @@ static void ar2315_irq_dispatch(void)
541
542 if (pending & CAUSEF_IP3)
543 do_IRQ(AR2315_IRQ_WLAN0);
544 +#ifdef CONFIG_PCI_AR2315
545 + else if (pending & CAUSEF_IP5)
546 + do_IRQ(AR2315_IRQ_LCBUS_PCI);
547 +#endif
548 else if (pending & CAUSEF_IP2)
549 do_IRQ(AR2315_IRQ_MISC);
550 else if (pending & CAUSEF_IP7)
551 @@ -299,10 +303,62 @@ void __init ar2315_plat_mem_setup(void)
552 _machine_restart = ar2315_restart;
553 }
554
555 +#ifdef CONFIG_PCI_AR2315
556 +static struct resource ar2315_pci_res[] = {
557 + {
558 + .name = "ar2315-pci-ctrl",
559 + .flags = IORESOURCE_MEM,
560 + .start = AR2315_PCI_BASE,
561 + .end = AR2315_PCI_BASE + AR2315_PCI_SIZE - 1,
562 + },
563 + {
564 + .name = "ar2315-pci-ext",
565 + .flags = IORESOURCE_MEM,
566 + .start = AR2315_PCI_EXT_BASE,
567 + .end = AR2315_PCI_EXT_BASE + AR2315_PCI_EXT_SIZE - 1,
568 + },
569 + {
570 + .name = "ar2315-pci",
571 + .flags = IORESOURCE_IRQ,
572 + .start = AR2315_IRQ_LCBUS_PCI,
573 + .end = AR2315_IRQ_LCBUS_PCI,
574 + },
575 +};
576 +#endif
577 +
578 void __init ar2315_arch_init(void)
579 {
580 unsigned irq = irq_create_mapping(ar2315_misc_irq_domain,
581 AR2315_MISC_IRQ_UART0);
582
583 ath25_serial_setup(AR2315_UART0_BASE, irq, ar2315_apb_frequency());
584 +
585 +#ifdef CONFIG_PCI_AR2315
586 + if (ath25_soc == ATH25_SOC_AR2315) {
587 + /* Reset PCI DMA logic */
588 + ar2315_rst_reg_mask(AR2315_RESET, 0, AR2315_RESET_PCIDMA);
589 + msleep(20);
590 + ar2315_rst_reg_mask(AR2315_RESET, AR2315_RESET_PCIDMA, 0);
591 + msleep(20);
592 +
593 + /* Configure endians */
594 + ar2315_rst_reg_mask(AR2315_ENDIAN_CTL, 0, AR2315_CONFIG_PCIAHB |
595 + AR2315_CONFIG_PCIAHB_BRIDGE);
596 +
597 + /* Configure as PCI host with DMA */
598 + ar2315_rst_reg_write(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM |
599 + (AR2315_PCICLK_IN_FREQ_DIV_6 <<
600 + AR2315_PCICLK_DIV_S));
601 + ar2315_rst_reg_mask(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI);
602 + ar2315_rst_reg_mask(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK |
603 + AR2315_IF_MASK, AR2315_IF_PCI |
604 + AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR |
605 + (AR2315_IF_PCI_CLK_OUTPUT_CLK <<
606 + AR2315_IF_PCI_CLK_SHIFT));
607 +
608 + platform_device_register_simple("ar2315-pci", -1,
609 + ar2315_pci_res,
610 + ARRAY_SIZE(ar2315_pci_res));
611 + }
612 +#endif
613 }
OpenWrt Source Repository