ath79: apply Engenius ECB1750 style to OpenMesh MR900 RGMII cfg
[openwrt/openwrt.git] / target / linux / ath79 / dts / ar7100.dtsi
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "ath79.dtsi"
4
5 / {
6 compatible = "qca,ar7100";
7
8 chosen {
9 bootargs = "console=ttyS0,115200";
10 };
11
12 cpus {
13 #address-cells = <1>;
14 #size-cells = <0>;
15
16 cpu@0 {
17 device_type = "cpu";
18 compatible = "mips,mips24Kc";
19 clocks = <&pll ATH79_CLK_CPU>;
20 reg = <0>;
21 };
22 };
23
24 ahb {
25 apb {
26 ddr_ctrl: memory-controller@18000000 {
27 compatible = "qca,ar7100-ddr-controller";
28 reg = <0x18000000 0x100>;
29
30 #qca,ddr-wb-channel-cells = <1>;
31 };
32
33 uart: uart@18020000 {
34 compatible = "ns16550a";
35 reg = <0x18020000 0x20>;
36 interrupts = <3>;
37
38 clocks = <&pll ATH79_CLK_AHB>;
39 clock-names = "uart";
40
41 reg-io-width = <4>;
42 reg-shift = <2>;
43 no-loopback-test;
44
45 status = "disabled";
46 };
47
48 usb_phy: usb-phy@18030000 {
49 compatible = "qca,ar7100-usb-phy";
50 reg = <0x18030000 0x10>;
51
52 reset-names = "usb-phy", "usb-host", "usb-ohci-dll";
53 resets = <&rst 4>, <&rst 5>, <&rst 6>;
54
55 #phy-cells = <0>;
56
57 status = "disabled";
58 };
59
60 gpio: gpio@18040000 {
61 compatible = "qca,ar7100-gpio";
62 reg = <0x18040000 0x30>;
63 interrupts = <2>;
64
65 ngpios = <16>;
66
67 gpio-controller;
68 #gpio-cells = <2>;
69
70 interrupt-controller;
71 #interrupt-cells = <2>;
72 };
73
74 pll: pll-controller@18050000 {
75 compatible = "qca,ar7100-pll", "syscon";
76 reg = <0x18050000 0x20>;
77
78 clock-names = "ref";
79 /* The board must provides the ref clock */
80
81 #clock-cells = <1>;
82 clock-output-names = "cpu", "ddr", "ahb";
83 };
84
85 wdt: wdt@18060008 {
86 compatible = "qca,ar7130-wdt";
87 reg = <0x18060008 0x8>;
88
89 interrupts = <4>;
90
91 clocks = <&pll ATH79_CLK_AHB>;
92 clock-names = "wdt";
93 };
94
95 pci_intc: interrupt-controller@18060018 {
96 compatible = "qca,ar7100-misc-intc";
97 reg = <0x18060018 0x4>;
98 interrupt-parent = <&cpuintc>;
99 interrupts = <2>;
100 interrupt-controller;
101 #interrupt-cells = <1>;
102 };
103
104 rst: reset-controller@18060024 {
105 compatible = "qca,ar7100-reset";
106 reg = <0x18060024 0x4>;
107
108 #reset-cells = <1>;
109 };
110
111 pcie0: pcie-controller@17010000 {
112 compatible = "qca,ar7100-pci";
113 #address-cells = <3>;
114 #size-cells = <2>;
115 bus-range = <0x0 0x0>;
116 reg = <0x17010000 0x100>;
117 reg-names = "cfg_base";
118 ranges = <0x2000000 0 0x10000000 0x10000000 0 0x07000000 /* pci memory */
119 0x1000000 0 0x00000000 0x0000000 0 0x000001>; /* io space */
120
121 interrupt-parent = <&pci_intc>;
122 interrupts = <4>;
123
124 #interrupt-cells = <1>;
125
126 interrupt-map-mask = <0xf800 0 0 0>;
127 interrupt-map = <0x8800 0 0 0 &pci_intc 0
128 0x9000 0 0 0 &pci_intc 1
129 0x9800 0 0 0 &pci_intc 2>;
130
131 status = "disabled";
132 };
133 };
134 };
135
136 usb2: usb@1b000000 {
137 compatible = "generic-ehci";
138 reg = <0x1b000000 0x1000>;
139
140 interrupt-parent = <&cpuintc>;
141 interrupts = <3>;
142
143 phy-names = "usb-phy";
144 phys = <&usb_phy>;
145
146 has-synopsys-hc-bug;
147
148 status = "disabled";
149 };
150
151 usb1: usb@1c000000 {
152 compatible = "generic-ohci";
153 reg = <0x1c000000 0x1000>;
154
155 interrupt-parent = <&miscintc>;
156 interrupts = <6>;
157
158 phy-names = "usb-phy";
159 phys = <&usb_phy>;
160
161 status = "disabled";
162 };
163
164 spi: spi@1f000000 {
165 compatible = "qca,ar7100-spi";
166 reg = <0x1f000000 0x10>;
167
168 clocks = <&pll ATH79_CLK_AHB>;
169 clock-names = "ahb";
170
171 #address-cells = <1>;
172 #size-cells = <0>;
173
174 status = "disabled";
175 };
176 };
177
178 &cpuintc {
179 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
180 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
181 <&ddr_ctrl 0>, <&ddr_ctrl 1>;
182 };
183
184 &miscintc {
185 compatible = "qca,ar7100-misc-intc";
186 };
187
188 &eth0 {
189 compatible = "qca,ar7100-eth", "syscon";
190 reg = <0x19000000 0x200
191 0x18070000 0x4>;
192
193 pll-data = <0x00110000 0x00001099 0x00991099>;
194 pll-reg = <0x4 0x10 17>;
195 pll-handle = <&pll>;
196 phy-mode = "rgmii";
197
198 resets = <&rst 9>;
199 reset-names = "mac";
200 qca,mac-idx = <0>;
201 };
202
203 &mdio1 {
204 builtin-switch;
205 };
206
207 &eth1 {
208 compatible = "qca,ar7100-eth", "syscon";
209 reg = <0x1a000000 0x200
210 0x18070004 0x4>;
211
212 pll-data = <0x00110000 0x00001099 0x00991099>;
213 pll-reg = <0x4 0x14 19>;
214 pll-handle = <&pll>;
215
216 phy-mode = "rgmii";
217
218 resets = <&rst 13>;
219 reset-names = "mac";
220 qca,mac-idx = <1>;
221 };