ath79: enable UART in SoC DTSI files
[openwrt/openwrt.git] / target / linux / ath79 / dts / ar7161_dlink_dir-825-b1.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "ar7100.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7
8 / {
9 compatible = "dlink,dir-825-b1", "qca,ar7161";
10 model = "D-Link DIR825B1";
11
12 aliases {
13 led-boot = &led_power_orange;
14 led-failsafe = &led_power_orange;
15 led-running = &led_power_blue;
16 led-upgrade = &led_power_orange;
17 };
18
19 extosc: ref {
20 compatible = "fixed-clock";
21 #clock-cells = <0>;
22 clock-output-names = "ref";
23 clock-frequency = <40000000>;
24 };
25
26 leds {
27 compatible = "gpio-leds";
28
29 usb {
30 label = "blue:usb";
31 gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
32 trigger-sources = <&usb_ohci_port>, <&usb_ehci_port>;
33 linux,default-trigger = "usbport";
34 };
35
36 led_power_orange: power_orange {
37 label = "orange:power";
38 gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
39 default-state = "on";
40 };
41
42 led_power_blue: power_blue {
43 label = "blue:power";
44 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
45 };
46
47 wps {
48 label = "blue:wps";
49 gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
50 };
51
52 planet_orange {
53 label = "orange:planet";
54 gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
55 };
56
57 planet_blue {
58 label = "blue:planet";
59 gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
60 };
61 };
62
63 ath9k-leds {
64 compatible = "gpio-leds";
65
66 wlan2g {
67 label = "blue:wlan2g";
68 gpios = <&ath9k0 5 GPIO_ACTIVE_LOW>;
69 linux,default-trigger = "phy0tpt";
70 };
71
72 wlan5g {
73 label = "blue:wlan5g";
74 gpios = <&ath9k1 5 GPIO_ACTIVE_LOW>;
75 linux,default-trigger = "phy1tpt";
76 };
77 };
78
79 keys {
80 compatible = "gpio-keys";
81
82 reset {
83 label = "reset";
84 linux,code = <KEY_RESTART>;
85 gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
86 };
87
88 wps {
89 label = "wps";
90 linux,code = <KEY_WPS_BUTTON>;
91 gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
92 };
93 };
94
95 rtl8366s {
96 compatible = "realtek,rtl8366s";
97 gpio-sda = <&gpio 5 GPIO_ACTIVE_HIGH>;
98 gpio-sck = <&gpio 7 GPIO_ACTIVE_HIGH>;
99 realtek,initvals = <0x06 0x0108>;
100
101 mdio-bus {
102 #address-cells = <1>;
103 #size-cells = <0>;
104 status = "okay";
105
106 phy-mask = <0x10>;
107
108 phy4: ethernet-phy@4 {
109 reg = <4>;
110 phy-mode = "rgmii";
111 };
112 };
113 };
114 };
115
116 &usb1 {
117 #address-cells = <1>;
118 #size-cells = <0>;
119 status = "okay";
120
121 usb_ohci_port: port@1 {
122 reg = <1>;
123 #trigger-source-cells = <0>;
124 };
125 };
126
127 &usb2 {
128 #address-cells = <1>;
129 #size-cells = <0>;
130 status = "okay";
131
132 usb_ehci_port: port@1 {
133 reg = <1>;
134 #trigger-source-cells = <0>;
135 };
136 };
137
138 &usb_phy {
139 status = "okay";
140 };
141
142 &pcie0 {
143 status = "okay";
144
145 ath9k0: wifi@0,11 {
146 compatible = "pci168c,0029";
147 reg = <0x8800 0 0 0 0>;
148 qca,no-eeprom;
149 #gpio-cells = <2>;
150 gpio-controller;
151 };
152
153 ath9k1: wifi@0,12 {
154 compatible = "pci168c,0029";
155 reg = <0x9000 0 0 0 0>;
156 qca,no-eeprom;
157 #gpio-cells = <2>;
158 gpio-controller;
159 };
160 };
161
162 &pll {
163 clocks = <&extosc>;
164 };
165
166 &spi {
167 status = "okay";
168
169 flash@0 {
170 compatible = "jedec,spi-nor";
171 reg = <0>;
172 spi-max-frequency = <25000000>;
173
174 partitions {
175 compatible = "fixed-partitions";
176 #address-cells = <1>;
177 #size-cells = <1>;
178
179 partition@0 {
180 label = "u-boot";
181 reg = <0x000000 0x040000>;
182 read-only;
183 };
184
185 partition@40000 {
186 label = "config";
187 reg = <0x040000 0x010000>;
188 read-only;
189 };
190
191 partition@50000 {
192 compatible = "denx,uimage";
193 label = "firmware";
194 reg = <0x050000 0x610000>;
195 };
196
197 partition@660000 {
198 label = "caldata";
199 reg = <0x660000 0x010000>;
200 read-only;
201 };
202
203 partition@670000 {
204 label = "unknown";
205 reg = <0x670000 0x190000>;
206 read-only;
207 };
208 };
209 };
210 };
211
212 &eth0 {
213 status = "okay";
214
215 pll-data = <0x11110000 0x00001099 0x00991099>;
216
217 fixed-link {
218 speed = <1000>;
219 full-duplex;
220 };
221 };
222
223 &eth1 {
224 status = "okay";
225
226 pll-data = <0x11110000 0x00001099 0x00991099>;
227
228 phy-handle = <&phy4>;
229 };