ath79: enable UART in SoC DTSI files
[openwrt/openwrt.git] / target / linux / ath79 / dts / ar7241_tplink.dtsi
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "ar7241.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7
8 / {
9 aliases {
10 led-boot = &led_system;
11 led-failsafe = &led_system;
12 led-running = &led_system;
13 led-upgrade = &led_system;
14 label-mac-device = &ath9k;
15 };
16
17 keys {
18 compatible = "gpio-keys";
19
20 reset {
21 label = "reset";
22 linux,code = <KEY_RESTART>;
23 gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
24 debounce-interval = <60>;
25 };
26
27 qss {
28 label = "qss";
29 linux,code = <KEY_WPS_BUTTON>;
30 gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
31 debounce-interval = <60>;
32 };
33 };
34
35 leds: leds {
36 compatible = "gpio-leds";
37
38 led_system: system {
39 label = "green:system";
40 gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
41 };
42
43 qss {
44 label = "green:qss";
45 gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
46 };
47 };
48 };
49
50 &spi {
51 status = "okay";
52
53 flash@0 {
54 compatible = "jedec,spi-nor";
55 reg = <0>;
56 spi-max-frequency = <25000000>;
57
58 partitions {
59 compatible = "fixed-partitions";
60 #address-cells = <1>;
61 #size-cells = <1>;
62
63 uboot: partition@0 {
64 reg = <0x0 0x20000>;
65 label = "u-boot";
66 read-only;
67 };
68
69 partition@20000 {
70 compatible = "tplink,firmware";
71 reg = <0x20000 0x3d0000>;
72 label = "firmware";
73 };
74
75 partition@3f0000 {
76 reg = <0x3f0000 0x10000>;
77 label = "art";
78 read-only;
79 };
80 };
81 };
82 };
83
84 &pcie {
85 status = "okay";
86
87 ath9k: wifi@0,0 {
88 reg = <0x0000 0 0 0 0>;
89 #gpio-cells = <2>;
90 gpio-controller;
91 qca,no-eeprom;
92 mtd-mac-address = <&uboot 0x1fc00>;
93 };
94 };
95
96 &eth0 {
97 status = "okay";
98
99 mtd-mac-address = <&uboot 0x1fc00>;
100 mtd-mac-address-increment = <(-1)>;
101 };
102
103 &eth1 {
104 mtd-mac-address = <&uboot 0x1fc00>;
105 mtd-mac-address-increment = <1>;
106 };