ath79: add d-link dir-825-c1 and dir-835-a1
[openwrt/openwrt.git] / target / linux / ath79 / dts / ar9344_dlink_dir-8x5.dtsi
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 /dts-v1/;
3
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
6
7 #include "ar9344.dtsi"
8
9 / {
10 chosen {
11 bootargs = "console=ttyS0,115200";
12 };
13
14 keys {
15 compatible = "gpio-keys";
16
17 reset {
18 linux,code = <KEY_RESTART>;
19 gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
20 debounce-interval = <60>;
21 };
22
23 wps {
24 linux,code = <KEY_WPS_BUTTON>;
25 gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
26 debounce-interval = <60>;
27 };
28 };
29 };
30
31 &eth0 {
32 status = "okay";
33
34 /* default for ar934x, except for 1000M */
35 pll-data = <0x06000000 0x00000101 0x00001616>;
36
37 phy-mode = "rgmii";
38 phy-handle = <&phy0>;
39 };
40
41 &mdio0 {
42 status = "okay";
43
44 phy-mask = <0>;
45
46 phy0: ethernet-phy@0 {
47 reg = <0>;
48 qca,ar8327-initvals = <
49 /* GPL code drop (bsp.h & athrs17_phy.c) */
50 0x10 0xc1000000 /* PWS_REG_VALUE */
51 0x04 0x07600000 /* PORT0 PAD Mode */
52 0x0c 0x01000000 /* PORT6 PAD Mode */
53 0x7c 0x0000007e /* PORT0_STATUS */
54 0x94 0x0000007e /* PORT6_STATUS */
55 >;
56 };
57 };
58
59 &pcie {
60 status = "okay";
61
62 ath9k: wifi@0,0 {
63 compatible = "pci168c,0030";
64 reg = <0x0000 0 0 0 0>;
65 qca,no-eeprom;
66 gpio-controller;
67 #gpio-cells = <2>;
68 };
69 };
70
71 &ref {
72 clock-frequency = <40000000>;
73 };
74
75 &spi {
76 status = "okay";
77 num-cs = <1>;
78
79 flash@0 {
80 compatible = "jedec,spi-nor";
81 reg = <0>;
82 spi-max-frequency = <25000000>;
83
84 partitions {
85 compatible = "fixed-partitions";
86 #address-cells = <1>;
87 #size-cells = <1>;
88
89 partition@0 {
90 label = "uboot";
91 reg = <0x000000 0x010000>;
92 read-only;
93 };
94
95 partition@10000 {
96 label = "nvram";
97 reg = <0x010000 0x010000>;
98 read-only;
99 };
100
101 partition@20000 {
102 label = "firmware";
103 reg = <0x020000 0xF90000>;
104 compatible = "denx,uimage";
105 };
106
107 partition@fb0000 {
108 label = "lang";
109 reg = <0xfb0000 0x030000>;
110 read-only;
111 };
112
113 partition@fe0000 {
114 label = "mac";
115 reg = <0xfe0000 0x010000>;
116 read-only;
117 };
118
119 partition@ff0000 {
120 label = "art";
121 reg = <0xff0000 0x010000>;
122 read-only;
123 };
124 };
125 };
126 };
127
128 &uart {
129 status = "okay";
130 };
131
132 &usb {
133 status = "okay";
134 #address-cells = <1>;
135 #size-cells = <0>;
136
137 hub_port1: port@1 {
138 reg = <1>;
139 #trigger-source-cells = <0>;
140 };
141 };
142
143 &usb_phy {
144 status = "okay";
145 };
146
147 &wmac {
148 status = "okay";
149 qca,no-eeprom;
150 };
151