ath79: enable UART in SoC DTSI files
[openwrt/openwrt.git] / target / linux / ath79 / dts / ar9344_enterasys_ws-ap3705i.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "ar9344.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7
8 / {
9 compatible = "enterasys,ws-ap3705i", "qca,ar9344";
10 model = "Enterasys WS-AP3705i";
11
12 chosen {
13 bootargs = "console=ttyS0,115200n8";
14 };
15
16 aliases {
17 led-boot = &led_power_green;
18 led-failsafe = &led_power_red;
19 led-running = &led_power_green;
20 led-upgrade = &led_power_red;
21 label-mac-device = &eth0;
22 };
23
24 mtd-concat {
25 compatible = "mtd-concat";
26 devices = <&fwconcat0 &fwconcat1>;
27
28 partitions {
29 compatible = "fixed-partitions";
30 #address-cells = <1>;
31 #size-cells = <1>;
32
33 partition@0 {
34 compatible = "denx,uimage";
35 label = "firmware";
36 reg = <0x0 0x1dd0000>;
37 };
38 };
39 };
40
41 leds {
42 compatible = "gpio-leds";
43
44 pinctrl-names = "default";
45 pinctrl-0 = <&enable_gpio_11 &enable_gpio_16>;
46
47 led_power_green: power_green {
48 label = "green:power";
49 gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
50 };
51
52 led_power_red: power_red {
53 label = "red:power";
54 gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
55 };
56
57 lan_blue {
58 label = "blue:lan";
59 gpios = <&gpio 19 GPIO_ACTIVE_HIGH>;
60 };
61
62 lan_green {
63 label = "green:lan";
64 gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
65 };
66
67 radio2 {
68 label = "green:radio2";
69 gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
70 linux,default-trigger = "phy0tpt";
71 };
72 };
73
74 ath9k-leds {
75 compatible = "gpio-leds";
76
77 radio1 {
78 label = "green:radio1";
79 gpios = <&ath9k 0 GPIO_ACTIVE_LOW>;
80 linux,default-trigger = "phy1tpt";
81 };
82 };
83
84 keys {
85 compatible = "gpio-keys";
86
87 reset {
88 label = "Reset button";
89 linux,code = <KEY_RESTART>;
90 gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
91 };
92 };
93 };
94
95 &ref {
96 clock-frequency = <40000000>;
97 };
98
99 &pinmux {
100 enable_gpio_16: pinmux_enable_gpio_16 {
101 pinctrl-single,bits = <0x10 0x0 0x000000ff>;
102 };
103
104 enable_gpio_11: pinmux_enable_gpio_11 {
105 pinctrl-single,bits = <0x8 0x0 0xff000000>;
106 };
107 };
108
109 &wmac {
110 status = "okay";
111 qca,no-eeprom;
112 };
113
114 &spi {
115 status = "okay";
116
117 cs-gpios = <0>, <0>;
118
119 flash@0 {
120 compatible = "jedec,spi-nor";
121 reg = <0>;
122 spi-max-frequency = <25000000>;
123
124 partitions {
125 compatible = "fixed-partitions";
126 #address-cells = <1>;
127 #size-cells = <1>;
128
129 partition@0 {
130 label = "u-boot-bak";
131 reg = <0x0 0x80000>;
132 read-only;
133 };
134
135 partition@80000 {
136 label = "u-boot-env0";
137 reg = <0x80000 0x10000>;
138 read-only;
139 };
140
141 partition@90000 {
142 label = "u-boot-env1";
143 reg = <0x90000 0x10000>;
144 read-only;
145 };
146
147 partition@a0000 {
148 label = "u-boot";
149 reg = <0xa0000 0x80000>;
150 read-only;
151 };
152
153 partition@120000 {
154 label = "calibrate";
155 reg = <0x120000 0x10000>;
156 read-only;
157 };
158
159 partition@130000 {
160 label = "nvram";
161 reg = <0x130000 0x100000>;
162 read-only;
163 };
164
165 fwconcat0: partition@230000 {
166 label = "fwconcat0";
167 reg = <0x230000 0xdd0000>;
168 };
169 };
170 };
171
172 flash@1 {
173 compatible = "jedec,spi-nor";
174 reg = <1>;
175 spi-max-frequency = <25000000>;
176
177 partitions {
178 compatible = "fixed-partitions";
179 #address-cells = <1>;
180 #size-cells = <1>;
181
182 fwconcat1: partition@0 {
183 label = "fwconcat1";
184 reg = <0x0 0x1000000>;
185 };
186 };
187 };
188 };
189
190 &pcie {
191 status = "okay";
192
193 ath9k: wifi@0,0 {
194 compatible = "pci168c,0033";
195 reg = <0x0000 0 0 0 0>;
196 qca,no-eeprom;
197 #gpio-cells = <2>;
198 gpio-controller;
199 };
200 };
201
202 &mdio0 {
203 status = "okay";
204
205 phy0: ethernet-phy@0 {
206 reg = <0>;
207 };
208 };
209
210 &eth0 {
211 status = "okay";
212
213 pll-data = <0x1e000000 0x08000101 0x08001313>;
214
215 phy-mode = "rgmii";
216 phy-handle = <&phy0>;
217
218 gmac-config {
219 device = <&gmac>;
220 rgmii-gmac0 = <1>;
221 rxd-delay = <0>;
222 rxdv-delay = <0>;
223 txen-delay = <0>;
224 txd-delay = <0>;
225 };
226 };