target/linux/ath79/dts/ar9344_wd_mynet-n750.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2 /dts-v1/;
   3
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/input/input.h>
   6
   7 #include "ar9344.dtsi"
   8
   9 / {
  10         model = "Western Digital My Net N750";
  11         compatible = "wd,mynet-n750", "qca,ar9344";
  12
  13         chosen {
  14                 bootargs = "console=ttyS0,115200n8";
  15         };
  16
  17         aliases {
  18                 led-boot = &led_power;
  19                 led-failsafe = &led_power;
  20                 led-running = &led_power;
  21                 led-upgrade = &led_power;
  22         };
  23
  24         leds {
  25                 compatible = "gpio-leds";
  26
  27                 wifi {
  28                         label = "mynet-n750:blue:wireless";
  29                         gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
  30                 };
  31
  32                 internet {
  33                         label = "mynet-n750:blue:internet";
  34                         gpios = <&gpio 12 GPIO_ACTIVE_HIGH>;
  35                 };
  36
  37                 wps {
  38                         label = "mynet-n750:blue:wps";
  39                         gpios = <&gpio 13 GPIO_ACTIVE_HIGH>;
  40                 };
  41
  42                 led_power: power {
  43                         label = "mynet-n750:blue:power";
  44                         gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
  45                 };
  46         };
  47
  48         keys {
  49                 compatible = "gpio-keys";
  50
  51                 reset {
  52                         linux,code = <KEY_RESTART>;
  53                         gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
  54                 };
  55
  56                 wps {
  57                         linux,code = <KEY_WPS_BUTTON>;
  58                         gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
  59                 };
  60         };
  61 };
  62
  63 &ref {
  64         clock-frequency = <40000000>;
  65 };
  66
  67 &uart {
  68         status = "okay";
  69 };
  70
  71 &gpio {
  72         gpio_ext_lna0 {
  73                 gpio-hog;
  74                 gpios = <15 0>;
  75                 output-high;
  76                 line-name = "mynet-n750:ext:lna0";
  77         };
  78
  79         gpio_ext_lna1 {
  80                 gpio-hog;
  81                 gpios = <18 0>;
  82                 output-high;
  83                 line-name = "mynet-n750:ext:lna1";
  84         };
  85 };
  86
  87 &spi {
  88         status = "okay";
  89
  90         num-cs = <1>;
  91
  92         flash@0 {
  93                 compatible = "jedec,spi-nor";
  94                 reg = <0>;
  95                 spi-max-frequency = <25000000>;
  96
  97                 partitions {
  98                         compatible = "fixed-partitions";
  99                         #address-cells = <1>;
 100                         #size-cells = <1>;
 101
 102                         partition@0 {
 103                                 label = "bootloader";
 104                                 reg = <0x000000 0x40000>;
 105                                 read-only;
 106                         };
 107
 108                         partition@40000 {
 109                                 label = "bdcfg";
 110                                 reg = <0x040000 0x10000>;
 111                                 read-only;
 112                         };
 113
 114                         partition@50000 {
 115                                 label = "devdata";
 116                                 reg = <0x050000 0x10000>;
 117                                 read-only;
 118                         };
 119
 120                         partition@60000 {
 121                                 label = "devconf";
 122                                 reg = <0x060000 0x10000>;
 123                                 read-only;
 124                         };
 125
 126                         partition@70000 {
 127                                 compatible = "seama";
 128                                 label = "firmware";
 129                                 reg = <0x070000 0xf80000>;
 130                         };
 131
 132                         art: partition@ff0000 {
 133                                 label = "art";
 134                                 reg = <0xff0000 0x010000>;
 135                                 read-only;
 136                         };
 137                 };
 138         };
 139 };
 140
 141 &usb {
 142         #address-cells = <1>;
 143         #size-cells = <0>;
 144         status = "okay";
 145
 146         port@1 {
 147                 #address-cells = <1>;
 148                 #size-cells = <0>;
 149                 reg = <1>;
 150                 #trigger-source-cells = <0>;
 151
 152                 hub_port1: port@1 {
 153                         reg = <1>;
 154                         #trigger-source-cells = <0>;
 155                 };
 156
 157                 hub_port2: port@2 {
 158                         reg = <2>;
 159                         #trigger-source-cells = <0>;
 160                 };
 161         };
 162 };
 163
 164 &usb_phy {
 165         status = "okay";
 166 };
 167
 168 &pcie {
 169         status = "okay";
 170
 171         wifi@0,0 {
 172                 compatible = "pci168c,0033";
 173                 reg = <0x0000 0 0 0 0>;
 174                 qca,no-eeprom;
 175         };
 176 };
 177
 178 &wmac {
 179         status = "okay";
 180
 181         qca,no-eeprom;
 182 };
 183
 184 &mdio0 {
 185         status = "okay";
 186
 187         phy-mask = <0>;
 188
 189         switch0@1f {
 190                 compatible = "qca,ar8327";
 191                 reg = <0x1f>;
 192
 193                 qca,ar8327-initvals = <
 194                         0x04 0x07600000 /* PORT0 PAD MODE CTRL */
 195                         0x10 0x80000080 /* POWER_ON_STRIP */
 196                         0x50 0xc737c737 /* LED_CTRL0 */
 197                         0x54 0x00000000 /* LED_CTRL1 */
 198                         0x58 0x00000000 /* LED_CTRL2 */
 199                         0x5c 0x0030c300 /* LED_CTRL3 */
 200                         0x7c 0x0000007e /* PORT0_STATUS */
 201                         >;
 202         };
 203 };
 204
 205 &eth0 {
 206         status = "okay";
 207
 208         /* default for ar934x, except for 1000M */
 209         pll-data = <0x06000000 0x00000101 0x00001616>;
 210
 211         phy-mode = "rgmii";
 212         fixed-link {
 213                 speed = <1000>;
 214                 full-duplex;
 215         };
 216 };