ath79: enable UART in SoC DTSI files
[openwrt/openwrt.git] / target / linux / ath79 / dts / qca9531_tplink_tl-mr3420-v3.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "qca953x.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7
8 / {
9 compatible = "tplink,tl-mr3420-v3", "qca,qca9531";
10 model = "TP-Link TL-MR3420 v3";
11
12 aliases {
13 led-boot = &led_system;
14 led-failsafe = &led_system;
15 led-running = &led_system;
16 led-upgrade = &led_system;
17 label-mac-device = &wmac;
18
19 };
20
21 led_spi {
22 compatible = "spi-gpio";
23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 sck-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
27 mosi-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
28 cs-gpios = <&gpio 13 GPIO_ACTIVE_HIGH>;
29 num-chipselects = <1>;
30
31 led_gpio: led_gpio@0 {
32 compatible = "fairchild,74hc595";
33 reg = <0>;
34 gpio-controller;
35 #gpio-cells = <2>;
36 registers-number = <1>;
37 spi-max-frequency = <10000000>;
38 };
39 };
40
41 gpio-export {
42 compatible = "gpio-export";
43
44 gpio_shift_register_oe {
45 gpio-export,name = "tp-link:oe:sr";
46 gpio-export,output = <0>;
47 gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
48 };
49
50 gpio_shift_register_reset {
51 gpio-export,name = "tp-link:reset:sr";
52 gpio-export,output = <1>;
53 gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
54 };
55 };
56
57 leds {
58 compatible = "gpio-leds";
59
60 led_system: system {
61 label = "green:system";
62 gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
63 default-state = "on";
64 };
65
66 lan4 {
67 label = "green:lan4";
68 gpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;
69 };
70
71 lan3 {
72 label = "green:lan3";
73 gpios = <&led_gpio 1 GPIO_ACTIVE_LOW>;
74 };
75
76 lan2 {
77 label = "green:lan2";
78 gpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;
79 };
80
81 lan1 {
82 label = "green:lan1";
83 gpios = <&led_gpio 3 GPIO_ACTIVE_LOW>;
84 };
85
86 wan {
87 label = "green:wan";
88 gpios = <&led_gpio 4 GPIO_ACTIVE_LOW>;
89 };
90
91 wan_fail {
92 label = "orange:wan";
93 gpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;
94 };
95
96 wlan {
97 label = "green:wlan";
98 gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
99 linux,default-trigger = "phy0tpt";
100 };
101
102 usb {
103 label = "green:usb";
104 gpios = <&led_gpio 7 GPIO_ACTIVE_LOW>;
105 trigger-sources = <&hub_port>;
106 linux,default-trigger = "usbport";
107 };
108
109 qss {
110 label = "green:qss";
111 gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
112 };
113 };
114
115 keys {
116 compatible = "gpio-keys";
117
118 reset {
119 label = "Reset button";
120 linux,code = <KEY_RESTART>;
121 gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
122 debounce-interval = <60>;
123 };
124
125 rfkill {
126 label = "RF kill button";
127 linux,code = <KEY_RFKILL>;
128 gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
129 debounce-interval = <60>;
130 };
131 };
132
133 };
134
135 &spi {
136 status = "okay";
137
138 flash@0 {
139 compatible = "jedec,spi-nor";
140 reg = <0>;
141 spi-max-frequency = <25000000>;
142
143 partitions {
144 compatible = "fixed-partitions";
145 #address-cells = <1>;
146 #size-cells = <1>;
147
148 uboot: partition@0 {
149 label = "u-boot";
150 reg = <0x000000 0x020000>;
151 read-only;
152 };
153
154 partition@20000 {
155 compatible = "tplink,firmware";
156 label = "firmware";
157 reg = <0x020000 0x3d0000>;
158 };
159
160 art: partition@3f0000 {
161 label = "art";
162 reg = <0x3f0000 0x010000>;
163 read-only;
164 };
165 };
166 };
167 };
168
169 &eth0 {
170 status = "okay";
171
172 phy-handle = <&swphy4>;
173
174 mtd-mac-address = <&uboot 0x1fc00>;
175 mtd-mac-address-increment = <1>;
176 };
177
178 &eth1 {
179 mtd-mac-address = <&uboot 0x1fc00>;
180 };
181
182 &wmac {
183 status = "okay";
184
185 mtd-cal-data = <&art 0x1000>;
186 mtd-mac-address = <&uboot 0x1fc00>;
187 };
188
189 &usb0 {
190 #address-cells = <1>;
191 #size-cells = <0>;
192 status = "okay";
193
194 hub_port: port@1 {
195 reg = <1>;
196 #trigger-source-cells = <0>;
197 };
198 };
199
200 &usb_phy {
201 status = "okay";
202 };