ath79: add support for tl-wr1043nd v2/v3
[openwrt/openwrt.git] / target / linux / ath79 / dts / qca9557.dtsi
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 #include <dt-bindings/clock/ath79-clk.h>
3 #include "ath79.dtsi"
4
5 / {
6 compatible = "qca,qca9557";
7
8 #address-cells = <1>;
9 #size-cells = <1>;
10
11 cpus {
12 #address-cells = <1>;
13 #size-cells = <0>;
14
15 cpu@0 {
16 device_type = "cpu";
17 compatible = "mips,mips74Kc";
18 clocks = <&pll ATH79_CLK_CPU>;
19 reg = <0>;
20 };
21 };
22
23 extosc: ref {
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-output-names = "ref";
27 clock-frequency = <40000000>;
28 };
29
30 ahb {
31 apb {
32 ddr_ctrl: memory-controller@18000000 {
33 compatible = "qca,ar9557-ddr-controller",
34 "qca,ar7240-ddr-controller";
35 reg = <0x18000000 0x100>;
36
37 #qca,ddr-wb-channel-cells = <1>;
38 };
39
40 uart: uart@18020000 {
41 compatible = "ns16550a";
42 reg = <0x18020000 0x20>;
43
44 interrupts = <3>;
45
46 clocks = <&pll ATH79_CLK_REF>;
47 clock-names = "uart";
48
49 reg-io-width = <4>;
50 reg-shift = <2>;
51 no-loopback-test;
52
53 status = "disabled";
54 };
55
56 usb_phy0: usb-phy@18030000 {
57 compatible ="qca,qca9550-usb-phy", "qca,ar7200-usb-phy";
58
59 reset-names = "usb-phy", "usb-suspend-override";
60 resets = <&rst 4>, <&rst 3>;
61
62 #phy-cells = <0>;
63
64 status = "disabled";
65 };
66
67 usb_phy1: usb-phy {
68 compatible = "qca,qca9550-usb-phy", "qca,ar7200-usb-phy";
69
70 reset-names = "usb-phy", "usb-suspend-override";
71 resets = <&rst2 4>, <&rst2 3>;
72
73 #phy-cells = <0>;
74
75 status = "disabled";
76 };
77
78 gpio: gpio@18040000 {
79 compatible = "qca,ar9557-gpio",
80 "qca,ar9340-gpio";
81 reg = <0x18040000 0x28>;
82
83 interrupts = <2>;
84 ngpios = <24>;
85
86 gpio-controller;
87 #gpio-cells = <2>;
88
89 interrupt-controller;
90 #interrupt-cells = <2>;
91 };
92
93 pinmux: pinmux@1804002c {
94 compatible = "pinctrl-single";
95
96 reg = <0x1804002c 0x40>;
97
98 #size-cells = <0>;
99
100 pinctrl-single,bit-per-mux;
101 pinctrl-single,register-width = <32>;
102 pinctrl-single,function-mask = <0x1>;
103 #pinctrl-cells = <2>;
104
105 jtag_disable_pins: pinmux_jtag_disable_pins {
106 pinctrl-single,bits = <0x40 0x2 0x2>;
107 };
108 };
109
110 pll: pll-controller@18050000 {
111 compatible = "qca,ar9557-pll",
112 "qca,qca9550-pll";
113 reg = <0x18050000 0x50>;
114
115 #clock-cells = <1>;
116 clock-output-names = "cpu", "ddr", "ahb";
117
118 clocks = <&extosc>;
119 };
120
121 wdt: wdt@18060008 {
122 compatible = "qca,ar7130-wdt";
123 reg = <0x18060008 0x8>;
124
125 interrupts = <4>;
126
127 clocks = <&pll ATH79_CLK_AHB>;
128 clock-names = "wdt";
129 };
130
131 rst: reset-controller@1806001c {
132 compatible = "qca,qca9550-reset",
133 "qca,ar7100-reset",
134 "simple-bus";
135 reg = <0x1806001c 0x4>;
136
137 #reset-cells = <1>;
138 interrupt-parent = <&cpuintc>;
139
140 intc3: interrupt-controller@3 {
141 compatible = "qcom,qca9556-intc";
142
143 interrupts = <3>;
144
145 interrupt-controller;
146 #interrupt-cells = <1>;
147
148 qcom,pending-bits = <0x1f000>, /* pcie rc */
149 <0x1000000>, /* usb1 */
150 <0x10000000>; /* usb2 */
151 };
152 };
153
154 rst2: reset-controller@180600c0 {
155 compatible = "qca,qca9550-reset",
156 "qca,ar7100-reset",
157 "simple-bus";
158 reg = <0x180600c0 0x4>;
159
160 #reset-cells = <1>;
161 };
162
163 pcie: pcie-controller@18250000 {
164 compatible = "qcom,ar7240-pci";
165 #address-cells = <3>;
166 #size-cells = <2>;
167 bus-range = <0x0 0x0>;
168 reg = <0x18250000 0x1000>, /* CRP */
169 <0x18280000 0x100>, /* CTRL */
170 <0x16000000 0x1000>; /* CFG */
171 reg-names = "crp_base", "ctrl_base", "cfg_base";
172 ranges = <0x2000000 0 0x12000000 0x12000000 0 0x02000000 /* pci memory */
173 0x1000000 0 0x00000000 0x0000000 0 0x000001>; /* io space */
174 interrupt-parent = <&intc3>;
175 interrupts = <0>;
176
177 interrupt-controller;
178 #interrupt-cells = <1>;
179
180 interrupt-map-mask = <0 0 0 1>;
181 interrupt-map = <0 0 0 0 &pcie 0>;
182 status = "disabled";
183 };
184
185 wmac: wmac@18100000 {
186 compatible = "qca,qca9550-wmac";
187 reg = <0x18100000 0x10000>;
188
189 interrupt-parent = <&cpuintc>;
190 interrupts = <2>;
191
192 status = "disabled";
193 };
194 };
195
196 usb0: usb@1b000000 {
197 compatible = "generic-ehci";
198 reg = <0x1b000000 0x1fc>;
199
200 interrupt-parent = <&intc3>;
201 interrupts = <1>;
202 resets = <&rst 5>;
203 reset-names = "usb-host";
204
205 has-transaction-translator;
206 caps-offset = <0x100>;
207
208 phy-names = "usb-phy0";
209 phys = <&usb_phy0>;
210
211 status = "disabled";
212 };
213
214 usb1: usb@1b400000 {
215 compatible = "generic-ehci";
216 reg = <0x1b400000 0x1fc>;
217
218 interrupt-parent = <&intc3>;
219 interrupts = <2>;
220 resets = <&rst2 5>;
221 reset-names = "usb-host";
222
223 has-transaction-translator;
224 caps-offset = <0x100>;
225
226 phy-names = "usb-phy1";
227 phys = <&usb_phy1>;
228
229 status = "disabled";
230 };
231
232 spi: spi@1f000000 {
233 compatible = "qca,ar9557-spi", "qca,ar7100-spi";
234 reg = <0x1f000000 0x10>;
235
236 clocks = <&pll ATH79_CLK_AHB>;
237 clock-names = "ahb";
238
239 status = "disabled";
240
241 #address-cells = <1>;
242 #size-cells = <0>;
243 };
244 };
245 };
246
247 &mdio0 {
248 resets = <&rst 22>;
249 reset-names = "mdio";
250 };
251
252 &eth0 {
253 compatible = "qca,qca9550-eth", "syscon";
254
255 pll-data = <0x82000101 0x80000101 0x80001313>;
256 phy-mode = "rgmii";
257
258 resets = <&rst 9>;
259 reset-names = "mac";
260 };
261
262 &mdio1 {
263 resets = <&rst 23>;
264 reset-names = "mdio";
265 };
266
267 &eth1 {
268 compatible = "qca,qca9550-eth", "syscon";
269
270 pll-data = <0x82000101 0x80000101 0x80001313>;
271 phy-mode = "sgmii";
272
273 resets = <&rst 13>;
274 reset-names = "mac";
275 };