ath79: enable UART in SoC DTSI files
[openwrt/openwrt.git] / target / linux / ath79 / dts / qca9557_iodata_wn-ac-dgr.dtsi
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "qca955x.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7
8 / {
9 aliases {
10 led-boot = &led_power;
11 led-failsafe = &led_power;
12 led-running = &led_power;
13 led-upgrade = &led_power;
14 };
15
16 leds: leds {
17 compatible = "gpio-leds";
18
19 led_power: power {
20 label = "green:power";
21 gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
22 default-state = "on";
23 };
24
25 eco {
26 label = "green:eco";
27 gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
28 };
29
30 wlan5g {
31 label = "green:wlan5g";
32 gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
33 linux,default-trigger = "phy0tpt";
34 };
35
36 wlan2g {
37 label = "green:wlan2g";
38 gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
39 linux,default-trigger = "phy1tpt";
40 };
41
42 notification {
43 label = "amber:notification";
44 gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
45 };
46 };
47
48 keys: keys {
49 compatible = "gpio-keys";
50
51 eco {
52 label = "eco";
53 gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
54 linux,code = <BTN_1>;
55 debounce-interval = <60>;
56 };
57
58 auto {
59 label = "auto";
60 gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
61 linux,code = <BTN_0>;
62 linux,input-type = <EV_SW>;
63 debounce-interval = <60>;
64 };
65
66 wps {
67 label = "wps";
68 gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
69 linux,code = <KEY_WPS_BUTTON>;
70 debounce-interval = <60>;
71 };
72
73 reset {
74 label = "reset";
75 gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
76 linux,code = <KEY_RESTART>;
77 debounce-interval = <60>;
78 };
79
80 router {
81 label = "router";
82 gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
83 linux,code = <BTN_0>;
84 linux,input-type = <EV_SW>;
85 debounce-interval = <60>;
86 };
87 };
88 };
89
90 &spi {
91 status = "okay";
92
93 flash@0 {
94 compatible = "jedec,spi-nor";
95 reg = <0>;
96 spi-max-frequency = <25000000>;
97
98 partitions {
99 compatible = "fixed-partitions";
100 #address-cells = <1>;
101 #size-cells = <1>;
102
103 partition@0 {
104 label = "u-boot";
105 reg = <0x000000 0x030000>;
106 read-only;
107 };
108
109 partition@30000 {
110 label = "u-boot-env";
111 reg = <0x030000 0x010000>;
112 read-only;
113 };
114
115 partition@40000 {
116 compatible = "denx,uimage";
117 label = "firmware";
118 reg = <0x040000 0xe50000>;
119 };
120
121 partition@e90000 {
122 label = "manufacture";
123 reg = <0xe90000 0x100000>;
124 read-only;
125 };
126
127 partition@f90000 {
128 label = "backup";
129 reg = <0xf90000 0x010000>;
130 read-only;
131 };
132
133 partition@fa0000 {
134 label = "storage";
135 reg = <0xfa0000 0x050000>;
136 read-only;
137 };
138
139 art: partition@ff0000 {
140 label = "art";
141 reg = <0xff0000 0x010000>;
142 read-only;
143 };
144 };
145 };
146 };
147
148 &mdio0 {
149 status = "okay";
150
151 phy0: ethernet-phy@0 {
152 reg = <0>;
153
154 qca,ar8327-initvals = <
155 0x04 0x87600000 /* PORT0 PAD MODE CTRL */
156 0x7c 0x0000007e /* PORT0_STATUS */
157 >;
158 };
159 };
160
161 &eth0 {
162 status = "okay";
163
164 pll-data = <0xa6000000 0x00000101 0x00001616>;
165 phy-handle = <&phy0>;
166 };
167
168 &pcie1 {
169 status = "okay";
170
171 wifi@0,0 {
172 compatible = "pci168c,003c";
173 reg = <0x0000 0 0 0 0>;
174 };
175 };
176
177 &usb_phy0 {
178 status = "okay";
179 };
180
181 &usb0 {
182 status = "okay";
183 };
184
185 &wmac {
186 status = "okay";
187
188 qca,no-eeprom;
189 };