ath79: enable UART in SoC DTSI files
[openwrt/openwrt.git] / target / linux / ath79 / dts / qca9558_domywifi_dw33d.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "qca955x.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7
8 / {
9 compatible = "domywifi,dw33d", "qca,qca9558";
10 model = "DomyWifi DW33D";
11
12 aliases {
13 led-boot = &led_system;
14 led-failsafe = &led_system;
15 led-running = &led_system;
16 led-upgrade = &led_system;
17 };
18
19 leds {
20 compatible = "gpio-leds";
21
22 led_system: system {
23 label = "blue:system";
24 gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
25 };
26
27 mmc {
28 label = "blue:mmc";
29 gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
30 trigger-sources = <&hub_port0>;
31 linux,default-trigger = "usbport";
32 };
33
34 usb {
35 label = "blue:usb";
36 gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
37 trigger-sources = <&hub_port1>;
38 linux,default-trigger = "usbport";
39 };
40
41 wlan2g {
42 label = "blue:wlan2g";
43 gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
44 linux,default-trigger = "phy1tpt";
45 };
46
47 internet {
48 label = "blue:internet";
49 gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
50 };
51 };
52
53 keys {
54 compatible = "gpio-keys";
55
56 reset {
57 label = "Reset button";
58 linux,code = <KEY_RESTART>;
59 gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
60 debounce-interval = <60>;
61 };
62 };
63 };
64
65 &pcie0 {
66 status = "okay";
67
68 wifi@0,0 {
69 compatible = "qcom,ath10k";
70 reg = <0 0 0 0 0>;
71 };
72 };
73
74 &usb_phy0 {
75 status = "okay";
76 };
77
78 &usb0 {
79 #address-cells = <1>;
80 #size-cells = <0>;
81 status = "okay";
82
83 hub_port0: port@1 {
84 reg = <1>;
85 #trigger-source-cells = <0>;
86 };
87 };
88
89 &usb_phy1 {
90 status = "okay";
91 };
92
93 &usb1 {
94 #address-cells = <1>;
95 #size-cells = <0>;
96 status = "okay";
97
98 hub_port1: port@1 {
99 reg = <1>;
100 #trigger-source-cells = <0>;
101 };
102 };
103
104 &spi {
105 status = "okay";
106
107 flash@0 {
108 compatible = "jedec,spi-nor";
109 reg = <0>;
110 spi-max-frequency = <25000000>;
111
112 partitions {
113 compatible = "fixed-partitions";
114 #address-cells = <1>;
115 #size-cells = <1>;
116
117 partition@0 {
118 label = "u-boot";
119 reg = <0x0 0x40000>;
120 read-only;
121 };
122
123 partition@40000 {
124 label = "u-boot-env";
125 reg = <0x40000 0x10000>;
126 };
127
128 partition@50000 {
129 label = "oem-firmware";
130 reg = <0x50000 0xfa0000>;
131 };
132
133 art: partition@ff0000 {
134 label = "art";
135 reg = <0xff0000 0x10000>;
136 read-only;
137 };
138 };
139 };
140 };
141
142 &nand {
143 status = "okay";
144
145 partitions {
146 compatible = "fixed-partitions";
147 #address-cells = <1>;
148 #size-cells = <1>;
149
150 partition@0 {
151 label = "kernel";
152 reg = <0x0 0x500000>;
153 };
154
155 partition@500000 {
156 label = "ubi";
157 reg = <0x500000 0x5b00000>;
158 };
159
160 partition@6000000 {
161 label = "oem-backup";
162 reg = <0x6000000 0x2000000>;
163 };
164 };
165 };
166
167 &mdio0 {
168 status = "okay";
169
170 phy0: ethernet-phy@0 {
171 reg = <0>;
172
173 qca,ar8327-initvals = <
174 0x04 0x87600000 /* PORT0 PAD MODE CTRL */
175 0x0c 0x00080080 /* PORT6 PAD MODE CTRL */
176 0x7c 0x0000007e /* PORT0_STATUS */
177 0x94 0x0000007e /* PORT6 STATUS */
178 >;
179 };
180 };
181
182 &eth0 {
183 status = "okay";
184
185 mtd-mac-address = <&art 0x0>;
186 pll-data = <0x56000000 0x00000101 0x00001616>;
187 phy-handle = <&phy0>;
188 };
189
190 &eth1 {
191 status = "okay";
192
193 mtd-mac-address = <&art 0x6>;
194 pll-data = <0x03000101 0x00000101 0x00001616>;
195 fixed-link {
196 speed = <1000>;
197 full-duplex;
198 };
199 };
200
201 &wmac {
202 status = "okay";
203
204 mtd-cal-data = <&art 0x1000>;
205 mtd-mac-address = <&art 0xc>;
206 };