target/linux/ath79/dts/qca9558_openmesh_om5p-ac-v2.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 #include "qca955x.dtsi"
   4
   5 #include <dt-bindings/gpio/gpio.h>
   6 #include <dt-bindings/input/input.h>
   7
   8 / {
   9         compatible = "openmesh,om5p-ac-v2", "qca,qca9558";
  10         model = "OpenMesh OM5P-AC V2";
  11
  12         extosc: ref {
  13                 compatible = "fixed-clock";
  14                 #clock-cells = <0>;
  15                 clock-output-names = "ref";
  16                 clock-frequency = <40000000>;
  17         };
  18
  19         leds {
  20                 compatible = "gpio-leds";
  21
  22                 power {
  23                         label = "blue:power";
  24                         gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
  25                 };
  26
  27                 wifi_green {
  28                         label = "green:wifi";
  29                         gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
  30                 };
  31
  32                 wifi_yellow {
  33                         label = "yellow:wifi";
  34                         gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
  35                 };
  36
  37                 wifi_red {
  38                         label = "red:wifi";
  39                         gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
  40                 };
  41         };
  42
  43         keys {
  44                 compatible = "gpio-keys";
  45
  46                 reset {
  47                         label = "reset";
  48                         linux,code = <KEY_RESTART>;
  49                         gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
  50                 };
  51         };
  52
  53         gpio-export {
  54                 compatible = "gpio-export";
  55                 #size-cells = <0>;
  56
  57                 gpio_pa_dcdc {
  58                         gpio-export,name = "om5pac:pa_dcdc";
  59                         gpio-export,output = <1>;
  60                         gpios = <&gpio 2 GPIO_ACTIVE_HIGH>;
  61                 };
  62                 gpio_pa_high {
  63                         gpio-export,name = "om5pac:pa_high";
  64                         gpio-export,output = <1>;
  65                         gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
  66                 };
  67         };
  68 };
  69
  70 &pinmux {
  71         pinmux_pa_dcdc_pins {
  72                 pinctrl-single,bits = <0x0 0xff00 0x0>;
  73         };
  74
  75         pinmux_pa_high_pins {
  76                 pinctrl-single,bits = <0x10 0xff 0x0>;
  77         };
  78 };
  79
  80 &pcie0 {
  81         status = "okay";
  82 };
  83
  84 &pll {
  85         clocks = <&extosc>;
  86 };
  87
  88 &spi {
  89         status = "okay";
  90
  91         flash@0 {
  92                 compatible = "jedec,spi-nor";
  93                 reg = <0>;
  94                 spi-max-frequency = <25000000>;
  95
  96                 partitions {
  97                         compatible = "fixed-partitions";
  98                         #address-cells = <1>;
  99                         #size-cells = <1>;
 100
 101                         partition@0 {
 102                                 label = "u-boot";
 103                                 reg = <0x000000 0x040000>;
 104                                 read-only;
 105                         };
 106
 107                         partition@1 {
 108                                 label = "u-boot-env";
 109                                 reg = <0x040000 0x010000>;
 110                         };
 111
 112                         partition@2 {
 113                                 compatible = "denx,uimage";
 114                                 label = "firmware";
 115                                 reg = <0x850000 0x7a0000>;
 116                         };
 117
 118                         partition@3 {
 119                                 label = "art";
 120                                 reg = <0xff0000 0x010000>;
 121                                 read-only;
 122                         };
 123                 };
 124         };
 125 };
 126
 127 &mdio0 {
 128         status = "okay";
 129
 130         phy4: ethernet-phy@4 {
 131                 reg = <4>;
 132                 phy-mode = "rgmii-id";
 133         };
 134 };
 135
 136 &mdio1 {
 137         status = "okay";
 138
 139         phy1: ethernet-phy@1 {
 140                 reg = <1>;
 141                 phy-mode = "sgmii";
 142         };
 143 };
 144
 145 &eth0 {
 146         status = "okay";
 147
 148         pll-data = <0x82000101 0x80000101 0x80001313>;
 149
 150         phy-handle = <&phy4>;
 151 };
 152
 153 &eth1 {
 154         status = "okay";
 155
 156         pll-data = <0x03000101 0x80000101 0x80001313>;
 157
 158         phy-handle = <&phy1>;
 159 };