ath79: enable UART in SoC DTSI files
[openwrt/openwrt.git] / target / linux / ath79 / dts / qca9563_dlink_dir-859-a1.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "qca956x.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7
8 / {
9 model = "D-Link DIR-859 A1";
10 compatible = "dlink,dir-859-a1", "qca,qca9563";
11
12 aliases {
13 led-boot = &led_power;
14 led-failsafe = &led_power;
15 led-running = &led_power;
16 led-upgrade = &led_power;
17 };
18
19 leds {
20 compatible = "gpio-leds";
21
22 wps {
23 label = "green:wps";
24 gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
25 };
26
27 led_power: power {
28 label = "green:power";
29 gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
30 };
31
32 internet {
33 label = "green:internet";
34 gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
35 };
36
37 wlan {
38 label = "green:wlan";
39 gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
40 linux,default-trigger = "phy0tpt";
41 };
42 };
43
44 keys {
45 compatible = "gpio-keys";
46
47 wps {
48 linux,code = <KEY_WPS_BUTTON>;
49 gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
50 debounce-interval = <60>;
51 };
52
53 reset {
54 linux,code = <KEY_RESTART>;
55 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
56 debounce-interval = <60>;
57 };
58 };
59
60 gpio-export {
61 compatible = "gpio-export";
62 #size-cells = <0>;
63
64 gpio_switch_reset {
65 gpio-export,name = "dir-859-a1:reset:switch";
66 gpio-export,output = <1>;
67 gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
68 };
69 };
70 };
71
72 &pcie {
73 status = "okay";
74 };
75
76 &spi {
77 status = "okay";
78
79 flash@0 {
80 compatible = "jedec,spi-nor";
81 reg = <0>;
82 spi-max-frequency = <30000000>;
83
84 partitions {
85 compatible = "fixed-partitions";
86 #address-cells = <1>;
87 #size-cells = <1>;
88
89 partition@0 {
90 label = "bootloader";
91 reg = <0x000000 0x40000>;
92 read-only;
93 };
94
95 partition@40000 {
96 label = "bdcfg";
97 reg = <0x040000 0x10000>;
98 read-only;
99 };
100
101 partition@50000 {
102 label = "devdata";
103 reg = <0x050000 0x10000>;
104 read-only;
105 };
106
107 partition@60000 {
108 label = "devconf";
109 reg = <0x060000 0x10000>;
110 read-only;
111 };
112
113 partition@70000 {
114 compatible = "seama";
115 label = "firmware";
116 reg = <0x070000 0xf80000>;
117 };
118
119 art: partition@ff0000 {
120 label = "art";
121 reg = <0xff0000 0x010000>;
122 read-only;
123 };
124 };
125 };
126 };
127
128 &mdio0 {
129 status = "okay";
130
131 phy-mask = <0>;
132
133 phy0: ethernet-phy@0 {
134 reg = <0>;
135 phy-mode = "sgmii";
136 qca,mib-poll-interval = <500>;
137
138 qca,ar8327-initvals = <
139 0x04 0x00080080 /* PORT0 PAD MODE CTRL */
140 0x10 0x81000080 /* POWER_ON_STRAP */
141 0x50 0xcc35cc35 /* LED_CTRL0 */
142 0x54 0xcb37cb37 /* LED_CTRL1 */
143 0x58 0x00000000 /* LED_CTRL2 */
144 0x5c 0x00f3cf00 /* LED_CTRL3 */
145 0x7c 0x0000007e /* PORT0_STATUS */
146 >;
147 };
148 };
149
150 &eth0 {
151 status = "okay";
152
153 pll-data = <0x03000101 0x00000101 0x00001919>;
154
155 phy-mode = "sgmii";
156 phy-handle = <&phy0>;
157 };
158
159 &wmac {
160 status = "okay";
161
162 qca,no-eeprom;
163 };