projects / openwrt / openwrt.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
kernel: Update kernel 4.19 to version 4.19.131
[openwrt/openwrt.git] / target / linux / ath79 / files / drivers / mtd / nand / raw / ar934x_nand.c
1 /*
2 * Driver for the built-in NAND controller of the Atheros AR934x SoCs
3 *
4 * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11 #include <linux/version.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/module.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/mtd/mtd.h>
17 #include <linux/mtd/rawnand.h>
18 #include <linux/mtd/partitions.h>
19 #include <linux/platform_device.h>
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/of.h>
23 #include <linux/of_device.h>
24 #include <linux/reset.h>
25
26 #define AR934X_NFC_DRIVER_NAME "ar934x-nand"
27
28 #define AR934X_NFC_REG_CMD 0x00
29 #define AR934X_NFC_REG_CTRL 0x04
30 #define AR934X_NFC_REG_STATUS 0x08
31 #define AR934X_NFC_REG_INT_MASK 0x0c
32 #define AR934X_NFC_REG_INT_STATUS 0x10
33 #define AR934X_NFC_REG_ECC_CTRL 0x14
34 #define AR934X_NFC_REG_ECC_OFFSET 0x18
35 #define AR934X_NFC_REG_ADDR0_0 0x1c
36 #define AR934X_NFC_REG_ADDR0_1 0x24
37 #define AR934X_NFC_REG_ADDR1_0 0x20
38 #define AR934X_NFC_REG_ADDR1_1 0x28
39 #define AR934X_NFC_REG_SPARE_SIZE 0x30
40 #define AR934X_NFC_REG_PROTECT 0x38
41 #define AR934X_NFC_REG_LOOKUP_EN 0x40
42 #define AR934X_NFC_REG_LOOKUP(_x) (0x44 + (_i) * 4)
43 #define AR934X_NFC_REG_DMA_ADDR 0x64
44 #define AR934X_NFC_REG_DMA_COUNT 0x68
45 #define AR934X_NFC_REG_DMA_CTRL 0x6c
46 #define AR934X_NFC_REG_MEM_CTRL 0x80
47 #define AR934X_NFC_REG_DATA_SIZE 0x84
48 #define AR934X_NFC_REG_READ_STATUS 0x88
49 #define AR934X_NFC_REG_TIME_SEQ 0x8c
50 #define AR934X_NFC_REG_TIMINGS_ASYN 0x90
51 #define AR934X_NFC_REG_TIMINGS_SYN 0x94
52 #define AR934X_NFC_REG_FIFO_DATA 0x98
53 #define AR934X_NFC_REG_TIME_MODE 0x9c
54 #define AR934X_NFC_REG_DMA_ADDR_OFFS 0xa0
55 #define AR934X_NFC_REG_FIFO_INIT 0xb0
56 #define AR934X_NFC_REG_GEN_SEQ_CTRL 0xb4
57
58 #define AR934X_NFC_CMD_CMD_SEQ_S 0
59 #define AR934X_NFC_CMD_CMD_SEQ_M 0x3f
60 #define AR934X_NFC_CMD_SEQ_1C 0x00
61 #define AR934X_NFC_CMD_SEQ_ERASE 0x0e
62 #define AR934X_NFC_CMD_SEQ_12 0x0c
63 #define AR934X_NFC_CMD_SEQ_1C1AXR 0x21
64 #define AR934X_NFC_CMD_SEQ_S 0x24
65 #define AR934X_NFC_CMD_SEQ_1C3AXR 0x27
66 #define AR934X_NFC_CMD_SEQ_1C5A1CXR 0x2a
67 #define AR934X_NFC_CMD_SEQ_18 0x32
68 #define AR934X_NFC_CMD_INPUT_SEL_SIU 0
69 #define AR934X_NFC_CMD_INPUT_SEL_DMA BIT(6)
70 #define AR934X_NFC_CMD_ADDR_SEL_0 0
71 #define AR934X_NFC_CMD_ADDR_SEL_1 BIT(7)
72 #define AR934X_NFC_CMD_CMD0_S 8
73 #define AR934X_NFC_CMD_CMD0_M 0xff
74 #define AR934X_NFC_CMD_CMD1_S 16
75 #define AR934X_NFC_CMD_CMD1_M 0xff
76 #define AR934X_NFC_CMD_CMD2_S 24
77 #define AR934X_NFC_CMD_CMD2_M 0xff
78
79 #define AR934X_NFC_CTRL_ADDR_CYCLE0_M 0x7
80 #define AR934X_NFC_CTRL_ADDR_CYCLE0_S 0
81 #define AR934X_NFC_CTRL_SPARE_EN BIT(3)
82 #define AR934X_NFC_CTRL_INT_EN BIT(4)
83 #define AR934X_NFC_CTRL_ECC_EN BIT(5)
84 #define AR934X_NFC_CTRL_BLOCK_SIZE_S 6
85 #define AR934X_NFC_CTRL_BLOCK_SIZE_M 0x3
86 #define AR934X_NFC_CTRL_BLOCK_SIZE_32 0
87 #define AR934X_NFC_CTRL_BLOCK_SIZE_64 1
88 #define AR934X_NFC_CTRL_BLOCK_SIZE_128 2
89 #define AR934X_NFC_CTRL_BLOCK_SIZE_256 3
90 #define AR934X_NFC_CTRL_PAGE_SIZE_S 8
91 #define AR934X_NFC_CTRL_PAGE_SIZE_M 0x7
92 #define AR934X_NFC_CTRL_PAGE_SIZE_256 0
93 #define AR934X_NFC_CTRL_PAGE_SIZE_512 1
94 #define AR934X_NFC_CTRL_PAGE_SIZE_1024 2
95 #define AR934X_NFC_CTRL_PAGE_SIZE_2048 3
96 #define AR934X_NFC_CTRL_PAGE_SIZE_4096 4
97 #define AR934X_NFC_CTRL_PAGE_SIZE_8192 5
98 #define AR934X_NFC_CTRL_PAGE_SIZE_16384 6
99 #define AR934X_NFC_CTRL_CUSTOM_SIZE_EN BIT(11)
100 #define AR934X_NFC_CTRL_IO_WIDTH_8BITS 0
101 #define AR934X_NFC_CTRL_IO_WIDTH_16BITS BIT(12)
102 #define AR934X_NFC_CTRL_LOOKUP_EN BIT(13)
103 #define AR934X_NFC_CTRL_PROT_EN BIT(14)
104 #define AR934X_NFC_CTRL_WORK_MODE_ASYNC 0
105 #define AR934X_NFC_CTRL_WORK_MODE_SYNC BIT(15)
106 #define AR934X_NFC_CTRL_ADDR0_AUTO_INC BIT(16)
107 #define AR934X_NFC_CTRL_ADDR1_AUTO_INC BIT(17)
108 #define AR934X_NFC_CTRL_ADDR_CYCLE1_M 0x7
109 #define AR934X_NFC_CTRL_ADDR_CYCLE1_S 18
110 #define AR934X_NFC_CTRL_SMALL_PAGE BIT(21)
111
112 #define AR934X_NFC_DMA_CTRL_DMA_START BIT(7)
113 #define AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE 0
114 #define AR934X_NFC_DMA_CTRL_DMA_DIR_READ BIT(6)
115 #define AR934X_NFC_DMA_CTRL_DMA_MODE_SG BIT(5)
116 #define AR934X_NFC_DMA_CTRL_DMA_BURST_S 2
117 #define AR934X_NFC_DMA_CTRL_DMA_BURST_0 0
118 #define AR934X_NFC_DMA_CTRL_DMA_BURST_1 1
119 #define AR934X_NFC_DMA_CTRL_DMA_BURST_2 2
120 #define AR934X_NFC_DMA_CTRL_DMA_BURST_3 3
121 #define AR934X_NFC_DMA_CTRL_DMA_BURST_4 4
122 #define AR934X_NFC_DMA_CTRL_DMA_BURST_5 5
123 #define AR934X_NFC_DMA_CTRL_ERR_FLAG BIT(1)
124 #define AR934X_NFC_DMA_CTRL_DMA_READY BIT(0)
125
126 #define AR934X_NFC_INT_DEV_RDY(_x) BIT(4 + (_x))
127 #define AR934X_NFC_INT_CMD_END BIT(1)
128
129 #define AR934X_NFC_ECC_CTRL_ERR_THRES_S 8
130 #define AR934X_NFC_ECC_CTRL_ERR_THRES_M 0x1f
131 #define AR934X_NFC_ECC_CTRL_ECC_CAP_S 5
132 #define AR934X_NFC_ECC_CTRL_ECC_CAP_M 0x7
133 #define AR934X_NFC_ECC_CTRL_ECC_CAP_2 0
134 #define AR934X_NFC_ECC_CTRL_ECC_CAP_4 1
135 #define AR934X_NFC_ECC_CTRL_ECC_CAP_6 2
136 #define AR934X_NFC_ECC_CTRL_ECC_CAP_8 3
137 #define AR934X_NFC_ECC_CTRL_ECC_CAP_10 4
138 #define AR934X_NFC_ECC_CTRL_ECC_CAP_12 5
139 #define AR934X_NFC_ECC_CTRL_ECC_CAP_14 6
140 #define AR934X_NFC_ECC_CTRL_ECC_CAP_16 7
141 #define AR934X_NFC_ECC_CTRL_ERR_OVER BIT(2)
142 #define AR934X_NFC_ECC_CTRL_ERR_UNCORRECT BIT(1)
143 #define AR934X_NFC_ECC_CTRL_ERR_CORRECT BIT(0)
144
145 #define AR934X_NFC_ECC_OFFS_OFSET_M 0xffff
146
147 /* default timing values */
148 #define AR934X_NFC_TIME_SEQ_DEFAULT 0x7fff
149 #define AR934X_NFC_TIMINGS_ASYN_DEFAULT 0x22
150 #define AR934X_NFC_TIMINGS_SYN_DEFAULT 0xf
151
152 #define AR934X_NFC_ID_BUF_SIZE 8
153 #define AR934X_NFC_DEV_READY_TIMEOUT 25 /* msecs */
154 #define AR934X_NFC_DMA_READY_TIMEOUT 25 /* msecs */
155 #define AR934X_NFC_DONE_TIMEOUT 1000
156 #define AR934X_NFC_DMA_RETRIES 20
157
158 #define AR934X_NFC_USE_IRQ true
159 #define AR934X_NFC_IRQ_MASK AR934X_NFC_INT_DEV_RDY(0)
160
161 #define AR934X_NFC_GENSEQ_SMALL_PAGE_READ 0x30043
162
163 #undef AR934X_NFC_DEBUG_DATA
164 #undef AR934X_NFC_DEBUG
165
166 struct mtd_info;
167 struct mtd_partition;
168 struct ar934x_nfc;
169
170 struct ar934x_nfc {
171 struct nand_chip nand_chip;
172 struct device *parent;
173 void __iomem *base;
174 bool swap_dma;
175 int irq;
176 wait_queue_head_t irq_waitq;
177
178 bool spurious_irq_expected;
179 u32 irq_status;
180
181 u32 ctrl_reg;
182 u32 ecc_ctrl_reg;
183 u32 ecc_offset_reg;
184 u32 ecc_thres;
185 u32 ecc_oob_pos;
186
187 bool small_page;
188 unsigned int addr_count0;
189 unsigned int addr_count1;
190
191 u8 *buf;
192 dma_addr_t buf_dma;
193 unsigned int buf_size;
194 int buf_index;
195
196 bool read_id;
197
198 int erase1_page_addr;
199
200 int rndout_page_addr;
201 int rndout_read_cmd;
202
203 int seqin_page_addr;
204 int seqin_column;
205 int seqin_read_cmd;
206
207 struct reset_control *rst;
208 };
209
210 static inline __printf(2, 3)
211 void _nfc_dbg(struct ar934x_nfc *nfc, const char *fmt, ...)
212 {
213 }
214
215 #ifdef AR934X_NFC_DEBUG
216 #define nfc_dbg(_nfc, fmt, ...) \
217 dev_info((_nfc)->parent, fmt, ##__VA_ARGS__)
218 #else
219 #define nfc_dbg(_nfc, fmt, ...) \
220 _nfc_dbg((_nfc), fmt, ##__VA_ARGS__)
221 #endif /* AR934X_NFC_DEBUG */
222
223 #ifdef AR934X_NFC_DEBUG_DATA
224 static void nfc_debug_data(const char *label, void *data, int len)
225 {
226 print_hex_dump(KERN_WARNING, label, DUMP_PREFIX_OFFSET, 16, 1,
227 data, len, 0);
228 }
229 #else
230 static inline void nfc_debug_data(const char *label, void *data, int len) {}
231 #endif /* AR934X_NFC_DEBUG_DATA */
232
233 static void ar934x_nfc_restart(struct ar934x_nfc *nfc);
234
235 static inline bool is_all_ff(u8 *buf, int len)
236 {
237 while (len--)
238 if (buf[len] != 0xff)
239 return false;
240
241 return true;
242 }
243
244 static inline void ar934x_nfc_wr(struct ar934x_nfc *nfc, unsigned reg, u32 val)
245 {
246 __raw_writel(val, nfc->base + reg);
247 }
248
249 static inline u32 ar934x_nfc_rr(struct ar934x_nfc *nfc, unsigned reg)
250 {
251 return __raw_readl(nfc->base + reg);
252 }
253
254 static inline struct ar934x_nfc *mtd_to_ar934x_nfc(struct mtd_info *mtd)
255 {
256 struct nand_chip *chip = mtd_to_nand(mtd);
257
258 return container_of(chip, struct ar934x_nfc, nand_chip);
259 }
260
261 static struct mtd_info *ar934x_nfc_to_mtd(struct ar934x_nfc *nfc)
262 {
263 return nand_to_mtd(&nfc->nand_chip);
264 }
265
266 static inline bool ar934x_nfc_use_irq(struct ar934x_nfc *nfc)
267 {
268 return AR934X_NFC_USE_IRQ;
269 }
270
271 static inline void ar934x_nfc_write_cmd_reg(struct ar934x_nfc *nfc, u32 cmd_reg)
272 {
273 wmb();
274
275 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CMD, cmd_reg);
276 /* flush write */
277 ar934x_nfc_rr(nfc, AR934X_NFC_REG_CMD);
278 }
279
280 static bool __ar934x_nfc_dev_ready(struct ar934x_nfc *nfc)
281 {
282 u32 status;
283
284 status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_STATUS);
285 return (status & 0xff) == 0xff;
286 }
287
288 static inline bool __ar934x_nfc_is_dma_ready(struct ar934x_nfc *nfc)
289 {
290 u32 status;
291
292 status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_DMA_CTRL);
293 return (status & AR934X_NFC_DMA_CTRL_DMA_READY) != 0;
294 }
295
296 static int ar934x_nfc_wait_dev_ready(struct ar934x_nfc *nfc)
297 {
298 unsigned long timeout;
299
300 timeout = jiffies + msecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT);
301 do {
302 if (__ar934x_nfc_dev_ready(nfc))
303 return 0;
304 } while time_before(jiffies, timeout);
305
306 nfc_dbg(nfc, "timeout waiting for device ready, status:%08x int:%08x\n",
307 ar934x_nfc_rr(nfc, AR934X_NFC_REG_STATUS),
308 ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS));
309 return -ETIMEDOUT;
310 }
311
312 static int ar934x_nfc_wait_dma_ready(struct ar934x_nfc *nfc)
313 {
314 unsigned long timeout;
315
316 timeout = jiffies + msecs_to_jiffies(AR934X_NFC_DMA_READY_TIMEOUT);
317 do {
318 if (__ar934x_nfc_is_dma_ready(nfc))
319 return 0;
320 } while time_before(jiffies, timeout);
321
322 nfc_dbg(nfc, "timeout waiting for DMA ready, dma_ctrl:%08x\n",
323 ar934x_nfc_rr(nfc, AR934X_NFC_REG_DMA_CTRL));
324 return -ETIMEDOUT;
325 }
326
327 static int ar934x_nfc_wait_irq(struct ar934x_nfc *nfc)
328 {
329 long timeout;
330 int ret;
331
332 timeout = wait_event_timeout(nfc->irq_waitq,
333 (nfc->irq_status & AR934X_NFC_IRQ_MASK) != 0,
334 msecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT));
335
336 ret = 0;
337 if (!timeout) {
338 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_MASK, 0);
339 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
340 /* flush write */
341 ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS);
342
343 nfc_dbg(nfc,
344 "timeout waiting for interrupt, status:%08x\n",
345 nfc->irq_status);
346 ret = -ETIMEDOUT;
347 }
348
349 nfc->irq_status = 0;
350 return ret;
351 }
352
353 static int ar934x_nfc_wait_done(struct ar934x_nfc *nfc)
354 {
355 int ret;
356
357 if (ar934x_nfc_use_irq(nfc))
358 ret = ar934x_nfc_wait_irq(nfc);
359 else
360 ret = ar934x_nfc_wait_dev_ready(nfc);
361
362 if (ret)
363 return ret;
364
365 return ar934x_nfc_wait_dma_ready(nfc);
366 }
367
368 static int ar934x_nfc_alloc_buf(struct ar934x_nfc *nfc, unsigned size)
369 {
370 nfc->buf = dma_alloc_coherent(nfc->parent, size,
371 &nfc->buf_dma, GFP_KERNEL);
372 if (nfc->buf == NULL) {
373 dev_err(nfc->parent, "no memory for DMA buffer\n");
374 return -ENOMEM;
375 }
376
377 nfc->buf_size = size;
378 nfc_dbg(nfc, "buf:%p size:%u\n", nfc->buf, nfc->buf_size);
379
380 return 0;
381 }
382
383 static void ar934x_nfc_free_buf(struct ar934x_nfc *nfc)
384 {
385 dma_free_coherent(nfc->parent, nfc->buf_size, nfc->buf, nfc->buf_dma);
386 }
387
388 static void ar934x_nfc_get_addr(struct ar934x_nfc *nfc, int column,
389 int page_addr, u32 *addr0, u32 *addr1)
390 {
391 u32 a0, a1;
392
393 a0 = 0;
394 a1 = 0;
395
396 if (column == -1) {
397 /* ERASE1 */
398 a0 = (page_addr & 0xffff) << 16;
399 a1 = (page_addr >> 16) & 0xf;
400 } else if (page_addr != -1) {
401 /* SEQIN, READ0, etc.. */
402
403 /* TODO: handle 16bit bus width */
404 if (nfc->small_page) {
405 a0 = column & 0xff;
406 a0 |= (page_addr & 0xff) << 8;
407 a0 |= ((page_addr >> 8) & 0xff) << 16;
408 a0 |= ((page_addr >> 16) & 0xff) << 24;
409 } else {
410 a0 = column & 0x0FFF;
411 a0 |= (page_addr & 0xffff) << 16;
412
413 if (nfc->addr_count0 > 4)
414 a1 = (page_addr >> 16) & 0xf;
415 }
416 }
417
418 *addr0 = a0;
419 *addr1 = a1;
420 }
421
422 static void ar934x_nfc_send_cmd(struct ar934x_nfc *nfc, unsigned command)
423 {
424 u32 cmd_reg;
425
426 cmd_reg = AR934X_NFC_CMD_INPUT_SEL_SIU | AR934X_NFC_CMD_ADDR_SEL_0 |
427 AR934X_NFC_CMD_SEQ_1C;
428 cmd_reg |= (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S;
429
430 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
431 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
432
433 ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
434 ar934x_nfc_wait_dev_ready(nfc);
435 }
436
437 static int ar934x_nfc_do_rw_command(struct ar934x_nfc *nfc, int column,
438 int page_addr, int len, u32 cmd_reg,
439 u32 ctrl_reg, bool write)
440 {
441 u32 addr0, addr1;
442 u32 dma_ctrl;
443 int dir;
444 int err;
445 int retries = 0;
446
447 WARN_ON(len & 3);
448
449 if (WARN_ON(len > nfc->buf_size))
450 dev_err(nfc->parent, "len=%d > buf_size=%d", len,
451 nfc->buf_size);
452
453 if (write) {
454 dma_ctrl = AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE;
455 dir = DMA_TO_DEVICE;
456 } else {
457 dma_ctrl = AR934X_NFC_DMA_CTRL_DMA_DIR_READ;
458 dir = DMA_FROM_DEVICE;
459 }
460
461 ar934x_nfc_get_addr(nfc, column, page_addr, &addr0, &addr1);
462
463 dma_ctrl |= AR934X_NFC_DMA_CTRL_DMA_START |
464 (AR934X_NFC_DMA_CTRL_DMA_BURST_3 <<
465 AR934X_NFC_DMA_CTRL_DMA_BURST_S);
466
467 cmd_reg |= AR934X_NFC_CMD_INPUT_SEL_DMA | AR934X_NFC_CMD_ADDR_SEL_0;
468 ctrl_reg |= AR934X_NFC_CTRL_INT_EN;
469
470 nfc_dbg(nfc, "%s a0:%08x a1:%08x len:%x cmd:%08x dma:%08x ctrl:%08x\n",
471 (write) ? "write" : "read",
472 addr0, addr1, len, cmd_reg, dma_ctrl, ctrl_reg);
473
474 retry:
475 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
476 ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_0, addr0);
477 ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_1, addr1);
478 ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_ADDR, nfc->buf_dma);
479 ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_COUNT, len);
480 ar934x_nfc_wr(nfc, AR934X_NFC_REG_DATA_SIZE, len);
481 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, ctrl_reg);
482 ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_CTRL, dma_ctrl);
483 ar934x_nfc_wr(nfc, AR934X_NFC_REG_ECC_CTRL, nfc->ecc_ctrl_reg);
484 ar934x_nfc_wr(nfc, AR934X_NFC_REG_ECC_OFFSET, nfc->ecc_offset_reg);
485
486 if (ar934x_nfc_use_irq(nfc)) {
487 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_MASK,
488 AR934X_NFC_IRQ_MASK);
489 /* flush write */
490 ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_MASK);
491 }
492
493 ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
494 err = ar934x_nfc_wait_done(nfc);
495 if (err) {
496 dev_dbg(nfc->parent, "%s operation stuck at page %d\n",
497 (write) ? "write" : "read", page_addr);
498
499 ar934x_nfc_restart(nfc);
500 if (retries++ < AR934X_NFC_DMA_RETRIES)
501 goto retry;
502
503 dev_err(nfc->parent, "%s operation failed on page %d\n",
504 (write) ? "write" : "read", page_addr);
505 }
506
507 return err;
508 }
509
510 static int ar934x_nfc_send_readid(struct ar934x_nfc *nfc, unsigned command)
511 {
512 u32 cmd_reg;
513 int err;
514
515 nfc_dbg(nfc, "readid, cmd:%02x\n", command);
516
517 cmd_reg = AR934X_NFC_CMD_SEQ_1C1AXR;
518 cmd_reg |= (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S;
519
520 err = ar934x_nfc_do_rw_command(nfc, -1, -1, AR934X_NFC_ID_BUF_SIZE,
521 cmd_reg, nfc->ctrl_reg, false);
522
523 nfc_debug_data("[id] ", nfc->buf, AR934X_NFC_ID_BUF_SIZE);
524
525 return err;
526 }
527
528 static int ar934x_nfc_send_read(struct ar934x_nfc *nfc, unsigned command,
529 int column, int page_addr, int len)
530 {
531 u32 cmd_reg;
532 int err;
533
534 nfc_dbg(nfc, "read, column=%d page=%d len=%d\n",
535 column, page_addr, len);
536
537 cmd_reg = (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S;
538
539 if (nfc->small_page) {
540 cmd_reg |= AR934X_NFC_CMD_SEQ_18;
541 } else {
542 cmd_reg |= NAND_CMD_READSTART << AR934X_NFC_CMD_CMD1_S;
543 cmd_reg |= AR934X_NFC_CMD_SEQ_1C5A1CXR;
544 }
545
546 err = ar934x_nfc_do_rw_command(nfc, column, page_addr, len,
547 cmd_reg, nfc->ctrl_reg, false);
548
549 nfc_debug_data("[data] ", nfc->buf, len);
550
551 return err;
552 }
553
554 static void ar934x_nfc_send_erase(struct ar934x_nfc *nfc, unsigned command,
555 int column, int page_addr)
556 {
557 u32 addr0, addr1;
558 u32 ctrl_reg;
559 u32 cmd_reg;
560
561 ar934x_nfc_get_addr(nfc, column, page_addr, &addr0, &addr1);
562
563 ctrl_reg = nfc->ctrl_reg;
564 if (nfc->small_page) {
565 /* override number of address cycles for the erase command */
566 ctrl_reg &= ~(AR934X_NFC_CTRL_ADDR_CYCLE0_M <<
567 AR934X_NFC_CTRL_ADDR_CYCLE0_S);
568 ctrl_reg &= ~(AR934X_NFC_CTRL_ADDR_CYCLE1_M <<
569 AR934X_NFC_CTRL_ADDR_CYCLE1_S);
570 ctrl_reg &= ~(AR934X_NFC_CTRL_SMALL_PAGE);
571 ctrl_reg |= (nfc->addr_count0 + 1) <<
572 AR934X_NFC_CTRL_ADDR_CYCLE0_S;
573 }
574
575 cmd_reg = NAND_CMD_ERASE1 << AR934X_NFC_CMD_CMD0_S;
576 cmd_reg |= command << AR934X_NFC_CMD_CMD1_S;
577 cmd_reg |= AR934X_NFC_CMD_SEQ_ERASE;
578
579 nfc_dbg(nfc, "erase page %d, a0:%08x a1:%08x cmd:%08x ctrl:%08x\n",
580 page_addr, addr0, addr1, cmd_reg, ctrl_reg);
581
582 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
583 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, ctrl_reg);
584 ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_0, addr0);
585 ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_1, addr1);
586
587 ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
588 ar934x_nfc_wait_dev_ready(nfc);
589 }
590
591 static int ar934x_nfc_send_write(struct ar934x_nfc *nfc, unsigned command,
592 int column, int page_addr, int len)
593 {
594 u32 cmd_reg;
595
596 nfc_dbg(nfc, "write, column=%d page=%d len=%d\n",
597 column, page_addr, len);
598
599 nfc_debug_data("[data] ", nfc->buf, len);
600
601 cmd_reg = NAND_CMD_SEQIN << AR934X_NFC_CMD_CMD0_S;
602 cmd_reg |= command << AR934X_NFC_CMD_CMD1_S;
603 cmd_reg |= AR934X_NFC_CMD_SEQ_12;
604
605 return ar934x_nfc_do_rw_command(nfc, column, page_addr, len,
606 cmd_reg, nfc->ctrl_reg, true);
607 }
608
609 static void ar934x_nfc_read_status(struct ar934x_nfc *nfc)
610 {
611 u32 cmd_reg;
612 u32 status;
613
614 cmd_reg = NAND_CMD_STATUS << AR934X_NFC_CMD_CMD0_S;
615 cmd_reg |= AR934X_NFC_CMD_SEQ_S;
616
617 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
618 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
619
620 ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
621 ar934x_nfc_wait_dev_ready(nfc);
622
623 status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_READ_STATUS);
624
625 nfc_dbg(nfc, "read status, cmd:%08x status:%02x\n",
626 cmd_reg, (status & 0xff));
627
628 if (nfc->swap_dma)
629 nfc->buf[0 ^ 3] = status;
630 else
631 nfc->buf[0] = status;
632 }
633
634 #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
635 static void ar934x_nfc_cmdfunc(struct mtd_info *mtd, unsigned int command,
636 int column, int page_addr)
637 {
638 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
639 struct nand_chip *nand = &nfc->nand_chip;
640 #else
641 static void ar934x_nfc_cmdfunc(struct nand_chip *nand, unsigned int command,
642 int column, int page_addr)
643 {
644 struct mtd_info *mtd = nand_to_mtd(nand);
645 struct ar934x_nfc *nfc = nand->priv;
646 #endif
647
648 nfc->read_id = false;
649 if (command != NAND_CMD_PAGEPROG)
650 nfc->buf_index = 0;
651
652 switch (command) {
653 case NAND_CMD_RESET:
654 ar934x_nfc_send_cmd(nfc, command);
655 break;
656
657 case NAND_CMD_READID:
658 nfc->read_id = true;
659 ar934x_nfc_send_readid(nfc, command);
660 break;
661
662 case NAND_CMD_READ0:
663 case NAND_CMD_READ1:
664 if (nfc->small_page) {
665 ar934x_nfc_send_read(nfc, command, column, page_addr,
666 mtd->writesize + mtd->oobsize);
667 } else {
668 ar934x_nfc_send_read(nfc, command, 0, page_addr,
669 mtd->writesize + mtd->oobsize);
670 nfc->buf_index = column;
671 nfc->rndout_page_addr = page_addr;
672 nfc->rndout_read_cmd = command;
673 }
674 break;
675
676 case NAND_CMD_READOOB:
677 if (nfc->small_page)
678 ar934x_nfc_send_read(nfc, NAND_CMD_READOOB,
679 column, page_addr,
680 mtd->oobsize);
681 else
682 ar934x_nfc_send_read(nfc, NAND_CMD_READ0,
683 mtd->writesize, page_addr,
684 mtd->oobsize);
685 break;
686
687 case NAND_CMD_RNDOUT:
688 if (WARN_ON(nfc->small_page))
689 break;
690
691 /* emulate subpage read */
692 ar934x_nfc_send_read(nfc, nfc->rndout_read_cmd, 0,
693 nfc->rndout_page_addr,
694 mtd->writesize + mtd->oobsize);
695 nfc->buf_index = column;
696 break;
697
698 case NAND_CMD_ERASE1:
699 nfc->erase1_page_addr = page_addr;
700 break;
701
702 case NAND_CMD_ERASE2:
703 ar934x_nfc_send_erase(nfc, command, -1, nfc->erase1_page_addr);
704 break;
705
706 case NAND_CMD_STATUS:
707 ar934x_nfc_read_status(nfc);
708 break;
709
710 case NAND_CMD_SEQIN:
711 if (nfc->small_page) {
712 /* output read command */
713 if (column >= mtd->writesize) {
714 column -= mtd->writesize;
715 nfc->seqin_read_cmd = NAND_CMD_READOOB;
716 } else if (column < 256) {
717 nfc->seqin_read_cmd = NAND_CMD_READ0;
718 } else {
719 column -= 256;
720 nfc->seqin_read_cmd = NAND_CMD_READ1;
721 }
722 } else {
723 nfc->seqin_read_cmd = NAND_CMD_READ0;
724 }
725 nfc->seqin_column = column;
726 nfc->seqin_page_addr = page_addr;
727 break;
728
729 case NAND_CMD_PAGEPROG:
730 if (nand->ecc.mode == NAND_ECC_HW) {
731 /* the data is already written */
732 break;
733 }
734
735 if (nfc->small_page)
736 ar934x_nfc_send_cmd(nfc, nfc->seqin_read_cmd);
737
738 ar934x_nfc_send_write(nfc, command, nfc->seqin_column,
739 nfc->seqin_page_addr,
740 nfc->buf_index);
741 break;
742
743 default:
744 dev_err(nfc->parent,
745 "unsupported command: %x, column:%d page_addr=%d\n",
746 command, column, page_addr);
747 break;
748 }
749 }
750
751 #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
752 static int ar934x_nfc_dev_ready(struct mtd_info *mtd)
753 {
754 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
755 #else
756 static int ar934x_nfc_dev_ready(struct nand_chip *chip)
757 {
758 struct ar934x_nfc *nfc = chip->priv;
759 #endif
760
761 return __ar934x_nfc_dev_ready(nfc);
762 }
763
764 #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
765 static u8 ar934x_nfc_read_byte(struct mtd_info *mtd)
766 {
767 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
768 #else
769 static u8 ar934x_nfc_read_byte(struct nand_chip *chip)
770 {
771 struct ar934x_nfc *nfc = chip->priv;
772 #endif
773 u8 data;
774
775 WARN_ON(nfc->buf_index >= nfc->buf_size);
776
777 if (nfc->swap_dma || nfc->read_id)
778 data = nfc->buf[nfc->buf_index ^ 3];
779 else
780 data = nfc->buf[nfc->buf_index];
781
782 nfc->buf_index++;
783
784 return data;
785 }
786
787 #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
788 static void ar934x_nfc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
789 {
790 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
791 #else
792 static void ar934x_nfc_write_buf(struct nand_chip *chip, const u8 *buf, int len)
793 {
794 struct ar934x_nfc *nfc = chip->priv;
795 #endif
796 int i;
797
798 WARN_ON(nfc->buf_index + len > nfc->buf_size);
799
800 if (nfc->swap_dma) {
801 for (i = 0; i < len; i++) {
802 nfc->buf[nfc->buf_index ^ 3] = buf[i];
803 nfc->buf_index++;
804 }
805 } else {
806 for (i = 0; i < len; i++) {
807 nfc->buf[nfc->buf_index] = buf[i];
808 nfc->buf_index++;
809 }
810 }
811 }
812
813 #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
814 static void ar934x_nfc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
815 {
816 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
817 #else
818 static void ar934x_nfc_read_buf(struct nand_chip *chip, u8 *buf, int len)
819 {
820 struct ar934x_nfc *nfc = chip->priv;
821 #endif
822 int buf_index;
823 int i;
824
825 WARN_ON(nfc->buf_index + len > nfc->buf_size);
826
827 buf_index = nfc->buf_index;
828
829 if (nfc->swap_dma || nfc->read_id) {
830 for (i = 0; i < len; i++) {
831 buf[i] = nfc->buf[buf_index ^ 3];
832 buf_index++;
833 }
834 } else {
835 for (i = 0; i < len; i++) {
836 buf[i] = nfc->buf[buf_index];
837 buf_index++;
838 }
839 }
840
841 nfc->buf_index = buf_index;
842 }
843
844 static inline void ar934x_nfc_enable_hwecc(struct ar934x_nfc *nfc)
845 {
846 nfc->ctrl_reg |= AR934X_NFC_CTRL_ECC_EN;
847 nfc->ctrl_reg &= ~AR934X_NFC_CTRL_CUSTOM_SIZE_EN;
848 }
849
850 static inline void ar934x_nfc_disable_hwecc(struct ar934x_nfc *nfc)
851 {
852 nfc->ctrl_reg &= ~AR934X_NFC_CTRL_ECC_EN;
853 nfc->ctrl_reg |= AR934X_NFC_CTRL_CUSTOM_SIZE_EN;
854 }
855
856 #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
857 static int ar934x_nfc_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
858 int page)
859 {
860 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
861 #else
862 static int ar934x_nfc_read_oob(struct nand_chip *chip,
863 int page)
864 {
865 struct ar934x_nfc *nfc = chip->priv;
866 struct mtd_info *mtd = ar934x_nfc_to_mtd(nfc);
867 #endif
868 int err;
869
870 nfc_dbg(nfc, "read_oob: page:%d\n", page);
871
872 err = ar934x_nfc_send_read(nfc, NAND_CMD_READ0, mtd->writesize, page,
873 mtd->oobsize);
874 if (err)
875 return err;
876
877 memcpy(chip->oob_poi, nfc->buf, mtd->oobsize);
878
879 return 0;
880 }
881
882 #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
883 static int ar934x_nfc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
884 int page)
885 {
886 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
887 #else
888 static int ar934x_nfc_write_oob(struct nand_chip *chip,
889 int page)
890 {
891 struct ar934x_nfc *nfc = chip->priv;
892 struct mtd_info *mtd = ar934x_nfc_to_mtd(nfc);
893 #endif
894 nfc_dbg(nfc, "write_oob: page:%d\n", page);
895
896 memcpy(nfc->buf, chip->oob_poi, mtd->oobsize);
897
898 return ar934x_nfc_send_write(nfc, NAND_CMD_PAGEPROG, mtd->writesize,
899 page, mtd->oobsize);
900 }
901
902 #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
903 static int ar934x_nfc_read_page_raw(struct mtd_info *mtd,
904 struct nand_chip *chip, u8 *buf,
905 int oob_required, int page)
906 {
907 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
908 #else
909 static int ar934x_nfc_read_page_raw(
910 struct nand_chip *chip, u8 *buf,
911 int oob_required, int page)
912 {
913 struct ar934x_nfc *nfc = chip->priv;
914 struct mtd_info *mtd = ar934x_nfc_to_mtd(nfc);
915 #endif
916 int len;
917 int err;
918
919 nfc_dbg(nfc, "read_page_raw: page:%d oob:%d\n", page, oob_required);
920
921 len = mtd->writesize;
922 if (oob_required)
923 len += mtd->oobsize;
924
925 err = ar934x_nfc_send_read(nfc, NAND_CMD_READ0, 0, page, len);
926 if (err)
927 return err;
928
929 memcpy(buf, nfc->buf, mtd->writesize);
930
931 if (oob_required)
932 memcpy(chip->oob_poi, &nfc->buf[mtd->writesize], mtd->oobsize);
933
934 return 0;
935 }
936
937 #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
938 static int ar934x_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
939 u8 *buf, int oob_required, int page)
940 {
941 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
942 #else
943 static int ar934x_nfc_read_page(struct nand_chip *chip,
944 u8 *buf, int oob_required, int page)
945 {
946 struct ar934x_nfc *nfc = chip->priv;
947 struct mtd_info *mtd = ar934x_nfc_to_mtd(nfc);
948 #endif
949 u32 ecc_ctrl;
950 int max_bitflips = 0;
951 bool ecc_failed;
952 bool ecc_corrected;
953 int err;
954
955 nfc_dbg(nfc, "read_page: page:%d oob:%d\n", page, oob_required);
956
957 ar934x_nfc_enable_hwecc(nfc);
958 err = ar934x_nfc_send_read(nfc, NAND_CMD_READ0, 0, page,
959 mtd->writesize);
960 ar934x_nfc_disable_hwecc(nfc);
961
962 if (err)
963 return err;
964
965 /* TODO: optimize to avoid memcpy */
966 memcpy(buf, nfc->buf, mtd->writesize);
967
968 /* read the ECC status */
969 ecc_ctrl = ar934x_nfc_rr(nfc, AR934X_NFC_REG_ECC_CTRL);
970 ecc_failed = ecc_ctrl & AR934X_NFC_ECC_CTRL_ERR_UNCORRECT;
971 ecc_corrected = ecc_ctrl & AR934X_NFC_ECC_CTRL_ERR_CORRECT;
972
973 if (oob_required || ecc_failed) {
974 err = ar934x_nfc_send_read(nfc, NAND_CMD_READ0, mtd->writesize,
975 page, mtd->oobsize);
976 if (err)
977 return err;
978
979 if (oob_required)
980 memcpy(chip->oob_poi, nfc->buf, mtd->oobsize);
981 }
982
983 if (ecc_failed) {
984 /*
985 * The hardware ECC engine reports uncorrectable errors
986 * on empty pages. Check the ECC bytes and the data. If
987 * both contains 0xff bytes only, dont report a failure.
988 *
989 * TODO: prebuild a buffer with 0xff bytes and use memcmp
990 * for better performance?
991 */
992 if (!is_all_ff(&nfc->buf[nfc->ecc_oob_pos], chip->ecc.total) ||
993 !is_all_ff(buf, mtd->writesize))
994 mtd->ecc_stats.failed++;
995 } else if (ecc_corrected) {
996 /*
997 * The hardware does not report the exact count of the
998 * corrected bitflips, use assumptions based on the
999 * threshold.
1000 */
1001 if (ecc_ctrl & AR934X_NFC_ECC_CTRL_ERR_OVER) {
1002 /*
1003 * The number of corrected bitflips exceeds the
1004 * threshold. Assume the maximum.
1005 */
1006 max_bitflips = chip->ecc.strength * chip->ecc.steps;
1007 } else {
1008 max_bitflips = nfc->ecc_thres * chip->ecc.steps;
1009 }
1010
1011 mtd->ecc_stats.corrected += max_bitflips;
1012 }
1013
1014 return max_bitflips;
1015 }
1016
1017 #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
1018 static int ar934x_nfc_write_page_raw(struct mtd_info *mtd,
1019 struct nand_chip *chip, const u8 *buf,
1020 int oob_required, int page)
1021 {
1022 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
1023 #else
1024 static int ar934x_nfc_write_page_raw(
1025 struct nand_chip *chip, const u8 *buf,
1026 int oob_required, int page)
1027 {
1028 struct ar934x_nfc *nfc = chip->priv;
1029 struct mtd_info *mtd = ar934x_nfc_to_mtd(nfc);
1030 #endif
1031 int len;
1032
1033 nfc_dbg(nfc, "write_page_raw: page:%d oob:%d\n", page, oob_required);
1034
1035 memcpy(nfc->buf, buf, mtd->writesize);
1036 len = mtd->writesize;
1037
1038 if (oob_required) {
1039 memcpy(&nfc->buf[mtd->writesize], chip->oob_poi, mtd->oobsize);
1040 len += mtd->oobsize;
1041 }
1042
1043 return ar934x_nfc_send_write(nfc, NAND_CMD_PAGEPROG, 0, page, len);
1044 }
1045
1046 #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
1047 static int ar934x_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1048 const u8 *buf, int oob_required, int page)
1049 {
1050 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
1051 #else
1052 static int ar934x_nfc_write_page(struct nand_chip *chip,
1053 const u8 *buf, int oob_required, int page)
1054 {
1055 struct ar934x_nfc *nfc = chip->priv;
1056 struct mtd_info *mtd = ar934x_nfc_to_mtd(nfc);
1057 #endif
1058 int err;
1059
1060 nfc_dbg(nfc, "write_page: page:%d oob:%d\n", page, oob_required);
1061
1062 /* write OOB first */
1063 if (oob_required &&
1064 !is_all_ff(chip->oob_poi, mtd->oobsize)) {
1065 #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
1066 err = ar934x_nfc_write_oob(mtd, chip, page);
1067 #else
1068 err = ar934x_nfc_write_oob(chip, page);
1069 #endif
1070 if (err)
1071 return err;
1072 }
1073
1074 /* TODO: optimize to avoid memcopy */
1075 memcpy(nfc->buf, buf, mtd->writesize);
1076
1077 ar934x_nfc_enable_hwecc(nfc);
1078 err = ar934x_nfc_send_write(nfc, NAND_CMD_PAGEPROG, 0, page,
1079 mtd->writesize);
1080 ar934x_nfc_disable_hwecc(nfc);
1081
1082 return err;
1083 }
1084
1085 static int ar934x_nfc_hw_reset_assert(struct ar934x_nfc *nfc)
1086 {
1087 int err;
1088
1089 err = reset_control_assert(nfc->rst);
1090 udelay(250);
1091 return err;
1092 }
1093
1094 static int ar934x_nfc_hw_reset_deassert(struct ar934x_nfc *nfc)
1095 {
1096 int err;
1097
1098 err = reset_control_deassert(nfc->rst);
1099 udelay(250);
1100 return err;
1101 }
1102
1103 static int ar934x_nfc_hw_init(struct ar934x_nfc *nfc)
1104 {
1105 ar934x_nfc_hw_reset_assert(nfc);
1106 ar934x_nfc_hw_reset_deassert(nfc);
1107 /*
1108 * setup timings
1109 * TODO: make it configurable via platform data or DT
1110 */
1111 ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIME_SEQ,
1112 AR934X_NFC_TIME_SEQ_DEFAULT);
1113 ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIMINGS_ASYN,
1114 AR934X_NFC_TIMINGS_ASYN_DEFAULT);
1115 ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIMINGS_SYN,
1116 AR934X_NFC_TIMINGS_SYN_DEFAULT);
1117
1118 /* disable WP on all chips, and select chip 0 */
1119 ar934x_nfc_wr(nfc, AR934X_NFC_REG_MEM_CTRL, 0xff00);
1120
1121 ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_ADDR_OFFS, 0);
1122
1123 /* initialize Control register */
1124 nfc->ctrl_reg = AR934X_NFC_CTRL_CUSTOM_SIZE_EN;
1125 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
1126
1127 if (nfc->small_page) {
1128 /* Setup generic sequence register for small page reads. */
1129 ar934x_nfc_wr(nfc, AR934X_NFC_REG_GEN_SEQ_CTRL,
1130 AR934X_NFC_GENSEQ_SMALL_PAGE_READ);
1131 }
1132
1133 return 0;
1134 }
1135
1136 static void ar934x_nfc_restart(struct ar934x_nfc *nfc)
1137 {
1138 u32 ctrl_reg;
1139
1140 ctrl_reg = nfc->ctrl_reg;
1141 ar934x_nfc_hw_init(nfc);
1142 nfc->ctrl_reg = ctrl_reg;
1143
1144 ar934x_nfc_send_cmd(nfc, NAND_CMD_RESET);
1145 }
1146
1147 static irqreturn_t ar934x_nfc_irq_handler(int irq, void *data)
1148 {
1149 struct ar934x_nfc *nfc = data;
1150 u32 status;
1151
1152 status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS);
1153
1154 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
1155 /* flush write */
1156 ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS);
1157
1158 status &= ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_MASK);
1159 if (status) {
1160 nfc_dbg(nfc, "got IRQ, status:%08x\n", status);
1161
1162 nfc->irq_status = status;
1163 nfc->spurious_irq_expected = true;
1164 wake_up(&nfc->irq_waitq);
1165 } else {
1166 if (nfc->spurious_irq_expected)
1167 nfc->spurious_irq_expected = false;
1168 else
1169 dev_warn(nfc->parent, "spurious interrupt\n");
1170 }
1171
1172 return IRQ_HANDLED;
1173 }
1174
1175 static int ar934x_nfc_init_tail(struct mtd_info *mtd)
1176 {
1177 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
1178 struct nand_chip *chip = &nfc->nand_chip;
1179 #if LINUX_VERSION_CODE < KERNEL_VERSION(5, 2, 0)
1180 u64 chipsize = chip->chipsize;
1181 #else
1182 u64 chipsize = nanddev_target_size(&chip->base);
1183 #endif
1184 u32 ctrl;
1185 u32 t;
1186 int err;
1187
1188 switch (mtd->oobsize) {
1189 case 16:
1190 case 64:
1191 case 128:
1192 ar934x_nfc_wr(nfc, AR934X_NFC_REG_SPARE_SIZE, mtd->oobsize);
1193 break;
1194
1195 default:
1196 dev_err(nfc->parent, "unsupported OOB size: %d bytes\n",
1197 mtd->oobsize);
1198 return -ENXIO;
1199 }
1200
1201 ctrl = AR934X_NFC_CTRL_CUSTOM_SIZE_EN;
1202
1203 switch (mtd->erasesize / mtd->writesize) {
1204 case 32:
1205 t = AR934X_NFC_CTRL_BLOCK_SIZE_32;
1206 break;
1207
1208 case 64:
1209 t = AR934X_NFC_CTRL_BLOCK_SIZE_64;
1210 break;
1211
1212 case 128:
1213 t = AR934X_NFC_CTRL_BLOCK_SIZE_128;
1214 break;
1215
1216 case 256:
1217 t = AR934X_NFC_CTRL_BLOCK_SIZE_256;
1218 break;
1219
1220 default:
1221 dev_err(nfc->parent, "unsupported block size: %u\n",
1222 mtd->erasesize / mtd->writesize);
1223 return -ENXIO;
1224 }
1225
1226 ctrl |= t << AR934X_NFC_CTRL_BLOCK_SIZE_S;
1227
1228 switch (mtd->writesize) {
1229 case 256:
1230 nfc->small_page = 1;
1231 t = AR934X_NFC_CTRL_PAGE_SIZE_256;
1232 break;
1233
1234 case 512:
1235 nfc->small_page = 1;
1236 t = AR934X_NFC_CTRL_PAGE_SIZE_512;
1237 break;
1238
1239 case 1024:
1240 t = AR934X_NFC_CTRL_PAGE_SIZE_1024;
1241 break;
1242
1243 case 2048:
1244 t = AR934X_NFC_CTRL_PAGE_SIZE_2048;
1245 break;
1246
1247 case 4096:
1248 t = AR934X_NFC_CTRL_PAGE_SIZE_4096;
1249 break;
1250
1251 case 8192:
1252 t = AR934X_NFC_CTRL_PAGE_SIZE_8192;
1253 break;
1254
1255 case 16384:
1256 t = AR934X_NFC_CTRL_PAGE_SIZE_16384;
1257 break;
1258
1259 default:
1260 dev_err(nfc->parent, "unsupported write size: %d bytes\n",
1261 mtd->writesize);
1262 return -ENXIO;
1263 }
1264
1265 ctrl |= t << AR934X_NFC_CTRL_PAGE_SIZE_S;
1266
1267 if (nfc->small_page) {
1268 ctrl |= AR934X_NFC_CTRL_SMALL_PAGE;
1269
1270 if (chipsize > (32 << 20)) {
1271 nfc->addr_count0 = 4;
1272 nfc->addr_count1 = 3;
1273 } else if (chipsize > (2 << 16)) {
1274 nfc->addr_count0 = 3;
1275 nfc->addr_count1 = 2;
1276 } else {
1277 nfc->addr_count0 = 2;
1278 nfc->addr_count1 = 1;
1279 }
1280 } else {
1281 if (chipsize > (128 << 20)) {
1282 nfc->addr_count0 = 5;
1283 nfc->addr_count1 = 3;
1284 } else if (chipsize > (8 << 16)) {
1285 nfc->addr_count0 = 4;
1286 nfc->addr_count1 = 2;
1287 } else {
1288 nfc->addr_count0 = 3;
1289 nfc->addr_count1 = 1;
1290 }
1291 }
1292
1293 ctrl |= nfc->addr_count0 << AR934X_NFC_CTRL_ADDR_CYCLE0_S;
1294 ctrl |= nfc->addr_count1 << AR934X_NFC_CTRL_ADDR_CYCLE1_S;
1295
1296 nfc->ctrl_reg = ctrl;
1297 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
1298
1299 ar934x_nfc_free_buf(nfc);
1300 err = ar934x_nfc_alloc_buf(nfc, mtd->writesize + mtd->oobsize);
1301
1302 return err;
1303 }
1304
1305 static int ar934x_nfc_ooblayout_ecc(struct mtd_info *mtd, int section,
1306 struct mtd_oob_region *oobregion)
1307 {
1308 if (section)
1309 return -ERANGE;
1310
1311 oobregion->offset = 20;
1312 oobregion->length = 28;
1313
1314 return 0;
1315 }
1316
1317 static int ar934x_nfc_ooblayout_free(struct mtd_info *mtd, int section,
1318 struct mtd_oob_region *oobregion)
1319 {
1320 switch (section) {
1321 case 0:
1322 oobregion->offset = 4;
1323 oobregion->length = 16;
1324 return 0;
1325 case 1:
1326 oobregion->offset = 48;
1327 oobregion->length = 16;
1328 return 0;
1329 default:
1330 return -ERANGE;
1331 }
1332 }
1333
1334 static const struct mtd_ooblayout_ops ar934x_nfc_ecclayout_ops = {
1335 .ecc = ar934x_nfc_ooblayout_ecc,
1336 .free = ar934x_nfc_ooblayout_free,
1337 };
1338
1339 static int ar934x_nfc_setup_hwecc(struct ar934x_nfc *nfc)
1340 {
1341 struct nand_chip *nand = &nfc->nand_chip;
1342 struct mtd_info *mtd = nand_to_mtd(nand);
1343 u32 ecc_cap;
1344 u32 ecc_thres;
1345 struct mtd_oob_region oobregion;
1346
1347 switch (mtd->writesize) {
1348 case 2048:
1349 /*
1350 * Writing a subpage separately is not supported, because
1351 * the controller only does ECC on full-page accesses.
1352 */
1353 nand->options = NAND_NO_SUBPAGE_WRITE;
1354
1355 nand->ecc.size = 512;
1356 nand->ecc.bytes = 7;
1357 nand->ecc.strength = 4;
1358 mtd_set_ooblayout(mtd, &ar934x_nfc_ecclayout_ops);
1359 break;
1360
1361 default:
1362 dev_err(nfc->parent,
1363 "hardware ECC is not available for %d byte pages\n",
1364 mtd->writesize);
1365 return -EINVAL;
1366 }
1367
1368 BUG_ON(!mtd->ooblayout->ecc);
1369
1370 switch (nand->ecc.strength) {
1371 case 4:
1372 ecc_cap = AR934X_NFC_ECC_CTRL_ECC_CAP_4;
1373 ecc_thres = 4;
1374 break;
1375
1376 default:
1377 dev_err(nfc->parent, "unsupported ECC strength %u\n",
1378 nand->ecc.strength);
1379 return -EINVAL;
1380 }
1381
1382 nfc->ecc_thres = ecc_thres;
1383 mtd->ooblayout->ecc(mtd, 0, &oobregion);
1384 nfc->ecc_oob_pos = oobregion.offset;
1385
1386 nfc->ecc_ctrl_reg = ecc_cap << AR934X_NFC_ECC_CTRL_ECC_CAP_S;
1387 nfc->ecc_ctrl_reg |= ecc_thres << AR934X_NFC_ECC_CTRL_ERR_THRES_S;
1388
1389 nfc->ecc_offset_reg = mtd->writesize + nfc->ecc_oob_pos;
1390
1391 nand->ecc.read_page = ar934x_nfc_read_page;
1392 nand->ecc.read_page_raw = ar934x_nfc_read_page_raw;
1393 nand->ecc.write_page = ar934x_nfc_write_page;
1394 nand->ecc.write_page_raw = ar934x_nfc_write_page_raw;
1395 nand->ecc.read_oob = ar934x_nfc_read_oob;
1396 nand->ecc.write_oob = ar934x_nfc_write_oob;
1397
1398 return 0;
1399 }
1400
1401 static int ar934x_nfc_attach_chip(struct nand_chip *nand)
1402 {
1403 struct mtd_info *mtd = nand_to_mtd(nand);
1404 struct ar934x_nfc *nfc = nand_get_controller_data(nand);
1405 struct device *dev = mtd->dev.parent;
1406 int ret;
1407
1408 ret = ar934x_nfc_init_tail(mtd);
1409 if (ret)
1410 return ret;
1411
1412 if (nand->ecc.mode == NAND_ECC_HW) {
1413 ret = ar934x_nfc_setup_hwecc(nfc);
1414 if (ret)
1415 return ret;
1416 } else if (nand->ecc.mode != NAND_ECC_SOFT) {
1417 dev_err(dev, "unknown ECC mode %d\n", nand->ecc.mode);
1418 return -EINVAL;
1419 } else if ((nand->ecc.algo != NAND_ECC_BCH) &&
1420 (nand->ecc.algo != NAND_ECC_HAMMING)) {
1421 dev_err(dev, "unknown software ECC algo %d\n", nand->ecc.algo);
1422 return -EINVAL;
1423 }
1424
1425 return 0;
1426 }
1427
1428 static u64 ar934x_nfc_dma_mask = DMA_BIT_MASK(32);
1429
1430 #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
1431 static void ar934x_nfc_cmd_ctrl(struct mtd_info *mtd, int dat,
1432 unsigned int ctrl)
1433 #else
1434 static void ar934x_nfc_cmd_ctrl(struct nand_chip *chip, int dat,
1435 unsigned int ctrl)
1436 #endif
1437 {
1438 WARN_ON(dat != NAND_CMD_NONE);
1439 }
1440
1441 static const struct nand_controller_ops ar934x_nfc_controller_ops = {
1442 .attach_chip = ar934x_nfc_attach_chip,
1443 };
1444
1445 static int ar934x_nfc_probe(struct platform_device *pdev)
1446 {
1447 struct ar934x_nfc *nfc;
1448 struct resource *res;
1449 struct mtd_info *mtd;
1450 struct nand_chip *nand;
1451 int ret;
1452
1453 pdev->dev.dma_mask = &ar934x_nfc_dma_mask;
1454 pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
1455
1456 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1457 if (!res) {
1458 dev_err(&pdev->dev, "failed to get I/O memory\n");
1459 return -EINVAL;
1460 }
1461
1462 nfc = devm_kzalloc(&pdev->dev, sizeof(struct ar934x_nfc), GFP_KERNEL);
1463 if (!nfc) {
1464 dev_err(&pdev->dev, "failed to allocate driver data\n");
1465 return -ENOMEM;
1466 }
1467
1468 nfc->base = devm_ioremap_resource(&pdev->dev, res);
1469 if (IS_ERR(nfc->base)) {
1470 dev_err(&pdev->dev, "failed to remap I/O memory\n");
1471 return PTR_ERR(nfc->base);
1472 }
1473
1474 nfc->irq = platform_get_irq(pdev, 0);
1475 if (nfc->irq < 0) {
1476 dev_err(&pdev->dev, "no IRQ resource specified\n");
1477 return -EINVAL;
1478 }
1479
1480 init_waitqueue_head(&nfc->irq_waitq);
1481 ret = devm_request_irq(&pdev->dev, nfc->irq, ar934x_nfc_irq_handler,
1482 0, AR934X_NFC_DRIVER_NAME, nfc);
1483 if (ret) {
1484 dev_err(&pdev->dev, "devm_request_irq failed, err:%d\n", ret);
1485 return ret;
1486 }
1487
1488 nfc->rst = devm_reset_control_get(&pdev->dev, "nand");
1489 if (IS_ERR(nfc->rst)) {
1490 dev_err(&pdev->dev, "Failed to get reset\n");
1491 return PTR_ERR(nfc->rst);
1492 }
1493
1494 nfc->parent = &pdev->dev;
1495 nfc->swap_dma = of_property_read_bool(pdev->dev.of_node,
1496 "qca,nand-swap-dma");
1497
1498 nand = &nfc->nand_chip;
1499 mtd = nand_to_mtd(nand);
1500
1501 mtd->owner = THIS_MODULE;
1502 mtd->dev.parent = &pdev->dev;
1503 mtd->name = AR934X_NFC_DRIVER_NAME;
1504
1505 nand_set_controller_data(nand, nfc);
1506 nand_set_flash_node(nand, pdev->dev.of_node);
1507 #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
1508 nand->chip_delay = 25;
1509 nand->dev_ready = ar934x_nfc_dev_ready;
1510 nand->cmdfunc = ar934x_nfc_cmdfunc;
1511 nand->cmd_ctrl = ar934x_nfc_cmd_ctrl; /* dummy */
1512 nand->read_byte = ar934x_nfc_read_byte;
1513 nand->write_buf = ar934x_nfc_write_buf;
1514 nand->read_buf = ar934x_nfc_read_buf;
1515 #else
1516 nand->legacy.chip_delay = 25;
1517 nand->legacy.dev_ready = ar934x_nfc_dev_ready;
1518 nand->legacy.cmdfunc = ar934x_nfc_cmdfunc;
1519 nand->legacy.cmd_ctrl = ar934x_nfc_cmd_ctrl; /* dummy */
1520 nand->legacy.read_byte = ar934x_nfc_read_byte;
1521 nand->legacy.write_buf = ar934x_nfc_write_buf;
1522 nand->legacy.read_buf = ar934x_nfc_read_buf;
1523 #endif
1524 nand->ecc.mode = NAND_ECC_HW; /* default */
1525 nand->priv = nfc;
1526 platform_set_drvdata(pdev, nfc);
1527
1528 ret = ar934x_nfc_alloc_buf(nfc, AR934X_NFC_ID_BUF_SIZE);
1529 if (ret)
1530 return ret;
1531
1532 ret = ar934x_nfc_hw_init(nfc);
1533 if (ret) {
1534 dev_err(&pdev->dev, "hardware init failed, err:%d\n", ret);
1535 goto err_free_buf;
1536 }
1537
1538 #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 19, 130)
1539 nand->dummy_controller.ops = &ar934x_nfc_controller_ops;
1540 ret = nand_scan(mtd, 1);
1541 #elif LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
1542 nand->dummy_controller.ops = &ar934x_nfc_controller_ops;
1543 ret = nand_scan(nand, 1);
1544 #else
1545 nand->legacy.dummy_controller.ops = &ar934x_nfc_controller_ops;
1546 ret = nand_scan(nand, 1);
1547 #endif
1548 if (ret) {
1549 dev_err(&pdev->dev, "nand_scan failed, err:%d\n", ret);
1550 goto err_free_buf;
1551 }
1552
1553 ret = mtd_device_register(mtd, NULL, 0);
1554 if (ret) {
1555 dev_err(&pdev->dev, "unable to register mtd, err:%d\n", ret);
1556 goto err_free_buf;
1557 }
1558
1559 return 0;
1560
1561 err_free_buf:
1562 ar934x_nfc_free_buf(nfc);
1563 return ret;
1564 }
1565
1566 static int ar934x_nfc_remove(struct platform_device *pdev)
1567 {
1568 struct ar934x_nfc *nfc;
1569 #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
1570 struct mtd_info *mtd;
1571 #endif
1572
1573 nfc = platform_get_drvdata(pdev);
1574 if (nfc) {
1575 nand_release(&nfc->nand_chip);
1576 ar934x_nfc_free_buf(nfc);
1577 }
1578
1579 return 0;
1580 }
1581
1582 static const struct of_device_id ar934x_nfc_match[] = {
1583 { .compatible = "qca," AR934X_NFC_DRIVER_NAME },
1584 {},
1585 };
1586
1587 MODULE_DEVICE_TABLE(of, ar934x_nfc_match);
1588
1589 static struct platform_driver ar934x_nfc_driver = {
1590 .probe = ar934x_nfc_probe,
1591 .remove = ar934x_nfc_remove,
1592 .driver = {
1593 .name = AR934X_NFC_DRIVER_NAME,
1594 .owner = THIS_MODULE,
1595 .of_match_table = ar934x_nfc_match,
1596 },
1597 };
1598
1599 module_platform_driver(ar934x_nfc_driver);
1600
1601 MODULE_LICENSE("GPL v2");
1602 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1603 MODULE_DESCRIPTION("Atheros AR934x NAND Flash Controller driver");
1604 MODULE_ALIAS("platform:" AR934X_NFC_DRIVER_NAME);
OpenWrt Source Repository