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ath79: add QCA955x SGMII link loss workaround
[openwrt/openwrt.git] / target / linux / ath79 / files / drivers / net / ethernet / atheros / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include <linux/sizes.h>
15 #include <linux/of_net.h>
16 #include <linux/of_address.h>
17 #include <linux/of_platform.h>
18 #include "ag71xx.h"
19
20 #define AG71XX_DEFAULT_MSG_ENABLE \
21 (NETIF_MSG_DRV \
22 | NETIF_MSG_PROBE \
23 | NETIF_MSG_LINK \
24 | NETIF_MSG_TIMER \
25 | NETIF_MSG_IFDOWN \
26 | NETIF_MSG_IFUP \
27 | NETIF_MSG_RX_ERR \
28 | NETIF_MSG_TX_ERR)
29
30 static int ag71xx_msg_level = -1;
31
32 module_param_named(msg_level, ag71xx_msg_level, int, 0);
33 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
34
35 #define ETH_SWITCH_HEADER_LEN 2
36
37 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush);
38
39 static inline unsigned int ag71xx_max_frame_len(unsigned int mtu)
40 {
41 return ETH_SWITCH_HEADER_LEN + ETH_HLEN + VLAN_HLEN + mtu + ETH_FCS_LEN;
42 }
43
44 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
45 {
46 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
47 ag->dev->name,
48 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
49 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
50 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
51
52 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
53 ag->dev->name,
54 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
55 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
56 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
57 }
58
59 static void ag71xx_dump_regs(struct ag71xx *ag)
60 {
61 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
62 ag->dev->name,
63 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
64 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
65 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
66 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
67 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
68 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
69 ag->dev->name,
70 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
71 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
72 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
73 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
74 ag->dev->name,
75 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
76 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
77 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
78 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
79 ag->dev->name,
80 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
81 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
82 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
83 }
84
85 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
86 {
87 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
88 ag->dev->name, label, intr,
89 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
90 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
91 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
92 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
93 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
94 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
95 }
96
97 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
98 {
99 struct ag71xx_ring *ring = &ag->tx_ring;
100 struct net_device *dev = ag->dev;
101 int ring_mask = BIT(ring->order) - 1;
102 u32 bytes_compl = 0, pkts_compl = 0;
103
104 while (ring->curr != ring->dirty) {
105 struct ag71xx_desc *desc;
106 u32 i = ring->dirty & ring_mask;
107
108 desc = ag71xx_ring_desc(ring, i);
109 if (!ag71xx_desc_empty(desc)) {
110 desc->ctrl = 0;
111 dev->stats.tx_errors++;
112 }
113
114 if (ring->buf[i].skb) {
115 bytes_compl += ring->buf[i].len;
116 pkts_compl++;
117 dev_kfree_skb_any(ring->buf[i].skb);
118 }
119 ring->buf[i].skb = NULL;
120 ring->dirty++;
121 }
122
123 /* flush descriptors */
124 wmb();
125
126 netdev_completed_queue(dev, pkts_compl, bytes_compl);
127 }
128
129 static void ag71xx_ring_tx_init(struct ag71xx *ag)
130 {
131 struct ag71xx_ring *ring = &ag->tx_ring;
132 int ring_size = BIT(ring->order);
133 int ring_mask = BIT(ring->order) - 1;
134 int i;
135
136 for (i = 0; i < ring_size; i++) {
137 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
138
139 desc->next = (u32) (ring->descs_dma +
140 AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
141
142 desc->ctrl = DESC_EMPTY;
143 ring->buf[i].skb = NULL;
144 }
145
146 /* flush descriptors */
147 wmb();
148
149 ring->curr = 0;
150 ring->dirty = 0;
151 netdev_reset_queue(ag->dev);
152 }
153
154 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
155 {
156 struct ag71xx_ring *ring = &ag->rx_ring;
157 int ring_size = BIT(ring->order);
158 int i;
159
160 if (!ring->buf)
161 return;
162
163 for (i = 0; i < ring_size; i++)
164 if (ring->buf[i].rx_buf) {
165 dma_unmap_single(&ag->pdev->dev, ring->buf[i].dma_addr,
166 ag->rx_buf_size, DMA_FROM_DEVICE);
167 skb_free_frag(ring->buf[i].rx_buf);
168 }
169 }
170
171 static int ag71xx_buffer_size(struct ag71xx *ag)
172 {
173 return ag->rx_buf_size +
174 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
175 }
176
177 static bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf,
178 int offset,
179 void *(*alloc)(unsigned int size))
180 {
181 struct ag71xx_ring *ring = &ag->rx_ring;
182 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, buf - &ring->buf[0]);
183 void *data;
184
185 data = alloc(ag71xx_buffer_size(ag));
186 if (!data)
187 return false;
188
189 buf->rx_buf = data;
190 buf->dma_addr = dma_map_single(&ag->pdev->dev, data, ag->rx_buf_size,
191 DMA_FROM_DEVICE);
192 desc->data = (u32) buf->dma_addr + offset;
193 return true;
194 }
195
196 static int ag71xx_ring_rx_init(struct ag71xx *ag)
197 {
198 struct ag71xx_ring *ring = &ag->rx_ring;
199 int ring_size = BIT(ring->order);
200 int ring_mask = BIT(ring->order) - 1;
201 unsigned int i;
202 int ret;
203
204 ret = 0;
205 for (i = 0; i < ring_size; i++) {
206 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
207
208 desc->next = (u32) (ring->descs_dma +
209 AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
210
211 DBG("ag71xx: RX desc at %p, next is %08x\n",
212 desc, desc->next);
213 }
214
215 for (i = 0; i < ring_size; i++) {
216 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
217
218 if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], ag->rx_buf_offset,
219 netdev_alloc_frag)) {
220 ret = -ENOMEM;
221 break;
222 }
223
224 desc->ctrl = DESC_EMPTY;
225 }
226
227 /* flush descriptors */
228 wmb();
229
230 ring->curr = 0;
231 ring->dirty = 0;
232
233 return ret;
234 }
235
236 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
237 {
238 struct ag71xx_ring *ring = &ag->rx_ring;
239 int ring_mask = BIT(ring->order) - 1;
240 unsigned int count;
241 int offset = ag->rx_buf_offset;
242
243 count = 0;
244 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
245 struct ag71xx_desc *desc;
246 unsigned int i;
247
248 i = ring->dirty & ring_mask;
249 desc = ag71xx_ring_desc(ring, i);
250
251 if (!ring->buf[i].rx_buf &&
252 !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset,
253 napi_alloc_frag))
254 break;
255
256 desc->ctrl = DESC_EMPTY;
257 count++;
258 }
259
260 /* flush descriptors */
261 wmb();
262
263 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
264
265 return count;
266 }
267
268 static int ag71xx_rings_init(struct ag71xx *ag)
269 {
270 struct ag71xx_ring *tx = &ag->tx_ring;
271 struct ag71xx_ring *rx = &ag->rx_ring;
272 int ring_size = BIT(tx->order) + BIT(rx->order);
273 int tx_size = BIT(tx->order);
274
275 tx->buf = kzalloc(ring_size * sizeof(*tx->buf), GFP_KERNEL);
276 if (!tx->buf)
277 return -ENOMEM;
278
279 tx->descs_cpu = dma_alloc_coherent(&ag->pdev->dev, ring_size * AG71XX_DESC_SIZE,
280 &tx->descs_dma, GFP_KERNEL);
281 if (!tx->descs_cpu) {
282 kfree(tx->buf);
283 tx->buf = NULL;
284 return -ENOMEM;
285 }
286
287 rx->buf = &tx->buf[tx_size];
288 rx->descs_cpu = ((void *)tx->descs_cpu) + tx_size * AG71XX_DESC_SIZE;
289 rx->descs_dma = tx->descs_dma + tx_size * AG71XX_DESC_SIZE;
290
291 ag71xx_ring_tx_init(ag);
292 return ag71xx_ring_rx_init(ag);
293 }
294
295 static void ag71xx_rings_free(struct ag71xx *ag)
296 {
297 struct ag71xx_ring *tx = &ag->tx_ring;
298 struct ag71xx_ring *rx = &ag->rx_ring;
299 int ring_size = BIT(tx->order) + BIT(rx->order);
300
301 if (tx->descs_cpu)
302 dma_free_coherent(&ag->pdev->dev, ring_size * AG71XX_DESC_SIZE,
303 tx->descs_cpu, tx->descs_dma);
304
305 kfree(tx->buf);
306
307 tx->descs_cpu = NULL;
308 rx->descs_cpu = NULL;
309 tx->buf = NULL;
310 rx->buf = NULL;
311 }
312
313 static void ag71xx_rings_cleanup(struct ag71xx *ag)
314 {
315 ag71xx_ring_rx_clean(ag);
316 ag71xx_ring_tx_clean(ag);
317 ag71xx_rings_free(ag);
318
319 netdev_reset_queue(ag->dev);
320 }
321
322 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
323 {
324 switch (ag->speed) {
325 case SPEED_1000:
326 return "1000";
327 case SPEED_100:
328 return "100";
329 case SPEED_10:
330 return "10";
331 }
332
333 return "?";
334 }
335
336 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
337 {
338 u32 t;
339
340 t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
341 | (((u32) mac[3]) << 8) | ((u32) mac[2]);
342
343 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
344
345 t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
346 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
347 }
348
349 static void ag71xx_dma_reset(struct ag71xx *ag)
350 {
351 u32 val;
352 int i;
353
354 ag71xx_dump_dma_regs(ag);
355
356 /* stop RX and TX */
357 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
358 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
359
360 /*
361 * give the hardware some time to really stop all rx/tx activity
362 * clearing the descriptors too early causes random memory corruption
363 */
364 mdelay(1);
365
366 /* clear descriptor addresses */
367 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
368 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
369
370 /* clear pending RX/TX interrupts */
371 for (i = 0; i < 256; i++) {
372 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
373 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
374 }
375
376 /* clear pending errors */
377 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
378 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
379
380 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
381 if (val)
382 pr_alert("%s: unable to clear DMA Rx status: %08x\n",
383 ag->dev->name, val);
384
385 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
386
387 /* mask out reserved bits */
388 val &= ~0xff000000;
389
390 if (val)
391 pr_alert("%s: unable to clear DMA Tx status: %08x\n",
392 ag->dev->name, val);
393
394 ag71xx_dump_dma_regs(ag);
395 }
396
397 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
398 MAC_CFG1_SRX | MAC_CFG1_STX)
399
400 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
401
402 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
403 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
404 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
405 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
406 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
407 FIFO_CFG4_VT)
408
409 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
410 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
411 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
412 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
413 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
414 FIFO_CFG5_17 | FIFO_CFG5_SF)
415
416 static void ag71xx_hw_stop(struct ag71xx *ag)
417 {
418 /* disable all interrupts and stop the rx/tx engine */
419 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
420 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
421 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
422 }
423
424 static void ag71xx_hw_setup(struct ag71xx *ag)
425 {
426 struct device_node *np = ag->pdev->dev.of_node;
427 u32 init = MAC_CFG1_INIT;
428
429 /* setup MAC configuration registers */
430 if (of_property_read_bool(np, "flow-control"))
431 init |= MAC_CFG1_TFC | MAC_CFG1_RFC;
432 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, init);
433
434 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
435 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
436
437 /* setup max frame length to zero */
438 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 0);
439
440 /* setup FIFO configuration registers */
441 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
442 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, ag->fifodata[0]);
443 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, ag->fifodata[1]);
444 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
445 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
446 }
447
448 static void ag71xx_hw_init(struct ag71xx *ag)
449 {
450 ag71xx_hw_stop(ag);
451
452 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
453 udelay(20);
454
455 reset_control_assert(ag->mac_reset);
456 if (ag->mdio_reset)
457 reset_control_assert(ag->mdio_reset);
458 msleep(100);
459 reset_control_deassert(ag->mac_reset);
460 if (ag->mdio_reset)
461 reset_control_deassert(ag->mdio_reset);
462 msleep(200);
463
464 ag71xx_hw_setup(ag);
465
466 ag71xx_dma_reset(ag);
467 }
468
469 static void ag71xx_fast_reset(struct ag71xx *ag)
470 {
471 struct net_device *dev = ag->dev;
472 u32 rx_ds;
473 u32 mii_reg;
474
475 ag71xx_hw_stop(ag);
476 wmb();
477
478 mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
479 rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
480
481 ag71xx_tx_packets(ag, true);
482
483 reset_control_assert(ag->mac_reset);
484 udelay(10);
485 reset_control_deassert(ag->mac_reset);
486 udelay(10);
487
488 ag71xx_dma_reset(ag);
489 ag71xx_hw_setup(ag);
490 ag->tx_ring.curr = 0;
491 ag->tx_ring.dirty = 0;
492 netdev_reset_queue(ag->dev);
493
494 /* setup max frame length */
495 ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
496 ag71xx_max_frame_len(ag->dev->mtu));
497
498 ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
499 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
500 ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
501
502 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
503 }
504
505 static void ag71xx_hw_start(struct ag71xx *ag)
506 {
507 /* start RX engine */
508 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
509
510 /* enable interrupts */
511 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
512
513 netif_wake_queue(ag->dev);
514 }
515
516 static void ath79_set_pllval(struct ag71xx *ag)
517 {
518 u32 pll_reg = ag->pllreg[1];
519 u32 pll_val;
520
521 if (!ag->pllregmap)
522 return;
523
524 switch (ag->speed) {
525 case SPEED_10:
526 pll_val = ag->plldata[2];
527 break;
528 case SPEED_100:
529 pll_val = ag->plldata[1];
530 break;
531 case SPEED_1000:
532 pll_val = ag->plldata[0];
533 break;
534 default:
535 BUG();
536 }
537
538 if (pll_val)
539 regmap_write(ag->pllregmap, pll_reg, pll_val);
540 }
541
542 static void ath79_set_pll(struct ag71xx *ag)
543 {
544 u32 pll_cfg = ag->pllreg[0];
545 u32 pll_shift = ag->pllreg[2];
546
547 if (!ag->pllregmap)
548 return;
549
550 regmap_update_bits(ag->pllregmap, pll_cfg, 3 << pll_shift, 2 << pll_shift);
551 udelay(100);
552
553 ath79_set_pllval(ag);
554
555 regmap_update_bits(ag->pllregmap, pll_cfg, 3 << pll_shift, 3 << pll_shift);
556 udelay(100);
557
558 regmap_update_bits(ag->pllregmap, pll_cfg, 3 << pll_shift, 0);
559 udelay(100);
560 }
561
562 static void ag71xx_bit_set(void __iomem *reg, u32 bit)
563 {
564 u32 val;
565
566 val = __raw_readl(reg) | bit;
567 __raw_writel(val, reg);
568 __raw_readl(reg);
569 }
570
571 static void ag71xx_bit_clear(void __iomem *reg, u32 bit)
572 {
573 u32 val;
574
575 val = __raw_readl(reg) & ~bit;
576 __raw_writel(val, reg);
577 __raw_readl(reg);
578 }
579
580 static void ag71xx_sgmii_init_qca955x(struct device_node *np)
581 {
582 struct device_node *np_dev;
583 void __iomem *gmac_base;
584 u32 mr_an_status;
585 u32 sgmii_status;
586 u8 tries = 0;
587 int err = 0;
588
589 np = of_get_child_by_name(np, "gmac-config");
590 if (!np)
591 return;
592
593 np_dev = of_parse_phandle(np, "device", 0);
594 if (!np_dev)
595 goto out;
596
597 gmac_base = of_iomap(np_dev, 0);
598 if (!gmac_base) {
599 pr_err("%pOF: can't map GMAC registers\n", np_dev);
600 err = -ENOMEM;
601 goto err_iomap;
602 }
603
604 mr_an_status = __raw_readl(gmac_base + QCA955X_GMAC_REG_MR_AN_STATUS);
605 if (!(mr_an_status & QCA955X_MR_AN_STATUS_AN_ABILITY))
606 goto sgmii_out;
607
608 /* SGMII reset sequence */
609 __raw_writel(QCA955X_SGMII_RESET_RX_CLK_N_RESET,
610 gmac_base + QCA955X_GMAC_REG_SGMII_RESET);
611 __raw_readl(gmac_base + QCA955X_GMAC_REG_SGMII_RESET);
612 udelay(10);
613
614 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
615 QCA955X_SGMII_RESET_HW_RX_125M_N);
616 udelay(10);
617
618 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
619 QCA955X_SGMII_RESET_RX_125M_N);
620 udelay(10);
621
622 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
623 QCA955X_SGMII_RESET_TX_125M_N);
624 udelay(10);
625
626 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
627 QCA955X_SGMII_RESET_RX_CLK_N);
628 udelay(10);
629
630 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
631 QCA955X_SGMII_RESET_TX_CLK_N);
632 udelay(10);
633
634 /*
635 * The following is what QCA has to say about what happens here:
636 *
637 * Across resets SGMII link status goes to weird state.
638 * If SGMII_DEBUG register reads other than 0x1f or 0x10,
639 * we are for sure in a bad state.
640 *
641 * Issue a PHY reset in MR_AN_CONTROL to keep going.
642 */
643 do {
644 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_MR_AN_CONTROL,
645 QCA955X_MR_AN_CONTROL_PHY_RESET |
646 QCA955X_MR_AN_CONTROL_AN_ENABLE);
647 udelay(200);
648 ag71xx_bit_clear(gmac_base + QCA955X_GMAC_REG_MR_AN_CONTROL,
649 QCA955X_MR_AN_CONTROL_PHY_RESET);
650 mdelay(300);
651 sgmii_status = __raw_readl(gmac_base + QCA955X_GMAC_REG_SGMII_DEBUG) &
652 QCA955X_SGMII_DEBUG_TX_STATE_MASK;
653
654 if (tries++ >= 20) {
655 pr_err("ag71xx: max retries for SGMII fixup exceeded\n");
656 break;
657 }
658 } while (!(sgmii_status == 0xf || sgmii_status == 0x10));
659
660 sgmii_out:
661 iounmap(gmac_base);
662 err_iomap:
663 of_node_put(np_dev);
664 out:
665 of_node_put(np);
666 }
667
668 static void ath79_mii_ctrl_set_if(struct ag71xx *ag, unsigned int mii_if)
669 {
670 u32 t;
671
672 t = __raw_readl(ag->mii_base);
673 t &= ~(AR71XX_MII_CTRL_IF_MASK);
674 t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
675 __raw_writel(t, ag->mii_base);
676 }
677
678 static void ath79_mii0_ctrl_set_if(struct ag71xx *ag)
679 {
680 unsigned int mii_if;
681
682 switch (ag->phy_if_mode) {
683 case PHY_INTERFACE_MODE_MII:
684 mii_if = AR71XX_MII0_CTRL_IF_MII;
685 break;
686 case PHY_INTERFACE_MODE_GMII:
687 mii_if = AR71XX_MII0_CTRL_IF_GMII;
688 break;
689 case PHY_INTERFACE_MODE_RGMII:
690 case PHY_INTERFACE_MODE_RGMII_ID:
691 mii_if = AR71XX_MII0_CTRL_IF_RGMII;
692 break;
693 case PHY_INTERFACE_MODE_RMII:
694 mii_if = AR71XX_MII0_CTRL_IF_RMII;
695 break;
696 default:
697 WARN(1, "Impossible PHY mode defined.\n");
698 return;
699 }
700
701 ath79_mii_ctrl_set_if(ag, mii_if);
702 }
703
704 static void ath79_mii1_ctrl_set_if(struct ag71xx *ag)
705 {
706 unsigned int mii_if;
707
708 switch (ag->phy_if_mode) {
709 case PHY_INTERFACE_MODE_RMII:
710 mii_if = AR71XX_MII1_CTRL_IF_RMII;
711 break;
712 case PHY_INTERFACE_MODE_RGMII:
713 case PHY_INTERFACE_MODE_RGMII_ID:
714 mii_if = AR71XX_MII1_CTRL_IF_RGMII;
715 break;
716 default:
717 WARN(1, "Impossible PHY mode defined.\n");
718 return;
719 }
720
721 ath79_mii_ctrl_set_if(ag, mii_if);
722 }
723
724 static void ath79_mii_ctrl_set_speed(struct ag71xx *ag)
725 {
726 unsigned int mii_speed;
727 u32 t;
728
729 if (!ag->mii_base)
730 return;
731
732 switch (ag->speed) {
733 case SPEED_10:
734 mii_speed = AR71XX_MII_CTRL_SPEED_10;
735 break;
736 case SPEED_100:
737 mii_speed = AR71XX_MII_CTRL_SPEED_100;
738 break;
739 case SPEED_1000:
740 mii_speed = AR71XX_MII_CTRL_SPEED_1000;
741 break;
742 default:
743 BUG();
744 }
745
746 t = __raw_readl(ag->mii_base);
747 t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);
748 t |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT;
749 __raw_writel(t, ag->mii_base);
750 }
751
752 static void
753 __ag71xx_link_adjust(struct ag71xx *ag, bool update)
754 {
755 struct device_node *np = ag->pdev->dev.of_node;
756 u32 cfg2;
757 u32 ifctl;
758 u32 fifo5;
759
760 if (!ag->link && update) {
761 ag71xx_hw_stop(ag);
762 netif_carrier_off(ag->dev);
763 if (netif_msg_link(ag))
764 pr_info("%s: link down\n", ag->dev->name);
765 return;
766 }
767
768 if (!of_device_is_compatible(np, "qca,ar9130-eth") &&
769 !of_device_is_compatible(np, "qca,ar7100-eth"))
770 ag71xx_fast_reset(ag);
771
772 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
773 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
774 cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
775
776 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
777 ifctl &= ~(MAC_IFCTL_SPEED);
778
779 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
780 fifo5 &= ~FIFO_CFG5_BM;
781
782 switch (ag->speed) {
783 case SPEED_1000:
784 cfg2 |= MAC_CFG2_IF_1000;
785 fifo5 |= FIFO_CFG5_BM;
786 break;
787 case SPEED_100:
788 cfg2 |= MAC_CFG2_IF_10_100;
789 ifctl |= MAC_IFCTL_SPEED;
790 break;
791 case SPEED_10:
792 cfg2 |= MAC_CFG2_IF_10_100;
793 break;
794 default:
795 BUG();
796 return;
797 }
798
799 if (ag->tx_ring.desc_split) {
800 ag->fifodata[2] &= 0xffff;
801 ag->fifodata[2] |= ((2048 - ag->tx_ring.desc_split) / 4) << 16;
802 }
803
804 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, ag->fifodata[2]);
805
806 if (update) {
807 if (of_device_is_compatible(np, "qca,ar7100-eth") ||
808 of_device_is_compatible(np, "qca,ar9130-eth")) {
809 ath79_set_pll(ag);
810 ath79_mii_ctrl_set_speed(ag);
811 } else if (of_device_is_compatible(np, "qca,ar7242-eth") ||
812 of_device_is_compatible(np, "qca,ar9340-eth") ||
813 of_device_is_compatible(np, "qca,qca9550-eth") ||
814 of_device_is_compatible(np, "qca,qca9560-eth")) {
815 ath79_set_pllval(ag);
816 if (of_property_read_bool(np, "qca955x-sgmii-fixup"))
817 ag71xx_sgmii_init_qca955x(np);
818 }
819 }
820
821 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
822 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
823 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
824
825 if (of_device_is_compatible(np, "qca,qca9530-eth") ||
826 of_device_is_compatible(np, "qca,qca9560-eth")) {
827 /*
828 * The rx ring buffer can stall on small packets on QCA953x and
829 * QCA956x. Disabling the inline checksum engine fixes the stall.
830 * The wr, rr functions cannot be used since this hidden register
831 * is outside of the normal ag71xx register block.
832 */
833 void __iomem *dam = ioremap_nocache(0xb90001bc, 0x4);
834 if (dam) {
835 __raw_writel(__raw_readl(dam) & ~BIT(27), dam);
836 (void)__raw_readl(dam);
837 iounmap(dam);
838 }
839 }
840
841 ag71xx_hw_start(ag);
842
843 netif_carrier_on(ag->dev);
844 if (update && netif_msg_link(ag))
845 pr_info("%s: link up (%sMbps/%s duplex)\n",
846 ag->dev->name,
847 ag71xx_speed_str(ag),
848 (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
849
850 ag71xx_dump_regs(ag);
851 }
852
853 void ag71xx_link_adjust(struct ag71xx *ag)
854 {
855 __ag71xx_link_adjust(ag, true);
856 }
857
858 static int ag71xx_hw_enable(struct ag71xx *ag)
859 {
860 int ret;
861
862 ret = ag71xx_rings_init(ag);
863 if (ret)
864 return ret;
865
866 napi_enable(&ag->napi);
867 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
868 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
869 netif_start_queue(ag->dev);
870
871 return 0;
872 }
873
874 static void ag71xx_hw_disable(struct ag71xx *ag)
875 {
876 netif_stop_queue(ag->dev);
877
878 ag71xx_hw_stop(ag);
879 ag71xx_dma_reset(ag);
880
881 napi_disable(&ag->napi);
882 del_timer_sync(&ag->oom_timer);
883
884 ag71xx_rings_cleanup(ag);
885 }
886
887 static int ag71xx_open(struct net_device *dev)
888 {
889 struct ag71xx *ag = netdev_priv(dev);
890 unsigned int max_frame_len;
891 int ret;
892
893 netif_carrier_off(dev);
894 max_frame_len = ag71xx_max_frame_len(dev->mtu);
895 ag->rx_buf_size = SKB_DATA_ALIGN(max_frame_len + NET_SKB_PAD + NET_IP_ALIGN);
896
897 /* setup max frame length */
898 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, max_frame_len);
899 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
900
901 ret = ag71xx_hw_enable(ag);
902 if (ret)
903 goto err;
904
905 phy_start(ag->phy_dev);
906
907 return 0;
908
909 err:
910 ag71xx_rings_cleanup(ag);
911 return ret;
912 }
913
914 static int ag71xx_stop(struct net_device *dev)
915 {
916 unsigned long flags;
917 struct ag71xx *ag = netdev_priv(dev);
918
919 netif_carrier_off(dev);
920 phy_stop(ag->phy_dev);
921
922 spin_lock_irqsave(&ag->lock, flags);
923 if (ag->link) {
924 ag->link = 0;
925 ag71xx_link_adjust(ag);
926 }
927 spin_unlock_irqrestore(&ag->lock, flags);
928
929 ag71xx_hw_disable(ag);
930
931 return 0;
932 }
933
934 static int ag71xx_fill_dma_desc(struct ag71xx_ring *ring, u32 addr, int len)
935 {
936 int i;
937 struct ag71xx_desc *desc;
938 int ring_mask = BIT(ring->order) - 1;
939 int ndesc = 0;
940 int split = ring->desc_split;
941
942 if (!split)
943 split = len;
944
945 while (len > 0) {
946 unsigned int cur_len = len;
947
948 i = (ring->curr + ndesc) & ring_mask;
949 desc = ag71xx_ring_desc(ring, i);
950
951 if (!ag71xx_desc_empty(desc))
952 return -1;
953
954 if (cur_len > split) {
955 cur_len = split;
956
957 /*
958 * TX will hang if DMA transfers <= 4 bytes,
959 * make sure next segment is more than 4 bytes long.
960 */
961 if (len <= split + 4)
962 cur_len -= 4;
963 }
964
965 desc->data = addr;
966 addr += cur_len;
967 len -= cur_len;
968
969 if (len > 0)
970 cur_len |= DESC_MORE;
971
972 /* prevent early tx attempt of this descriptor */
973 if (!ndesc)
974 cur_len |= DESC_EMPTY;
975
976 desc->ctrl = cur_len;
977 ndesc++;
978 }
979
980 return ndesc;
981 }
982
983 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
984 struct net_device *dev)
985 {
986 struct ag71xx *ag = netdev_priv(dev);
987 struct ag71xx_ring *ring = &ag->tx_ring;
988 int ring_mask = BIT(ring->order) - 1;
989 int ring_size = BIT(ring->order);
990 struct ag71xx_desc *desc;
991 dma_addr_t dma_addr;
992 int i, n, ring_min;
993
994 if (skb->len <= 4) {
995 DBG("%s: packet len is too small\n", ag->dev->name);
996 goto err_drop;
997 }
998
999 dma_addr = dma_map_single(&ag->pdev->dev, skb->data, skb->len,
1000 DMA_TO_DEVICE);
1001
1002 i = ring->curr & ring_mask;
1003 desc = ag71xx_ring_desc(ring, i);
1004
1005 /* setup descriptor fields */
1006 n = ag71xx_fill_dma_desc(ring, (u32) dma_addr, skb->len & ag->desc_pktlen_mask);
1007 if (n < 0)
1008 goto err_drop_unmap;
1009
1010 i = (ring->curr + n - 1) & ring_mask;
1011 ring->buf[i].len = skb->len;
1012 ring->buf[i].skb = skb;
1013
1014 netdev_sent_queue(dev, skb->len);
1015
1016 skb_tx_timestamp(skb);
1017
1018 desc->ctrl &= ~DESC_EMPTY;
1019 ring->curr += n;
1020
1021 /* flush descriptor */
1022 wmb();
1023
1024 ring_min = 2;
1025 if (ring->desc_split)
1026 ring_min *= AG71XX_TX_RING_DS_PER_PKT;
1027
1028 if (ring->curr - ring->dirty >= ring_size - ring_min) {
1029 DBG("%s: tx queue full\n", dev->name);
1030 netif_stop_queue(dev);
1031 }
1032
1033 DBG("%s: packet injected into TX queue\n", ag->dev->name);
1034
1035 /* enable TX engine */
1036 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
1037
1038 return NETDEV_TX_OK;
1039
1040 err_drop_unmap:
1041 dma_unmap_single(&ag->pdev->dev, dma_addr, skb->len, DMA_TO_DEVICE);
1042
1043 err_drop:
1044 dev->stats.tx_dropped++;
1045
1046 dev_kfree_skb(skb);
1047 return NETDEV_TX_OK;
1048 }
1049
1050 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1051 {
1052 struct ag71xx *ag = netdev_priv(dev);
1053
1054
1055 switch (cmd) {
1056 case SIOCSIFHWADDR:
1057 if (copy_from_user
1058 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
1059 return -EFAULT;
1060 return 0;
1061
1062 case SIOCGIFHWADDR:
1063 if (copy_to_user
1064 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
1065 return -EFAULT;
1066 return 0;
1067
1068 case SIOCGMIIPHY:
1069 case SIOCGMIIREG:
1070 case SIOCSMIIREG:
1071 if (ag->phy_dev == NULL)
1072 break;
1073
1074 return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
1075
1076 default:
1077 break;
1078 }
1079
1080 return -EOPNOTSUPP;
1081 }
1082
1083 #if (LINUX_VERSION_CODE < KERNEL_VERSION(4,15,0))
1084 static void ag71xx_oom_timer_handler(unsigned long data)
1085 {
1086 struct net_device *dev = (struct net_device *) data;
1087 struct ag71xx *ag = netdev_priv(dev);
1088 #else
1089 static void ag71xx_oom_timer_handler(struct timer_list *t)
1090 {
1091 struct ag71xx *ag = from_timer(ag, t, oom_timer);
1092 #endif
1093
1094 napi_schedule(&ag->napi);
1095 }
1096
1097 static void ag71xx_tx_timeout(struct net_device *dev)
1098 {
1099 struct ag71xx *ag = netdev_priv(dev);
1100
1101 if (netif_msg_tx_err(ag))
1102 pr_info("%s: tx timeout\n", ag->dev->name);
1103
1104 schedule_delayed_work(&ag->restart_work, 1);
1105 }
1106
1107 static void ag71xx_restart_work_func(struct work_struct *work)
1108 {
1109 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work.work);
1110
1111 rtnl_lock();
1112 ag71xx_hw_disable(ag);
1113 ag71xx_hw_enable(ag);
1114 if (ag->link)
1115 __ag71xx_link_adjust(ag, false);
1116 rtnl_unlock();
1117 }
1118
1119 static bool ag71xx_check_dma_stuck(struct ag71xx *ag)
1120 {
1121 unsigned long timestamp;
1122 u32 rx_sm, tx_sm, rx_fd;
1123
1124 timestamp = netdev_get_tx_queue(ag->dev, 0)->trans_start;
1125 if (likely(time_before(jiffies, timestamp + HZ/10)))
1126 return false;
1127
1128 if (!netif_carrier_ok(ag->dev))
1129 return false;
1130
1131 rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM);
1132 if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6)
1133 return true;
1134
1135 tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM);
1136 rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH);
1137 if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) &&
1138 ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0)
1139 return true;
1140
1141 return false;
1142 }
1143
1144 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush)
1145 {
1146 struct ag71xx_ring *ring = &ag->tx_ring;
1147 bool dma_stuck = false;
1148 int ring_mask = BIT(ring->order) - 1;
1149 int ring_size = BIT(ring->order);
1150 int sent = 0;
1151 int bytes_compl = 0;
1152 int n = 0;
1153
1154 DBG("%s: processing TX ring\n", ag->dev->name);
1155
1156 while (ring->dirty + n != ring->curr) {
1157 unsigned int i = (ring->dirty + n) & ring_mask;
1158 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
1159 struct sk_buff *skb = ring->buf[i].skb;
1160
1161 if (!flush && !ag71xx_desc_empty(desc)) {
1162 if (ag->tx_hang_workaround &&
1163 ag71xx_check_dma_stuck(ag)) {
1164 schedule_delayed_work(&ag->restart_work, HZ / 2);
1165 dma_stuck = true;
1166 }
1167 break;
1168 }
1169
1170 if (flush)
1171 desc->ctrl |= DESC_EMPTY;
1172
1173 n++;
1174 if (!skb)
1175 continue;
1176
1177 dev_kfree_skb_any(skb);
1178 ring->buf[i].skb = NULL;
1179
1180 bytes_compl += ring->buf[i].len;
1181
1182 sent++;
1183 ring->dirty += n;
1184
1185 while (n > 0) {
1186 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
1187 n--;
1188 }
1189 }
1190
1191 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
1192
1193 if (!sent)
1194 return 0;
1195
1196 ag->dev->stats.tx_bytes += bytes_compl;
1197 ag->dev->stats.tx_packets += sent;
1198
1199 netdev_completed_queue(ag->dev, sent, bytes_compl);
1200 if ((ring->curr - ring->dirty) < (ring_size * 3) / 4)
1201 netif_wake_queue(ag->dev);
1202
1203 if (!dma_stuck)
1204 cancel_delayed_work(&ag->restart_work);
1205
1206 return sent;
1207 }
1208
1209 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
1210 {
1211 struct net_device *dev = ag->dev;
1212 struct ag71xx_ring *ring = &ag->rx_ring;
1213 unsigned int pktlen_mask = ag->desc_pktlen_mask;
1214 unsigned int offset = ag->rx_buf_offset;
1215 int ring_mask = BIT(ring->order) - 1;
1216 int ring_size = BIT(ring->order);
1217 struct sk_buff_head queue;
1218 struct sk_buff *skb;
1219 int done = 0;
1220
1221 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
1222 dev->name, limit, ring->curr, ring->dirty);
1223
1224 skb_queue_head_init(&queue);
1225
1226 while (done < limit) {
1227 unsigned int i = ring->curr & ring_mask;
1228 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
1229 int pktlen;
1230 int err = 0;
1231
1232 if (ag71xx_desc_empty(desc))
1233 break;
1234
1235 if ((ring->dirty + ring_size) == ring->curr) {
1236 ag71xx_assert(0);
1237 break;
1238 }
1239
1240 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
1241
1242 pktlen = desc->ctrl & pktlen_mask;
1243 pktlen -= ETH_FCS_LEN;
1244
1245 dma_unmap_single(&ag->pdev->dev, ring->buf[i].dma_addr,
1246 ag->rx_buf_size, DMA_FROM_DEVICE);
1247
1248 dev->stats.rx_packets++;
1249 dev->stats.rx_bytes += pktlen;
1250
1251 skb = build_skb(ring->buf[i].rx_buf, ag71xx_buffer_size(ag));
1252 if (!skb) {
1253 skb_free_frag(ring->buf[i].rx_buf);
1254 goto next;
1255 }
1256
1257 skb_reserve(skb, offset);
1258 skb_put(skb, pktlen);
1259
1260 if (err) {
1261 dev->stats.rx_dropped++;
1262 kfree_skb(skb);
1263 } else {
1264 skb->dev = dev;
1265 skb->ip_summed = CHECKSUM_NONE;
1266 __skb_queue_tail(&queue, skb);
1267 }
1268
1269 next:
1270 ring->buf[i].rx_buf = NULL;
1271 done++;
1272
1273 ring->curr++;
1274 }
1275
1276 ag71xx_ring_rx_refill(ag);
1277
1278 while ((skb = __skb_dequeue(&queue)) != NULL) {
1279 skb->protocol = eth_type_trans(skb, dev);
1280 netif_receive_skb(skb);
1281 }
1282
1283 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
1284 dev->name, ring->curr, ring->dirty, done);
1285
1286 return done;
1287 }
1288
1289 static int ag71xx_poll(struct napi_struct *napi, int limit)
1290 {
1291 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
1292 struct net_device *dev = ag->dev;
1293 struct ag71xx_ring *rx_ring = &ag->rx_ring;
1294 int rx_ring_size = BIT(rx_ring->order);
1295 unsigned long flags;
1296 u32 status;
1297 int tx_done;
1298 int rx_done;
1299
1300 tx_done = ag71xx_tx_packets(ag, false);
1301
1302 DBG("%s: processing RX ring\n", dev->name);
1303 rx_done = ag71xx_rx_packets(ag, limit);
1304
1305 ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
1306
1307 if (rx_ring->buf[rx_ring->dirty % rx_ring_size].rx_buf == NULL)
1308 goto oom;
1309
1310 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
1311 if (unlikely(status & RX_STATUS_OF)) {
1312 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
1313 dev->stats.rx_fifo_errors++;
1314
1315 /* restart RX */
1316 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
1317 }
1318
1319 if (rx_done < limit) {
1320 if (status & RX_STATUS_PR)
1321 goto more;
1322
1323 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
1324 if (status & TX_STATUS_PS)
1325 goto more;
1326
1327 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
1328 dev->name, rx_done, tx_done, limit);
1329
1330 napi_complete(napi);
1331
1332 /* enable interrupts */
1333 spin_lock_irqsave(&ag->lock, flags);
1334 ag71xx_int_enable(ag, AG71XX_INT_POLL);
1335 spin_unlock_irqrestore(&ag->lock, flags);
1336 return rx_done;
1337 }
1338
1339 more:
1340 DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
1341 dev->name, rx_done, tx_done, limit);
1342 return limit;
1343
1344 oom:
1345 if (netif_msg_rx_err(ag))
1346 pr_info("%s: out of memory\n", dev->name);
1347
1348 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
1349 napi_complete(napi);
1350 return 0;
1351 }
1352
1353 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
1354 {
1355 struct net_device *dev = dev_id;
1356 struct ag71xx *ag = netdev_priv(dev);
1357 u32 status;
1358
1359 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
1360 ag71xx_dump_intr(ag, "raw", status);
1361
1362 if (unlikely(!status))
1363 return IRQ_NONE;
1364
1365 if (unlikely(status & AG71XX_INT_ERR)) {
1366 if (status & AG71XX_INT_TX_BE) {
1367 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
1368 dev_err(&dev->dev, "TX BUS error\n");
1369 }
1370 if (status & AG71XX_INT_RX_BE) {
1371 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
1372 dev_err(&dev->dev, "RX BUS error\n");
1373 }
1374 }
1375
1376 if (likely(status & AG71XX_INT_POLL)) {
1377 ag71xx_int_disable(ag, AG71XX_INT_POLL);
1378 DBG("%s: enable polling mode\n", dev->name);
1379 napi_schedule(&ag->napi);
1380 }
1381
1382 ag71xx_debugfs_update_int_stats(ag, status);
1383
1384 return IRQ_HANDLED;
1385 }
1386
1387 static int ag71xx_change_mtu(struct net_device *dev, int new_mtu)
1388 {
1389 struct ag71xx *ag = netdev_priv(dev);
1390
1391 dev->mtu = new_mtu;
1392 ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
1393 ag71xx_max_frame_len(dev->mtu));
1394
1395 return 0;
1396 }
1397
1398 static const struct net_device_ops ag71xx_netdev_ops = {
1399 .ndo_open = ag71xx_open,
1400 .ndo_stop = ag71xx_stop,
1401 .ndo_start_xmit = ag71xx_hard_start_xmit,
1402 .ndo_do_ioctl = ag71xx_do_ioctl,
1403 .ndo_tx_timeout = ag71xx_tx_timeout,
1404 .ndo_change_mtu = ag71xx_change_mtu,
1405 .ndo_set_mac_address = eth_mac_addr,
1406 .ndo_validate_addr = eth_validate_addr,
1407 };
1408
1409 static int ag71xx_probe(struct platform_device *pdev)
1410 {
1411 struct device_node *np = pdev->dev.of_node;
1412 struct net_device *dev;
1413 struct resource *res;
1414 struct ag71xx *ag;
1415 const void *mac_addr;
1416 u32 max_frame_len;
1417 int tx_size, err;
1418
1419 if (!np)
1420 return -ENODEV;
1421
1422 dev = devm_alloc_etherdev(&pdev->dev, sizeof(*ag));
1423 if (!dev)
1424 return -ENOMEM;
1425
1426 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1427 if (!res)
1428 return -EINVAL;
1429
1430 err = ag71xx_setup_gmac(np);
1431 if (err)
1432 return err;
1433
1434 SET_NETDEV_DEV(dev, &pdev->dev);
1435
1436 ag = netdev_priv(dev);
1437 ag->pdev = pdev;
1438 ag->dev = dev;
1439 ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1440 AG71XX_DEFAULT_MSG_ENABLE);
1441 spin_lock_init(&ag->lock);
1442
1443 ag->mac_reset = devm_reset_control_get_exclusive(&pdev->dev, "mac");
1444 if (IS_ERR(ag->mac_reset)) {
1445 dev_err(&pdev->dev, "missing mac reset\n");
1446 return PTR_ERR(ag->mac_reset);
1447 }
1448
1449 ag->mdio_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "mdio");
1450
1451 if (of_property_read_u32_array(np, "fifo-data", ag->fifodata, 3)) {
1452 if (of_device_is_compatible(np, "qca,ar9130-eth") ||
1453 of_device_is_compatible(np, "qca,ar7100-eth")) {
1454 ag->fifodata[0] = 0x0fff0000;
1455 ag->fifodata[1] = 0x00001fff;
1456 } else {
1457 ag->fifodata[0] = 0x0010ffff;
1458 ag->fifodata[1] = 0x015500aa;
1459 ag->fifodata[2] = 0x01f00140;
1460 }
1461 if (of_device_is_compatible(np, "qca,ar9130-eth"))
1462 ag->fifodata[2] = 0x00780fff;
1463 else if (of_device_is_compatible(np, "qca,ar7100-eth"))
1464 ag->fifodata[2] = 0x008001ff;
1465 }
1466
1467 if (of_property_read_u32_array(np, "pll-data", ag->plldata, 3))
1468 dev_dbg(&pdev->dev, "failed to read pll-data property\n");
1469
1470 if (of_property_read_u32_array(np, "pll-reg", ag->pllreg, 3))
1471 dev_dbg(&pdev->dev, "failed to read pll-reg property\n");
1472
1473 ag->pllregmap = syscon_regmap_lookup_by_phandle(np, "pll-handle");
1474 if (IS_ERR(ag->pllregmap)) {
1475 dev_dbg(&pdev->dev, "failed to read pll-handle property\n");
1476 ag->pllregmap = NULL;
1477 }
1478
1479 ag->mac_base = devm_ioremap_nocache(&pdev->dev, res->start,
1480 res->end - res->start + 1);
1481 if (!ag->mac_base)
1482 return -ENOMEM;
1483
1484 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1485 if (res) {
1486 ag->mii_base = devm_ioremap_nocache(&pdev->dev, res->start,
1487 res->end - res->start + 1);
1488 if (!ag->mii_base)
1489 return -ENOMEM;
1490 }
1491
1492 dev->irq = platform_get_irq(pdev, 0);
1493 err = devm_request_irq(&pdev->dev, dev->irq, ag71xx_interrupt,
1494 0x0, dev_name(&pdev->dev), dev);
1495 if (err) {
1496 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1497 return err;
1498 }
1499
1500 dev->netdev_ops = &ag71xx_netdev_ops;
1501 dev->ethtool_ops = &ag71xx_ethtool_ops;
1502
1503 INIT_DELAYED_WORK(&ag->restart_work, ag71xx_restart_work_func);
1504
1505 #if (LINUX_VERSION_CODE < KERNEL_VERSION(4,15,0))
1506 init_timer(&ag->oom_timer);
1507 ag->oom_timer.data = (unsigned long) dev;
1508 ag->oom_timer.function = ag71xx_oom_timer_handler;
1509 #else
1510 timer_setup(&ag->oom_timer, ag71xx_oom_timer_handler, 0);
1511 #endif
1512
1513 tx_size = AG71XX_TX_RING_SIZE_DEFAULT;
1514 ag->rx_ring.order = ag71xx_ring_size_order(AG71XX_RX_RING_SIZE_DEFAULT);
1515
1516 if (of_device_is_compatible(np, "qca,ar9340-eth") ||
1517 of_device_is_compatible(np, "qca,qca9530-eth") ||
1518 of_device_is_compatible(np, "qca,qca9550-eth") ||
1519 of_device_is_compatible(np, "qca,qca9560-eth"))
1520 ag->desc_pktlen_mask = SZ_16K - 1;
1521 else
1522 ag->desc_pktlen_mask = SZ_4K - 1;
1523
1524 if (ag->desc_pktlen_mask == SZ_16K - 1 &&
1525 !of_device_is_compatible(np, "qca,qca9550-eth") &&
1526 !of_device_is_compatible(np, "qca,qca9560-eth"))
1527 max_frame_len = ag->desc_pktlen_mask;
1528 else
1529 max_frame_len = 1540;
1530
1531 dev->min_mtu = 68;
1532 dev->max_mtu = max_frame_len - ag71xx_max_frame_len(0);
1533
1534 if (of_device_is_compatible(np, "qca,ar7240-eth") ||
1535 of_device_is_compatible(np, "qca,ar7241-eth") ||
1536 of_device_is_compatible(np, "qca,ar7242-eth") ||
1537 of_device_is_compatible(np, "qca,ar9330-eth") ||
1538 of_device_is_compatible(np, "qca,ar9340-eth") ||
1539 of_device_is_compatible(np, "qca,qca9530-eth") ||
1540 of_device_is_compatible(np, "qca,qca9550-eth") ||
1541 of_device_is_compatible(np, "qca,qca9560-eth"))
1542 ag->tx_hang_workaround = 1;
1543
1544 ag->rx_buf_offset = NET_SKB_PAD;
1545 if (!of_device_is_compatible(np, "qca,ar7100-eth") &&
1546 !of_device_is_compatible(np, "qca,ar9130-eth"))
1547 ag->rx_buf_offset += NET_IP_ALIGN;
1548
1549 if (of_device_is_compatible(np, "qca,ar7100-eth")) {
1550 ag->tx_ring.desc_split = AG71XX_TX_RING_SPLIT;
1551 tx_size *= AG71XX_TX_RING_DS_PER_PKT;
1552 }
1553 ag->tx_ring.order = ag71xx_ring_size_order(tx_size);
1554
1555 ag->stop_desc = dmam_alloc_coherent(&pdev->dev,
1556 sizeof(struct ag71xx_desc),
1557 &ag->stop_desc_dma, GFP_KERNEL);
1558 if (!ag->stop_desc)
1559 return -ENOMEM;
1560
1561 ag->stop_desc->data = 0;
1562 ag->stop_desc->ctrl = 0;
1563 ag->stop_desc->next = (u32) ag->stop_desc_dma;
1564
1565 mac_addr = of_get_mac_address(np);
1566 if (mac_addr)
1567 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
1568 if (!mac_addr || !is_valid_ether_addr(dev->dev_addr)) {
1569 dev_err(&pdev->dev, "invalid MAC address, using random address\n");
1570 eth_random_addr(dev->dev_addr);
1571 }
1572
1573 ag->phy_if_mode = of_get_phy_mode(np);
1574 if (ag->phy_if_mode < 0) {
1575 dev_err(&pdev->dev, "missing phy-mode property in DT\n");
1576 return ag->phy_if_mode;
1577 }
1578
1579 if (of_property_read_u32(np, "qca,mac-idx", &ag->mac_idx))
1580 ag->mac_idx = -1;
1581 if (ag->mii_base)
1582 switch (ag->mac_idx) {
1583 case 0:
1584 ath79_mii0_ctrl_set_if(ag);
1585 break;
1586 case 1:
1587 ath79_mii1_ctrl_set_if(ag);
1588 break;
1589 default:
1590 break;
1591 }
1592
1593 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1594
1595 ag71xx_dump_regs(ag);
1596
1597 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, 0);
1598
1599 ag71xx_hw_init(ag);
1600
1601 ag71xx_dump_regs(ag);
1602
1603 /*
1604 * populate current node to register mdio-bus as a subdevice.
1605 * the mdio bus works independently on ar7241 and later chips
1606 * and we need to load mdio1 before gmac0, which can be done
1607 * by adding a "simple-mfd" compatible to gmac node. The
1608 * following code checks OF_POPULATED_BUS flag before populating
1609 * to avoid duplicated population.
1610 */
1611 if (!of_node_check_flag(np, OF_POPULATED_BUS)) {
1612 err = of_platform_populate(np, NULL, NULL, &pdev->dev);
1613 if (err)
1614 return err;
1615 }
1616
1617 err = ag71xx_phy_connect(ag);
1618 if (err)
1619 return err;
1620
1621 err = ag71xx_debugfs_init(ag);
1622 if (err)
1623 goto err_phy_disconnect;
1624
1625 platform_set_drvdata(pdev, dev);
1626
1627 err = register_netdev(dev);
1628 if (err) {
1629 dev_err(&pdev->dev, "unable to register net device\n");
1630 platform_set_drvdata(pdev, NULL);
1631 ag71xx_debugfs_exit(ag);
1632 goto err_phy_disconnect;
1633 }
1634
1635 pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d, mode: %s\n",
1636 dev->name, (unsigned long) ag->mac_base, dev->irq,
1637 phy_modes(ag->phy_if_mode));
1638
1639 return 0;
1640
1641 err_phy_disconnect:
1642 ag71xx_phy_disconnect(ag);
1643 return err;
1644 }
1645
1646 static int ag71xx_remove(struct platform_device *pdev)
1647 {
1648 struct net_device *dev = platform_get_drvdata(pdev);
1649 struct ag71xx *ag;
1650
1651 if (!dev)
1652 return 0;
1653
1654 ag = netdev_priv(dev);
1655 ag71xx_debugfs_exit(ag);
1656 ag71xx_phy_disconnect(ag);
1657 unregister_netdev(dev);
1658 platform_set_drvdata(pdev, NULL);
1659 return 0;
1660 }
1661
1662 static const struct of_device_id ag71xx_match[] = {
1663 { .compatible = "qca,ar7100-eth" },
1664 { .compatible = "qca,ar7240-eth" },
1665 { .compatible = "qca,ar7241-eth" },
1666 { .compatible = "qca,ar7242-eth" },
1667 { .compatible = "qca,ar9130-eth" },
1668 { .compatible = "qca,ar9330-eth" },
1669 { .compatible = "qca,ar9340-eth" },
1670 { .compatible = "qca,qca9530-eth" },
1671 { .compatible = "qca,qca9550-eth" },
1672 { .compatible = "qca,qca9560-eth" },
1673 {}
1674 };
1675
1676 static struct platform_driver ag71xx_driver = {
1677 .probe = ag71xx_probe,
1678 .remove = ag71xx_remove,
1679 .driver = {
1680 .name = AG71XX_DRV_NAME,
1681 .of_match_table = ag71xx_match,
1682 }
1683 };
1684
1685 static int __init ag71xx_module_init(void)
1686 {
1687 int ret;
1688
1689 ret = ag71xx_debugfs_root_init();
1690 if (ret)
1691 goto err_out;
1692
1693 ret = platform_driver_register(&ag71xx_driver);
1694 if (ret)
1695 goto err_debugfs_exit;
1696
1697 return 0;
1698
1699 err_debugfs_exit:
1700 ag71xx_debugfs_root_exit();
1701 err_out:
1702 return ret;
1703 }
1704
1705 static void __exit ag71xx_module_exit(void)
1706 {
1707 platform_driver_unregister(&ag71xx_driver);
1708 ag71xx_debugfs_root_exit();
1709 }
1710
1711 module_init(ag71xx_module_init);
1712 module_exit(ag71xx_module_exit);
1713
1714 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1715 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1716 MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
1717 MODULE_LICENSE("GPL v2");
1718 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
OpenWrt Source Repository