target/linux/ath79/patches-4.14/0021-MIPS-ath79-turn-pci-ar724x-driver-into-a-pure-OF-dri.patch

   1 From 0e7f36bfd68401e8c42933e7f770f270497bb9a8 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <john@phrozen.org>
   3 Date: Tue, 6 Mar 2018 09:23:25 +0100
   4 Subject: [PATCH 21/27] MIPS: ath79: turn pci-ar724x driver into a pure OF
   5  driver
   6
   7 Signed-off-by: John Crispin <john@phrozen.org>
   8 ---
   9  arch/mips/pci/pci-ar724x.c | 86 +++++++++++++++++++++-------------------------
  10  1 file changed, 40 insertions(+), 46 deletions(-)
  11
  12 diff --git a/arch/mips/pci/pci-ar724x.c b/arch/mips/pci/pci-ar724x.c
  13 index 64b58cc48a91..7eb9b0999c8c 100644
  14 --- a/arch/mips/pci/pci-ar724x.c
  15 +++ b/arch/mips/pci/pci-ar724x.c
  16 @@ -14,8 +14,11 @@
  17  #include <linux/init.h>
  18  #include <linux/delay.h>
  19  #include <linux/platform_device.h>
  20 +#include <linux/irqchip/chained_irq.h>
  21  #include <asm/mach-ath79/ath79.h>
  22  #include <asm/mach-ath79/ar71xx_regs.h>
  23 +#include <linux/of_irq.h>
  24 +#include <linux/of_pci.h>
  25
  26  #define AR724X_PCI_REG_APP             0x00
  27  #define AR724X_PCI_REG_RESET           0x18
  28 @@ -45,17 +48,20 @@ struct ar724x_pci_controller {
  29         void __iomem *crp_base;
  30
  31         int irq;
  32 -       int irq_base;
  33
  34         bool link_up;
  35         bool bar0_is_cached;
  36         u32  bar0_value;
  37
  38 +       struct device_node *np;
  39         struct pci_controller pci_controller;
  40 +       struct irq_domain *domain;
  41         struct resource io_res;
  42         struct resource mem_res;
  43  };
  44
  45 +static struct irq_chip ar724x_pci_irq_chip;
  46 +
  47  static inline bool ar724x_pci_check_link(struct ar724x_pci_controller *apc)
  48  {
  49         u32 reset;
  50 @@ -231,35 +237,31 @@ static struct pci_ops ar724x_pci_ops = {
  51
  52  static void ar724x_pci_irq_handler(struct irq_desc *desc)
  53  {
  54 -       struct ar724x_pci_controller *apc;
  55 -       void __iomem *base;
  56 +       struct irq_chip *chip = irq_desc_get_chip(desc);
  57 +       struct ar724x_pci_controller *apc = irq_desc_get_handler_data(desc);
  58         u32 pending;
  59
  60 -       apc = irq_desc_get_handler_data(desc);
  61 -       base = apc->ctrl_base;
  62 -
  63 -       pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) &
  64 -                 __raw_readl(base + AR724X_PCI_REG_INT_MASK);
  65 +       chained_irq_enter(chip, desc);
  66 +       pending = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_INT_STATUS) &
  67 +                 __raw_readl(apc->ctrl_base + AR724X_PCI_REG_INT_MASK);
  68
  69         if (pending & AR724X_PCI_INT_DEV0)
  70 -               generic_handle_irq(apc->irq_base + 0);
  71 -
  72 +               generic_handle_irq(irq_linear_revmap(apc->domain, 1));
  73         else
  74                 spurious_interrupt();
  75 +       chained_irq_exit(chip, desc);
  76  }
  77
  78  static void ar724x_pci_irq_unmask(struct irq_data *d)
  79  {
  80         struct ar724x_pci_controller *apc;
  81         void __iomem *base;
  82 -       int offset;
  83         u32 t;
  84
  85         apc = irq_data_get_irq_chip_data(d);
  86         base = apc->ctrl_base;
  87 -       offset = apc->irq_base - d->irq;
  88
  89 -       switch (offset) {
  90 +       switch (irq_linear_revmap(apc->domain, d->irq)) {
  91         case 0:
  92                 t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
  93                 __raw_writel(t | AR724X_PCI_INT_DEV0,
  94 @@ -273,14 +275,12 @@ static void ar724x_pci_irq_mask(struct irq_data *d)
  95  {
  96         struct ar724x_pci_controller *apc;
  97         void __iomem *base;
  98 -       int offset;
  99         u32 t;
 100
 101         apc = irq_data_get_irq_chip_data(d);
 102         base = apc->ctrl_base;
 103 -       offset = apc->irq_base - d->irq;
 104
 105 -       switch (offset) {
 106 +       switch (irq_linear_revmap(apc->domain, d->irq)) {
 107         case 0:
 108                 t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
 109                 __raw_writel(t & ~AR724X_PCI_INT_DEV0,
 110 @@ -305,26 +305,32 @@ static struct irq_chip ar724x_pci_irq_chip = {
 111         .irq_mask_ack   = ar724x_pci_irq_mask,
 112  };
 113
 114 +static int ar724x_pci_irq_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
 115 +{
 116 +       struct ar724x_pci_controller *apc = d->host_data;
 117 +
 118 +       irq_set_chip_and_handler(irq, &ar724x_pci_irq_chip, handle_level_irq);
 119 +       irq_set_chip_data(irq, apc);
 120 +
 121 +       return 0;
 122 +}
 123 +
 124 +static const struct irq_domain_ops ar724x_pci_domain_ops = {
 125 +       .xlate = irq_domain_xlate_onecell,
 126 +       .map = ar724x_pci_irq_map,
 127 +};
 128 +
 129  static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc,
 130                                 int id)
 131  {
 132         void __iomem *base;
 133 -       int i;
 134
 135         base = apc->ctrl_base;
 136
 137         __raw_writel(0, base + AR724X_PCI_REG_INT_MASK);
 138         __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);
 139
 140 -       apc->irq_base = ATH79_PCI_IRQ_BASE + (id * AR724X_PCI_IRQ_COUNT);
 141 -
 142 -       for (i = apc->irq_base;
 143 -            i < apc->irq_base + AR724X_PCI_IRQ_COUNT; i++) {
 144 -               irq_set_chip_and_handler(i, &ar724x_pci_irq_chip,
 145 -                                        handle_level_irq);
 146 -               irq_set_chip_data(i, apc);
 147 -       }
 148 -
 149 +       apc->domain = irq_domain_add_linear(apc->np, 2, &ar724x_pci_domain_ops, apc);
 150         irq_set_chained_handler_and_data(apc->irq, ar724x_pci_irq_handler,
 151                                          apc);
 152  }
 153 @@ -394,29 +400,11 @@ static int ar724x_pci_probe(struct platform_device *pdev)
 154         if (apc->irq < 0)
 155                 return -EINVAL;
 156
 157 -       res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base");
 158 -       if (!res)
 159 -               return -EINVAL;
 160 -
 161 -       apc->io_res.parent = res;
 162 -       apc->io_res.name = "PCI IO space";
 163 -       apc->io_res.start = res->start;
 164 -       apc->io_res.end = res->end;
 165 -       apc->io_res.flags = IORESOURCE_IO;
 166 -
 167 -       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base");
 168 -       if (!res)
 169 -               return -EINVAL;
 170 -
 171 -       apc->mem_res.parent = res;
 172 -       apc->mem_res.name = "PCI memory space";
 173 -       apc->mem_res.start = res->start;
 174 -       apc->mem_res.end = res->end;
 175 -       apc->mem_res.flags = IORESOURCE_MEM;
 176 -
 177 +       apc->np = pdev->dev.of_node;
 178         apc->pci_controller.pci_ops = &ar724x_pci_ops;
 179         apc->pci_controller.io_resource = &apc->io_res;
 180         apc->pci_controller.mem_resource = &apc->mem_res;
 181 +       pci_load_of_ranges(&apc->pci_controller, pdev->dev.of_node);
 182
 183         /*
 184          * Do the full PCIE Root Complex Initialization Sequence if the PCIe
 185 @@ -438,10 +426,16 @@ static int ar724x_pci_probe(struct platform_device *pdev)
 186         return 0;
 187  }
 188
 189 +static const struct of_device_id ar724x_pci_ids[] = {
 190 +       { .compatible = "qcom,ar7240-pci" },
 191 +       {},
 192 +};
 193 +
 194  static struct platform_driver ar724x_pci_driver = {
 195         .probe = ar724x_pci_probe,
 196         .driver = {
 197                 .name = "ar724x-pci",
 198 +               .of_match_table = of_match_ptr(ar724x_pci_ids),
 199         },
 200  };
 201
 202 --
 203 2.11.0
 204