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kernel: bump 4.14 to 4.14.43 for 18.06
[openwrt/openwrt.git] / target / linux / ath79 / patches-4.14 / 0022-MIPS-ath79-drop-pci.c.patch
1 From f4128f3224df2309262ef8d1275d928717ebefd0 Mon Sep 17 00:00:00 2001
2 From: John Crispin <john@phrozen.org>
3 Date: Tue, 6 Mar 2018 09:21:46 +0100
4 Subject: [PATCH 22/27] MIPS: ath79: drop pci.c
5
6 This patch drops pci.c fromt he ath79 folder and moves the the pcibios
7 callbacks to a new fixup file.
8
9 Signed-off-by: John Crispin <john@phrozen.org>
10 ---
11 arch/mips/ath79/Makefile | 1 -
12 arch/mips/ath79/pci.c | 285 --------------------------------------------
13 arch/mips/pci/Makefile | 1 +
14 arch/mips/pci/fixup-ath79.c | 21 ++++
15 4 files changed, 22 insertions(+), 286 deletions(-)
16 delete mode 100644 arch/mips/ath79/pci.c
17 create mode 100644 arch/mips/pci/fixup-ath79.c
18
19 --- a/arch/mips/ath79/Makefile
20 +++ b/arch/mips/ath79/Makefile
21 @@ -11,7 +11,6 @@
22 obj-y := prom.o setup.o irq.o common.o clock.o
23
24 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
25 -obj-$(CONFIG_PCI) += pci.o
26
27 #
28 # Devices
29 --- a/arch/mips/ath79/pci.c
30 +++ /dev/null
31 @@ -1,285 +0,0 @@
32 -/*
33 - * Atheros AR71XX/AR724X specific PCI setup code
34 - *
35 - * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
36 - * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
37 - * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
38 - *
39 - * Parts of this file are based on Atheros' 2.6.15 BSP
40 - *
41 - * This program is free software; you can redistribute it and/or modify it
42 - * under the terms of the GNU General Public License version 2 as published
43 - * by the Free Software Foundation.
44 - */
45 -
46 -#include <linux/init.h>
47 -#include <linux/pci.h>
48 -#include <linux/resource.h>
49 -#include <linux/platform_device.h>
50 -#include <asm/mach-ath79/ar71xx_regs.h>
51 -#include <asm/mach-ath79/ath79.h>
52 -#include <asm/mach-ath79/irq.h>
53 -#include "pci.h"
54 -
55 -static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev);
56 -static const struct ath79_pci_irq *ath79_pci_irq_map;
57 -static unsigned ath79_pci_nr_irqs;
58 -
59 -static const struct ath79_pci_irq ar71xx_pci_irq_map[] = {
60 - {
61 - .slot = 17,
62 - .pin = 1,
63 - .irq = ATH79_PCI_IRQ(0),
64 - }, {
65 - .slot = 18,
66 - .pin = 1,
67 - .irq = ATH79_PCI_IRQ(1),
68 - }, {
69 - .slot = 19,
70 - .pin = 1,
71 - .irq = ATH79_PCI_IRQ(2),
72 - }
73 -};
74 -
75 -static const struct ath79_pci_irq ar724x_pci_irq_map[] = {
76 - {
77 - .slot = 0,
78 - .pin = 1,
79 - .irq = ATH79_PCI_IRQ(0),
80 - }
81 -};
82 -
83 -static const struct ath79_pci_irq qca955x_pci_irq_map[] = {
84 - {
85 - .bus = 0,
86 - .slot = 0,
87 - .pin = 1,
88 - .irq = ATH79_PCI_IRQ(0),
89 - },
90 - {
91 - .bus = 1,
92 - .slot = 0,
93 - .pin = 1,
94 - .irq = ATH79_PCI_IRQ(1),
95 - },
96 -};
97 -
98 -int pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
99 -{
100 - int irq = -1;
101 - int i;
102 -
103 - if (ath79_pci_nr_irqs == 0 ||
104 - ath79_pci_irq_map == NULL) {
105 - if (soc_is_ar71xx()) {
106 - ath79_pci_irq_map = ar71xx_pci_irq_map;
107 - ath79_pci_nr_irqs = ARRAY_SIZE(ar71xx_pci_irq_map);
108 - } else if (soc_is_ar724x() ||
109 - soc_is_ar9342() ||
110 - soc_is_ar9344()) {
111 - ath79_pci_irq_map = ar724x_pci_irq_map;
112 - ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map);
113 - } else if (soc_is_qca955x()) {
114 - ath79_pci_irq_map = qca955x_pci_irq_map;
115 - ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map);
116 - } else if (soc_is_qca956x()) {
117 - ath79_pci_irq_map = qca956x_pci_irq_map;
118 - ath79_pci_nr_irqs = ARRAY_SIZE(qca956x_pci_irq_map);
119 - } else {
120 - pr_crit("pci %s: invalid irq map\n",
121 - pci_name((struct pci_dev *) dev));
122 - return irq;
123 - }
124 - }
125 -
126 - for (i = 0; i < ath79_pci_nr_irqs; i++) {
127 - const struct ath79_pci_irq *entry;
128 -
129 - entry = &ath79_pci_irq_map[i];
130 - if (entry->bus == dev->bus->number &&
131 - entry->slot == slot &&
132 - entry->pin == pin) {
133 - irq = entry->irq;
134 - break;
135 - }
136 - }
137 -
138 - if (irq < 0)
139 - pr_crit("pci %s: no irq found for pin %u\n",
140 - pci_name((struct pci_dev *) dev), pin);
141 - else
142 - pr_info("pci %s: using irq %d for pin %u\n",
143 - pci_name((struct pci_dev *) dev), irq, pin);
144 -
145 - return irq;
146 -}
147 -
148 -int pcibios_plat_dev_init(struct pci_dev *dev)
149 -{
150 - if (ath79_pci_plat_dev_init)
151 - return ath79_pci_plat_dev_init(dev);
152 -
153 - return 0;
154 -}
155 -
156 -void __init ath79_pci_set_irq_map(unsigned nr_irqs,
157 - const struct ath79_pci_irq *map)
158 -{
159 - ath79_pci_nr_irqs = nr_irqs;
160 - ath79_pci_irq_map = map;
161 -}
162 -
163 -void __init ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev))
164 -{
165 - ath79_pci_plat_dev_init = func;
166 -}
167 -
168 -static struct platform_device *
169 -ath79_register_pci_ar71xx(void)
170 -{
171 - struct platform_device *pdev;
172 - struct resource res[4];
173 -
174 - memset(res, 0, sizeof(res));
175 -
176 - res[0].name = "cfg_base";
177 - res[0].flags = IORESOURCE_MEM;
178 - res[0].start = AR71XX_PCI_CFG_BASE;
179 - res[0].end = AR71XX_PCI_CFG_BASE + AR71XX_PCI_CFG_SIZE - 1;
180 -
181 - res[1].flags = IORESOURCE_IRQ;
182 - res[1].start = ATH79_CPU_IRQ(2);
183 - res[1].end = ATH79_CPU_IRQ(2);
184 -
185 - res[2].name = "io_base";
186 - res[2].flags = IORESOURCE_IO;
187 - res[2].start = 0;
188 - res[2].end = 0;
189 -
190 - res[3].name = "mem_base";
191 - res[3].flags = IORESOURCE_MEM;
192 - res[3].start = AR71XX_PCI_MEM_BASE;
193 - res[3].end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1;
194 -
195 - pdev = platform_device_register_simple("ar71xx-pci", -1,
196 - res, ARRAY_SIZE(res));
197 - return pdev;
198 -}
199 -
200 -static struct platform_device *
201 -ath79_register_pci_ar724x(int id,
202 - unsigned long cfg_base,
203 - unsigned long ctrl_base,
204 - unsigned long crp_base,
205 - unsigned long mem_base,
206 - unsigned long mem_size,
207 - unsigned long io_base,
208 - int irq)
209 -{
210 - struct platform_device *pdev;
211 - struct resource res[6];
212 -
213 - memset(res, 0, sizeof(res));
214 -
215 - res[0].name = "cfg_base";
216 - res[0].flags = IORESOURCE_MEM;
217 - res[0].start = cfg_base;
218 - res[0].end = cfg_base + AR724X_PCI_CFG_SIZE - 1;
219 -
220 - res[1].name = "ctrl_base";
221 - res[1].flags = IORESOURCE_MEM;
222 - res[1].start = ctrl_base;
223 - res[1].end = ctrl_base + AR724X_PCI_CTRL_SIZE - 1;
224 -
225 - res[2].flags = IORESOURCE_IRQ;
226 - res[2].start = irq;
227 - res[2].end = irq;
228 -
229 - res[3].name = "mem_base";
230 - res[3].flags = IORESOURCE_MEM;
231 - res[3].start = mem_base;
232 - res[3].end = mem_base + mem_size - 1;
233 -
234 - res[4].name = "io_base";
235 - res[4].flags = IORESOURCE_IO;
236 - res[4].start = io_base;
237 - res[4].end = io_base;
238 -
239 - res[5].name = "crp_base";
240 - res[5].flags = IORESOURCE_MEM;
241 - res[5].start = crp_base;
242 - res[5].end = crp_base + AR724X_PCI_CRP_SIZE - 1;
243 -
244 - pdev = platform_device_register_simple("ar724x-pci", id,
245 - res, ARRAY_SIZE(res));
246 - return pdev;
247 -}
248 -
249 -int __init ath79_register_pci(void)
250 -{
251 - struct platform_device *pdev = NULL;
252 -
253 - if (soc_is_ar71xx()) {
254 - pdev = ath79_register_pci_ar71xx();
255 - } else if (soc_is_ar724x()) {
256 - pdev = ath79_register_pci_ar724x(-1,
257 - AR724X_PCI_CFG_BASE,
258 - AR724X_PCI_CTRL_BASE,
259 - AR724X_PCI_CRP_BASE,
260 - AR724X_PCI_MEM_BASE,
261 - AR724X_PCI_MEM_SIZE,
262 - 0,
263 - ATH79_CPU_IRQ(2));
264 - } else if (soc_is_ar9342() ||
265 - soc_is_ar9344()) {
266 - u32 bootstrap;
267 -
268 - bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
269 - if ((bootstrap & AR934X_BOOTSTRAP_PCIE_RC) == 0)
270 - return -ENODEV;
271 -
272 - pdev = ath79_register_pci_ar724x(-1,
273 - AR724X_PCI_CFG_BASE,
274 - AR724X_PCI_CTRL_BASE,
275 - AR724X_PCI_CRP_BASE,
276 - AR724X_PCI_MEM_BASE,
277 - AR724X_PCI_MEM_SIZE,
278 - 0,
279 - ATH79_IP2_IRQ(0));
280 - } else if (soc_is_qca9558()) {
281 - pdev = ath79_register_pci_ar724x(0,
282 - QCA955X_PCI_CFG_BASE0,
283 - QCA955X_PCI_CTRL_BASE0,
284 - QCA955X_PCI_CRP_BASE0,
285 - QCA955X_PCI_MEM_BASE0,
286 - QCA955X_PCI_MEM_SIZE,
287 - 0,
288 - ATH79_IP2_IRQ(0));
289 -
290 - pdev = ath79_register_pci_ar724x(1,
291 - QCA955X_PCI_CFG_BASE1,
292 - QCA955X_PCI_CTRL_BASE1,
293 - QCA955X_PCI_CRP_BASE1,
294 - QCA955X_PCI_MEM_BASE1,
295 - QCA955X_PCI_MEM_SIZE,
296 - 1,
297 - ATH79_IP3_IRQ(2));
298 - } else if (soc_is_qca956x()) {
299 - pdev = ath79_register_pci_ar724x(0,
300 - QCA956X_PCI_CFG_BASE1,
301 - QCA956X_PCI_CTRL_BASE1,
302 - QCA956X_PCI_CRP_BASE1,
303 - QCA956X_PCI_MEM_BASE1,
304 - QCA956X_PCI_MEM_SIZE,
305 - 1,
306 - ATH79_IP3_IRQ(2));
307 - } else {
308 - /* No PCI support */
309 - return -ENODEV;
310 - }
311 -
312 - if (!pdev)
313 - pr_err("unable to register PCI controller device\n");
314 -
315 - return pdev ? 0 : -ENODEV;
316 -}
317 --- a/arch/mips/pci/Makefile
318 +++ b/arch/mips/pci/Makefile
319 @@ -29,6 +29,7 @@ obj-$(CONFIG_MIPS_PCI_VIRTIO) += pci-vir
320 #
321 # These are still pretty much in the old state, watch, go blind.
322 #
323 +obj-$(CONFIG_ATH79) += fixup-ath79.o
324 obj-$(CONFIG_LASAT) += pci-lasat.o
325 obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o
326 obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o
327 --- /dev/null
328 +++ b/arch/mips/pci/fixup-ath79.c
329 @@ -0,0 +1,21 @@
330 +/*
331 + * Copyright (C) 2018 John Crispin <john@phrozen.org>
332 + *
333 + * This program is free software; you can redistribute it and/or modify it
334 + * under the terms of the GNU General Public License version 2 as published
335 + * by the Free Software Foundation.
336 + */
337 +
338 +#include <linux/pci.h>
339 +//#include <linux/of_irq.h>
340 +#include <linux/of_pci.h>
341 +
342 +int pcibios_plat_dev_init(struct pci_dev *dev)
343 +{
344 + return PCIBIOS_SUCCESSFUL;
345 +}
346 +
347 +int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
348 +{
349 + return of_irq_parse_and_map_pci(dev, slot, pin);
350 +}
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