target/linux/ath79/patches-4.14/0025-MIPS-ath79-drop-irq.c.patch

   1 From 08b9cad7da5d981d595fe6d76e9675f85e23e688 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <john@phrozen.org>
   3 Date: Tue, 6 Mar 2018 09:57:15 +0100
   4 Subject: [PATCH 25/27] MIPS: ath79: drop irq.c
   5
   6 all IRQ init code will flow via OF based irq chips.
   7
   8 Signed-off-by: John Crispin <john@phrozen.org>
   9 ---
  10  arch/mips/ath79/Makefile |   2 +-
  11  arch/mips/ath79/irq.c    | 285 -----------------------------------------------
  12  arch/mips/ath79/setup.c  |   6 +
  13  3 files changed, 7 insertions(+), 286 deletions(-)
  14  delete mode 100644 arch/mips/ath79/irq.c
  15
  16 diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile
  17 index 783369bc1c5b..bd0c9b8b1b5b 100644
  18 --- a/arch/mips/ath79/Makefile
  19 +++ b/arch/mips/ath79/Makefile
  20 @@ -8,7 +8,7 @@
  21  # under the terms of the GNU General Public License version 2 as published
  22  # by the Free Software Foundation.
  23
  24 -obj-y  := prom.o setup.o irq.o common.o clock.o
  25 +obj-y  := prom.o setup.o common.o clock.o
  26
  27  obj-$(CONFIG_EARLY_PRINTK)             += early_printk.o
  28
  29 diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c
  30 deleted file mode 100644
  31 index 58d17ef6f58f..000000000000
  32 --- a/arch/mips/ath79/irq.c
  33 +++ /dev/null
  34 @@ -1,285 +0,0 @@
  35 -/*
  36 - *  Atheros AR71xx/AR724x/AR913x specific interrupt handling
  37 - *
  38 - *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
  39 - *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
  40 - *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  41 - *
  42 - *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
  43 - *
  44 - *  This program is free software; you can redistribute it and/or modify it
  45 - *  under the terms of the GNU General Public License version 2 as published
  46 - *  by the Free Software Foundation.
  47 - */
  48 -
  49 -#include <linux/kernel.h>
  50 -#include <linux/init.h>
  51 -#include <linux/interrupt.h>
  52 -#include <linux/irqchip.h>
  53 -#include <linux/of_irq.h>
  54 -
  55 -#include <asm/irq_cpu.h>
  56 -#include <asm/mipsregs.h>
  57 -
  58 -#include <asm/mach-ath79/ath79.h>
  59 -#include <asm/mach-ath79/ar71xx_regs.h>
  60 -#include "common.h"
  61 -#include "machtypes.h"
  62 -
  63 -
  64 -static void ar934x_ip2_irq_dispatch(struct irq_desc *desc)
  65 -{
  66 -       u32 status;
  67 -
  68 -       status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS);
  69 -
  70 -       if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) {
  71 -               ath79_ddr_wb_flush(3);
  72 -               generic_handle_irq(ATH79_IP2_IRQ(0));
  73 -       } else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) {
  74 -               ath79_ddr_wb_flush(4);
  75 -               generic_handle_irq(ATH79_IP2_IRQ(1));
  76 -       } else {
  77 -               spurious_interrupt();
  78 -       }
  79 -}
  80 -
  81 -static void ar934x_ip2_irq_init(void)
  82 -{
  83 -       int i;
  84 -
  85 -       for (i = ATH79_IP2_IRQ_BASE;
  86 -            i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
  87 -               irq_set_chip_and_handler(i, &dummy_irq_chip,
  88 -                                        handle_level_irq);
  89 -
  90 -       irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
  91 -}
  92 -
  93 -static void qca953x_ip2_irq_dispatch(struct irq_desc *desc)
  94 -{
  95 -       u32 status;
  96 -
  97 -       status = ath79_reset_rr(QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS);
  98 -
  99 -       if (status & QCA953X_PCIE_WMAC_INT_PCIE_ALL) {
 100 -               ath79_ddr_wb_flush(3);
 101 -               generic_handle_irq(ATH79_IP2_IRQ(0));
 102 -       } else if (status & QCA953X_PCIE_WMAC_INT_WMAC_ALL) {
 103 -               ath79_ddr_wb_flush(4);
 104 -               generic_handle_irq(ATH79_IP2_IRQ(1));
 105 -       } else {
 106 -               spurious_interrupt();
 107 -       }
 108 -}
 109 -
 110 -static void qca953x_irq_init(void)
 111 -{
 112 -       int i;
 113 -
 114 -       for (i = ATH79_IP2_IRQ_BASE;
 115 -            i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
 116 -               irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
 117 -
 118 -       irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch);
 119 -}
 120 -
 121 -static void qca955x_ip2_irq_dispatch(struct irq_desc *desc)
 122 -{
 123 -       u32 status;
 124 -
 125 -       status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
 126 -       status &= QCA955X_EXT_INT_PCIE_RC1_ALL | QCA955X_EXT_INT_WMAC_ALL;
 127 -
 128 -       if (status == 0) {
 129 -               spurious_interrupt();
 130 -               return;
 131 -       }
 132 -
 133 -       if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) {
 134 -               /* TODO: flush DDR? */
 135 -               generic_handle_irq(ATH79_IP2_IRQ(0));
 136 -       }
 137 -
 138 -       if (status & QCA955X_EXT_INT_WMAC_ALL) {
 139 -               /* TODO: flush DDR? */
 140 -               generic_handle_irq(ATH79_IP2_IRQ(1));
 141 -       }
 142 -}
 143 -
 144 -static void qca955x_ip3_irq_dispatch(struct irq_desc *desc)
 145 -{
 146 -       u32 status;
 147 -
 148 -       status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
 149 -       status &= QCA955X_EXT_INT_PCIE_RC2_ALL |
 150 -                 QCA955X_EXT_INT_USB1 |
 151 -                 QCA955X_EXT_INT_USB2;
 152 -
 153 -       if (status == 0) {
 154 -               spurious_interrupt();
 155 -               return;
 156 -       }
 157 -
 158 -       if (status & QCA955X_EXT_INT_USB1) {
 159 -               /* TODO: flush DDR? */
 160 -               generic_handle_irq(ATH79_IP3_IRQ(0));
 161 -       }
 162 -
 163 -       if (status & QCA955X_EXT_INT_USB2) {
 164 -               /* TODO: flush DDR? */
 165 -               generic_handle_irq(ATH79_IP3_IRQ(1));
 166 -       }
 167 -
 168 -       if (status & QCA955X_EXT_INT_PCIE_RC2_ALL) {
 169 -               /* TODO: flush DDR? */
 170 -               generic_handle_irq(ATH79_IP3_IRQ(2));
 171 -       }
 172 -}
 173 -
 174 -static void qca955x_irq_init(void)
 175 -{
 176 -       int i;
 177 -
 178 -       for (i = ATH79_IP2_IRQ_BASE;
 179 -            i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
 180 -               irq_set_chip_and_handler(i, &dummy_irq_chip,
 181 -                                        handle_level_irq);
 182 -
 183 -       irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch);
 184 -
 185 -       for (i = ATH79_IP3_IRQ_BASE;
 186 -            i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
 187 -               irq_set_chip_and_handler(i, &dummy_irq_chip,
 188 -                                        handle_level_irq);
 189 -
 190 -       irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
 191 -}
 192 -
 193 -static void qca956x_ip2_irq_dispatch(struct irq_desc *desc)
 194 -{
 195 -       u32 status;
 196 -
 197 -       status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS);
 198 -       status &= QCA956X_EXT_INT_PCIE_RC1_ALL | QCA956X_EXT_INT_WMAC_ALL;
 199 -
 200 -       if (status == 0) {
 201 -               spurious_interrupt();
 202 -               return;
 203 -       }
 204 -
 205 -       if (status & QCA956X_EXT_INT_PCIE_RC1_ALL) {
 206 -               /* TODO: flush DDR? */
 207 -               generic_handle_irq(ATH79_IP2_IRQ(0));
 208 -       }
 209 -
 210 -       if (status & QCA956X_EXT_INT_WMAC_ALL) {
 211 -               /* TODO: flsuh DDR? */
 212 -               generic_handle_irq(ATH79_IP2_IRQ(1));
 213 -       }
 214 -}
 215 -
 216 -static void qca956x_ip3_irq_dispatch(struct irq_desc *desc)
 217 -{
 218 -       u32 status;
 219 -
 220 -       status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS);
 221 -       status &= QCA956X_EXT_INT_PCIE_RC2_ALL |
 222 -                 QCA956X_EXT_INT_USB1 | QCA956X_EXT_INT_USB2;
 223 -
 224 -       if (status == 0) {
 225 -               spurious_interrupt();
 226 -               return;
 227 -       }
 228 -
 229 -       if (status & QCA956X_EXT_INT_USB1) {
 230 -               /* TODO: flush DDR? */
 231 -               generic_handle_irq(ATH79_IP3_IRQ(0));
 232 -       }
 233 -
 234 -       if (status & QCA956X_EXT_INT_USB2) {
 235 -               /* TODO: flush DDR? */
 236 -               generic_handle_irq(ATH79_IP3_IRQ(1));
 237 -       }
 238 -
 239 -       if (status & QCA956X_EXT_INT_PCIE_RC2_ALL) {
 240 -               /* TODO: flush DDR? */
 241 -               generic_handle_irq(ATH79_IP3_IRQ(2));
 242 -       }
 243 -}
 244 -
 245 -static void qca956x_enable_timer_cb(void) {
 246 -       u32 misc;
 247 -
 248 -       misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
 249 -       misc |= MISC_INT_MIPS_SI_TIMERINT_MASK;
 250 -       ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc);
 251 -}
 252 -
 253 -static void qca956x_irq_init(void)
 254 -{
 255 -       int i;
 256 -
 257 -       for (i = ATH79_IP2_IRQ_BASE;
 258 -            i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
 259 -               irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
 260 -
 261 -       irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch);
 262 -
 263 -       for (i = ATH79_IP3_IRQ_BASE;
 264 -            i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
 265 -               irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
 266 -
 267 -       irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
 268 -
 269 -       /* QCA956x timer init workaround has to be applied right before setting
 270 -        * up the clock. Else, there will be no jiffies */
 271 -       late_time_init = &qca956x_enable_timer_cb;
 272 -}
 273 -
 274 -void __init arch_init_irq(void)
 275 -{
 276 -       unsigned irq_wb_chan2 = -1;
 277 -       unsigned irq_wb_chan3 = -1;
 278 -       bool misc_is_ar71xx;
 279 -
 280 -       if (mips_machtype == ATH79_MACH_GENERIC_OF) {
 281 -               irqchip_init();
 282 -               return;
 283 -       }
 284 -
 285 -       if (soc_is_ar71xx() || soc_is_ar724x() ||
 286 -           soc_is_ar913x() || soc_is_ar933x()) {
 287 -               irq_wb_chan2 = 3;
 288 -               irq_wb_chan3 = 2;
 289 -       } else if (soc_is_ar934x() || soc_is_qca953x()) {
 290 -               irq_wb_chan3 = 2;
 291 -       }
 292 -
 293 -       ath79_cpu_irq_init(irq_wb_chan2, irq_wb_chan3);
 294 -
 295 -       if (soc_is_ar71xx() || soc_is_ar913x())
 296 -               misc_is_ar71xx = true;
 297 -       else if (soc_is_ar724x() ||
 298 -                soc_is_ar933x() ||
 299 -                soc_is_ar934x() ||
 300 -                soc_is_qca953x() ||
 301 -                soc_is_qca955x() ||
 302 -                soc_is_qca956x() ||
 303 -                soc_is_tp9343())
 304 -               misc_is_ar71xx = false;
 305 -       else
 306 -               BUG();
 307 -       ath79_misc_irq_init(
 308 -               ath79_reset_base + AR71XX_RESET_REG_MISC_INT_STATUS,
 309 -               ATH79_CPU_IRQ(6), ATH79_MISC_IRQ_BASE, misc_is_ar71xx);
 310 -
 311 -       if (soc_is_ar934x())
 312 -               ar934x_ip2_irq_init();
 313 -       else if (soc_is_qca953x())
 314 -               qca953x_irq_init();
 315 -       else if (soc_is_qca955x())
 316 -               qca955x_irq_init();
 317 -       else if (soc_is_qca956x() || soc_is_tp9343())
 318 -               qca956x_irq_init();
 319 -}
 320 diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c
 321 index 8d7ffa2e8265..7b089c07d2fa 100644
 322 --- a/arch/mips/ath79/setup.c
 323 +++ b/arch/mips/ath79/setup.c
 324 @@ -19,6 +19,7 @@
 325  #include <linux/clk.h>
 326  #include <linux/clk-provider.h>
 327  #include <linux/of_fdt.h>
 328 +#include <linux/irqchip.h>
 329
 330  #include <asm/bootinfo.h>
 331  #include <asm/idle.h>
 332 @@ -310,6 +311,11 @@ void __init plat_time_init(void)
 333         mips_hpt_frequency = cpu_clk_rate / 2;
 334  }
 335
 336 +void __init arch_init_irq(void)
 337 +{
 338 +       irqchip_init();
 339 +}
 340 +
 341  static int __init ath79_setup(void)
 342  {
 343         if  (mips_machtype == ATH79_MACH_GENERIC_OF)
 344 --
 345 2.11.0
 346