target/linux/ath79/patches-4.14/0033-MIPS-ath79-export-switch-MDIO-reference-clock.patch

   1 From: Felix Fietkau <nbd@nbd.name>
   2 Date: Tue, 6 Mar 2018 13:27:28 +0100
   3 Subject: [PATCH] MIPS: ath79: export switch MDIO reference clock
   4
   5 On AR934x, the MDIO reference clock can be configured to a fixed 100 MHz
   6 clock. If that feature is not used, it defaults to the main reference clock,
   7 like on all other SoC.
   8
   9 Signed-off-by: Felix Fietkau <nbd@nbd.name>
  10 ---
  11
  12 --- a/arch/mips/ath79/clock.c
  13 +++ b/arch/mips/ath79/clock.c
  14 @@ -41,6 +41,7 @@ static const char * const clk_names[ATH7
  15         [ATH79_CLK_DDR] = "ddr",
  16         [ATH79_CLK_AHB] = "ahb",
  17         [ATH79_CLK_REF] = "ref",
  18 +       [ATH79_CLK_MDIO] = "mdio",
  19  };
  20
  21  static const char * __init ath79_clk_name(int type)
  22 @@ -341,6 +342,10 @@ static void __init ar934x_clocks_init(vo
  23         ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
  24         ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
  25
  26 +       clk_ctrl = __raw_readl(pll_base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
  27 +       if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL)
  28 +               ath79_set_clk(ATH79_CLK_MDIO, 100 * 1000 * 1000);
  29 +
  30         iounmap(dpll_base);
  31  }
  32
  33 @@ -687,6 +692,9 @@ static void __init ath79_clocks_init_dt(
  34         else if (of_device_is_compatible(np, "qca,qca9560-pll"))
  35                 qca956x_clocks_init(pll_base);
  36
  37 +       if (!clks[ATH79_CLK_MDIO])
  38 +               clks[ATH79_CLK_MDIO] = clks[ATH79_CLK_REF];
  39 +
  40         if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
  41                 pr_err("%pOF: could not register clk provider\n", np);
  42                 goto err_iounmap;
  43 --- a/include/dt-bindings/clock/ath79-clk.h
  44 +++ b/include/dt-bindings/clock/ath79-clk.h
  45 @@ -14,7 +14,8 @@
  46  #define ATH79_CLK_DDR          1
  47  #define ATH79_CLK_AHB          2
  48  #define ATH79_CLK_REF          3
  49 +#define ATH79_CLK_MDIO         4
  50
  51 -#define ATH79_CLK_END          4
  52 +#define ATH79_CLK_END          5
  53
  54  #endif /* __DT_BINDINGS_ATH79_CLK_H */