target/linux/ath79/patches-4.19/0018-MIPS-pci-ar71xx-convert-to-OF.patch

   1 From 1855ab6b1d27f5b38a648baf57ff6a534afec26d Mon Sep 17 00:00:00 2001
   2 From: John Crispin <john@phrozen.org>
   3 Date: Sat, 23 Jun 2018 15:07:23 +0200
   4 Subject: [PATCH 18/33] MIPS: pci-ar71xx: convert to OF
   5
   6 With the ath79 target getting converted to pure OF, we can drop all the
   7 platform data code and add the missing OF bits to the driver. We also add
   8 a irq domain for the PCI/e controllers cascade, thus making it usable from
   9 dts files.
  10
  11 Signed-off-by: John Crispin <john@phrozen.org>
  12 ---
  13  arch/mips/pci/pci-ar71xx.c | 82 +++++++++++++++++++++++-----------------------
  14  1 file changed, 41 insertions(+), 41 deletions(-)
  15
  16 --- a/arch/mips/pci/pci-ar71xx.c
  17 +++ b/arch/mips/pci/pci-ar71xx.c
  18 @@ -18,8 +18,11 @@
  19  #include <linux/pci.h>
  20  #include <linux/pci_regs.h>
  21  #include <linux/interrupt.h>
  22 +#include <linux/irqchip/chained_irq.h>
  23  #include <linux/init.h>
  24  #include <linux/platform_device.h>
  25 +#include <linux/of_irq.h>
  26 +#include <linux/of_pci.h>
  27
  28  #include <asm/mach-ath79/ar71xx_regs.h>
  29  #include <asm/mach-ath79/ath79.h>
  30 @@ -49,12 +52,13 @@
  31  #define AR71XX_PCI_IRQ_COUNT           5
  32
  33  struct ar71xx_pci_controller {
  34 +       struct device_node *np;
  35         void __iomem *cfg_base;
  36         int irq;
  37 -       int irq_base;
  38         struct pci_controller pci_ctrl;
  39         struct resource io_res;
  40         struct resource mem_res;
  41 +       struct irq_domain *domain;
  42  };
  43
  44  /* Byte lane enable bits */
  45 @@ -228,29 +232,30 @@ static struct pci_ops ar71xx_pci_ops = {
  46
  47  static void ar71xx_pci_irq_handler(struct irq_desc *desc)
  48  {
  49 -       struct ar71xx_pci_controller *apc;
  50         void __iomem *base = ath79_reset_base;
  51 +       struct irq_chip *chip = irq_desc_get_chip(desc);
  52 +       struct ar71xx_pci_controller *apc = irq_desc_get_handler_data(desc);
  53         u32 pending;
  54
  55 -       apc = irq_desc_get_handler_data(desc);
  56 -
  57 +       chained_irq_enter(chip, desc);
  58         pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
  59                   __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
  60
  61         if (pending & AR71XX_PCI_INT_DEV0)
  62 -               generic_handle_irq(apc->irq_base + 0);
  63 +               generic_handle_irq(irq_linear_revmap(apc->domain, 1));
  64
  65         else if (pending & AR71XX_PCI_INT_DEV1)
  66 -               generic_handle_irq(apc->irq_base + 1);
  67 +               generic_handle_irq(irq_linear_revmap(apc->domain, 2));
  68
  69         else if (pending & AR71XX_PCI_INT_DEV2)
  70 -               generic_handle_irq(apc->irq_base + 2);
  71 +               generic_handle_irq(irq_linear_revmap(apc->domain, 3));
  72
  73         else if (pending & AR71XX_PCI_INT_CORE)
  74 -               generic_handle_irq(apc->irq_base + 4);
  75 +               generic_handle_irq(irq_linear_revmap(apc->domain, 4));
  76
  77         else
  78                 spurious_interrupt();
  79 +       chained_irq_exit(chip, desc);
  80  }
  81
  82  static void ar71xx_pci_irq_unmask(struct irq_data *d)
  83 @@ -261,7 +266,7 @@ static void ar71xx_pci_irq_unmask(struct
  84         u32 t;
  85
  86         apc = irq_data_get_irq_chip_data(d);
  87 -       irq = d->irq - apc->irq_base;
  88 +       irq = irq_linear_revmap(apc->domain, d->irq);
  89
  90         t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
  91         __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
  92 @@ -278,7 +283,7 @@ static void ar71xx_pci_irq_mask(struct i
  93         u32 t;
  94
  95         apc = irq_data_get_irq_chip_data(d);
  96 -       irq = d->irq - apc->irq_base;
  97 +       irq = irq_linear_revmap(apc->domain, d->irq);
  98
  99         t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
 100         __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
 101 @@ -294,24 +299,31 @@ static struct irq_chip ar71xx_pci_irq_ch
 102         .irq_mask_ack   = ar71xx_pci_irq_mask,
 103  };
 104
 105 +static int ar71xx_pci_irq_map(struct irq_domain *d,
 106 +                             unsigned int irq, irq_hw_number_t hw)
 107 +{
 108 +       struct ar71xx_pci_controller *apc = d->host_data;
 109 +
 110 +       irq_set_chip_and_handler(irq, &ar71xx_pci_irq_chip, handle_level_irq);
 111 +       irq_set_chip_data(irq, apc);
 112 +
 113 +       return 0;
 114 +}
 115 +
 116 +static const struct irq_domain_ops ar71xx_pci_domain_ops = {
 117 +       .xlate = irq_domain_xlate_onecell,
 118 +       .map = ar71xx_pci_irq_map,
 119 +};
 120 +
 121  static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc)
 122  {
 123         void __iomem *base = ath79_reset_base;
 124 -       int i;
 125
 126         __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE);
 127         __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS);
 128
 129 -       BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR71XX_PCI_IRQ_COUNT);
 130 -
 131 -       apc->irq_base = ATH79_PCI_IRQ_BASE;
 132 -       for (i = apc->irq_base;
 133 -            i < apc->irq_base + AR71XX_PCI_IRQ_COUNT; i++) {
 134 -               irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip,
 135 -                                        handle_level_irq);
 136 -               irq_set_chip_data(i, apc);
 137 -       }
 138 -
 139 +       apc->domain = irq_domain_add_linear(apc->np, AR71XX_PCI_IRQ_COUNT,
 140 +                                           &ar71xx_pci_domain_ops, apc);
 141         irq_set_chained_handler_and_data(apc->irq, ar71xx_pci_irq_handler,
 142                                          apc);
 143  }
 144 @@ -328,6 +340,11 @@ static void ar71xx_pci_reset(void)
 145         mdelay(100);
 146  }
 147
 148 +static const struct of_device_id ar71xx_pci_ids[] = {
 149 +       { .compatible = "qca,ar7100-pci" },
 150 +       {},
 151 +};
 152 +
 153  static int ar71xx_pci_probe(struct platform_device *pdev)
 154  {
 155         struct ar71xx_pci_controller *apc;
 156 @@ -348,26 +365,6 @@ static int ar71xx_pci_probe(struct platf
 157         if (apc->irq < 0)
 158                 return -EINVAL;
 159
 160 -       res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base");
 161 -       if (!res)
 162 -               return -EINVAL;
 163 -
 164 -       apc->io_res.parent = res;
 165 -       apc->io_res.name = "PCI IO space";
 166 -       apc->io_res.start = res->start;
 167 -       apc->io_res.end = res->end;
 168 -       apc->io_res.flags = IORESOURCE_IO;
 169 -
 170 -       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base");
 171 -       if (!res)
 172 -               return -EINVAL;
 173 -
 174 -       apc->mem_res.parent = res;
 175 -       apc->mem_res.name = "PCI memory space";
 176 -       apc->mem_res.start = res->start;
 177 -       apc->mem_res.end = res->end;
 178 -       apc->mem_res.flags = IORESOURCE_MEM;
 179 -
 180         ar71xx_pci_reset();
 181
 182         /* setup COMMAND register */
 183 @@ -380,9 +377,11 @@ static int ar71xx_pci_probe(struct platf
 184
 185         ar71xx_pci_irq_init(apc);
 186
 187 +       apc->np = pdev->dev.of_node;
 188         apc->pci_ctrl.pci_ops = &ar71xx_pci_ops;
 189         apc->pci_ctrl.mem_resource = &apc->mem_res;
 190         apc->pci_ctrl.io_resource = &apc->io_res;
 191 +       pci_load_of_ranges(&apc->pci_ctrl, pdev->dev.of_node);
 192
 193         register_pci_controller(&apc->pci_ctrl);
 194
 195 @@ -393,6 +392,7 @@ static struct platform_driver ar71xx_pci
 196         .probe = ar71xx_pci_probe,
 197         .driver = {
 198                 .name = "ar71xx-pci",
 199 +               .of_match_table = of_match_ptr(ar71xx_pci_ids),
 200         },
 201  };
 202