target/linux/ath79/patches-4.19/0023-MIPS-ath79-pass-PLL-base-to-clock-init-functions.patch

   1 From 6350b2c36c522fecbc91a80b63f49319dafd2a72 Mon Sep 17 00:00:00 2001
   2 From: Felix Fietkau <nbd@nbd.name>
   3 Date: Tue, 6 Mar 2018 13:23:20 +0100
   4 Subject: [PATCH 23/33] MIPS: ath79: pass PLL base to clock init functions
   5
   6 Preparation for passing the mapped base via DT
   7
   8 Signed-off-by: Felix Fietkau <nbd@nbd.name>
   9 Signed-off-by: John Crispin <john@phrozen.org>
  10 ---
  11  arch/mips/ath79/clock.c | 60 ++++++++++++++++++++++++-------------------------
  12  1 file changed, 30 insertions(+), 30 deletions(-)
  13
  14 --- a/arch/mips/ath79/clock.c
  15 +++ b/arch/mips/ath79/clock.c
  16 @@ -80,7 +80,7 @@ static struct clk * __init ath79_set_ff_
  17         return clk;
  18  }
  19
  20 -static void __init ar71xx_clocks_init(void)
  21 +static void __init ar71xx_clocks_init(void __iomem *pll_base)
  22  {
  23         unsigned long ref_rate;
  24         unsigned long cpu_rate;
  25 @@ -92,7 +92,7 @@ static void __init ar71xx_clocks_init(vo
  26
  27         ref_rate = AR71XX_BASE_FREQ;
  28
  29 -       pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
  30 +       pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG);
  31
  32         div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1;
  33         freq = div * ref_rate;
  34 @@ -130,13 +130,13 @@ static void __init ar724x_clk_init(struc
  35         ath79_set_ff_clk(ATH79_CLK_AHB, "ref", mult, div * ahb_div);
  36  }
  37
  38 -static void __init ar724x_clocks_init(void)
  39 +static void __init ar724x_clocks_init(void __iomem *pll_base)
  40  {
  41         struct clk *ref_clk;
  42
  43         ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ);
  44
  45 -       ar724x_clk_init(ref_clk, ath79_pll_base);
  46 +       ar724x_clk_init(ref_clk, pll_base);
  47  }
  48
  49  static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
  50 @@ -197,7 +197,7 @@ static void __init ar9330_clk_init(struc
  51                          ref_div * out_div * ahb_div);
  52  }
  53
  54 -static void __init ar933x_clocks_init(void)
  55 +static void __init ar933x_clocks_init(void __iomem *pll_base)
  56  {
  57         struct clk *ref_clk;
  58         unsigned long ref_rate;
  59 @@ -234,7 +234,7 @@ static u32 __init ar934x_get_pll_freq(u3
  60         return ret;
  61  }
  62
  63 -static void __init ar934x_clocks_init(void)
  64 +static void __init ar934x_clocks_init(void __iomem *pll_base)
  65  {
  66         unsigned long ref_rate;
  67         unsigned long cpu_rate;
  68 @@ -265,7 +265,7 @@ static void __init ar934x_clocks_init(vo
  69                           AR934X_SRIF_DPLL1_REFDIV_MASK;
  70                 frac = 1 << 18;
  71         } else {
  72 -               pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
  73 +               pll = __raw_readl(pll_base + AR934X_PLL_CPU_CONFIG_REG);
  74                 out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
  75                         AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
  76                 ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
  77 @@ -292,7 +292,7 @@ static void __init ar934x_clocks_init(vo
  78                           AR934X_SRIF_DPLL1_REFDIV_MASK;
  79                 frac = 1 << 18;
  80         } else {
  81 -               pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
  82 +               pll = __raw_readl(pll_base + AR934X_PLL_DDR_CONFIG_REG);
  83                 out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
  84                           AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
  85                 ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
  86 @@ -307,7 +307,7 @@ static void __init ar934x_clocks_init(vo
  87         ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
  88                                       nfrac, frac, out_div);
  89
  90 -       clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
  91 +       clk_ctrl = __raw_readl(pll_base + AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
  92
  93         postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
  94                   AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
  95 @@ -347,7 +347,7 @@ static void __init ar934x_clocks_init(vo
  96         iounmap(dpll_base);
  97  }
  98
  99 -static void __init qca953x_clocks_init(void)
 100 +static void __init qca953x_clocks_init(void __iomem *pll_base)
 101  {
 102         unsigned long ref_rate;
 103         unsigned long cpu_rate;
 104 @@ -363,7 +363,7 @@ static void __init qca953x_clocks_init(v
 105         else
 106                 ref_rate = 25 * 1000 * 1000;
 107
 108 -       pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
 109 +       pll = __raw_readl(pll_base + QCA953X_PLL_CPU_CONFIG_REG);
 110         out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
 111                   QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
 112         ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
 113 @@ -377,7 +377,7 @@ static void __init qca953x_clocks_init(v
 114         cpu_pll += frac * (ref_rate >> 6) / ref_div;
 115         cpu_pll /= (1 << out_div);
 116
 117 -       pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG);
 118 +       pll = __raw_readl(pll_base + QCA953X_PLL_DDR_CONFIG_REG);
 119         out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
 120                   QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
 121         ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
 122 @@ -391,7 +391,7 @@ static void __init qca953x_clocks_init(v
 123         ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
 124         ddr_pll /= (1 << out_div);
 125
 126 -       clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG);
 127 +       clk_ctrl = __raw_readl(pll_base + QCA953X_PLL_CLK_CTRL_REG);
 128
 129         postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
 130                   QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
 131 @@ -429,7 +429,7 @@ static void __init qca953x_clocks_init(v
 132         ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
 133  }
 134
 135 -static void __init qca955x_clocks_init(void)
 136 +static void __init qca955x_clocks_init(void __iomem *pll_base)
 137  {
 138         unsigned long ref_rate;
 139         unsigned long cpu_rate;
 140 @@ -445,7 +445,7 @@ static void __init qca955x_clocks_init(v
 141         else
 142                 ref_rate = 25 * 1000 * 1000;
 143
 144 -       pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
 145 +       pll = __raw_readl(pll_base + QCA955X_PLL_CPU_CONFIG_REG);
 146         out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
 147                   QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
 148         ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
 149 @@ -459,7 +459,7 @@ static void __init qca955x_clocks_init(v
 150         cpu_pll += frac * ref_rate / (ref_div * (1 << 6));
 151         cpu_pll /= (1 << out_div);
 152
 153 -       pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
 154 +       pll = __raw_readl(pll_base + QCA955X_PLL_DDR_CONFIG_REG);
 155         out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
 156                   QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
 157         ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
 158 @@ -473,7 +473,7 @@ static void __init qca955x_clocks_init(v
 159         ddr_pll += frac * ref_rate / (ref_div * (1 << 10));
 160         ddr_pll /= (1 << out_div);
 161
 162 -       clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);
 163 +       clk_ctrl = __raw_readl(pll_base + QCA955X_PLL_CLK_CTRL_REG);
 164
 165         postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
 166                   QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
 167 @@ -511,7 +511,7 @@ static void __init qca955x_clocks_init(v
 168         ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
 169  }
 170
 171 -static void __init qca956x_clocks_init(void)
 172 +static void __init qca956x_clocks_init(void __iomem *pll_base)
 173  {
 174         unsigned long ref_rate;
 175         unsigned long cpu_rate;
 176 @@ -537,13 +537,13 @@ static void __init qca956x_clocks_init(v
 177         else
 178                 ref_rate = 25 * 1000 * 1000;
 179
 180 -       pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG);
 181 +       pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG_REG);
 182         out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
 183                   QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
 184         ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
 185                   QCA956X_PLL_CPU_CONFIG_REFDIV_MASK;
 186
 187 -       pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG);
 188 +       pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG1_REG);
 189         nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
 190                QCA956X_PLL_CPU_CONFIG1_NINT_MASK;
 191         hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
 192 @@ -556,12 +556,12 @@ static void __init qca956x_clocks_init(v
 193         cpu_pll += (hfrac >> 13) * ref_rate / ref_div;
 194         cpu_pll /= (1 << out_div);
 195
 196 -       pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG);
 197 +       pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG_REG);
 198         out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
 199                   QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK;
 200         ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
 201                   QCA956X_PLL_DDR_CONFIG_REFDIV_MASK;
 202 -       pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG);
 203 +       pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG1_REG);
 204         nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
 205                QCA956X_PLL_DDR_CONFIG1_NINT_MASK;
 206         hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
 207 @@ -574,7 +574,7 @@ static void __init qca956x_clocks_init(v
 208         ddr_pll += (hfrac >> 13) * ref_rate / ref_div;
 209         ddr_pll /= (1 << out_div);
 210
 211 -       clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG);
 212 +       clk_ctrl = __raw_readl(pll_base + QCA956X_PLL_CLK_CTRL_REG);
 213
 214         postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
 215                   QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
 216 @@ -618,19 +618,19 @@ void __init ath79_clocks_init(void)
 217         const char *uart;
 218
 219         if (soc_is_ar71xx())
 220 -               ar71xx_clocks_init();
 221 +               ar71xx_clocks_init(ath79_pll_base);
 222         else if (soc_is_ar724x() || soc_is_ar913x())
 223 -               ar724x_clocks_init();
 224 +               ar724x_clocks_init(ath79_pll_base);
 225         else if (soc_is_ar933x())
 226 -               ar933x_clocks_init();
 227 +               ar933x_clocks_init(ath79_pll_base);
 228         else if (soc_is_ar934x())
 229 -               ar934x_clocks_init();
 230 +               ar934x_clocks_init(ath79_pll_base);
 231         else if (soc_is_qca953x())
 232 -               qca953x_clocks_init();
 233 +               qca953x_clocks_init(ath79_pll_base);
 234         else if (soc_is_qca955x())
 235 -               qca955x_clocks_init();
 236 +               qca955x_clocks_init(ath79_pll_base);
 237         else if (soc_is_qca956x() || soc_is_tp9343())
 238 -               qca956x_clocks_init();
 239 +               qca956x_clocks_init(ath79_pll_base);
 240         else
 241                 BUG();
 242