target/linux/ath79/patches-4.19/0024-MIPS-ath79-make-specifying-the-reference-clock-in-DT.patch

   1 From 5fadb2544ed0bb72ddddd846aa303bb9ed2d211c Mon Sep 17 00:00:00 2001
   2 From: Felix Fietkau <nbd@nbd.name>
   3 Date: Tue, 6 Mar 2018 13:24:07 +0100
   4 Subject: [PATCH 24/33] MIPS: ath79: make specifying the reference clock in DT
   5  optional
   6
   7 It can be autodetected for many SoCs using the strapping options.
   8 If the clock is specified in DT, the autodetected value is ignored
   9
  10 Signed-off-by: Felix Fietkau <nbd@nbd.name>
  11 Signed-off-by: John Crispin <john@phrozen.org>
  12 ---
  13  arch/mips/ath79/clock.c | 84 +++++++++++++++++++++++--------------------------
  14  1 file changed, 40 insertions(+), 44 deletions(-)
  15
  16 --- a/arch/mips/ath79/clock.c
  17 +++ b/arch/mips/ath79/clock.c
  18 @@ -80,6 +80,18 @@ static struct clk * __init ath79_set_ff_
  19         return clk;
  20  }
  21
  22 +static unsigned long __init ath79_setup_ref_clk(unsigned long rate)
  23 +{
  24 +       struct clk *clk = clks[ATH79_CLK_REF];
  25 +
  26 +       if (clk)
  27 +               rate = clk_get_rate(clk);
  28 +       else
  29 +               clk = ath79_set_clk(ATH79_CLK_REF, rate);
  30 +
  31 +       return rate;
  32 +}
  33 +
  34  static void __init ar71xx_clocks_init(void __iomem *pll_base)
  35  {
  36         unsigned long ref_rate;
  37 @@ -90,7 +102,7 @@ static void __init ar71xx_clocks_init(vo
  38         u32 freq;
  39         u32 div;
  40
  41 -       ref_rate = AR71XX_BASE_FREQ;
  42 +       ref_rate = ath79_setup_ref_clk(AR71XX_BASE_FREQ);
  43
  44         pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG);
  45
  46 @@ -106,16 +118,17 @@ static void __init ar71xx_clocks_init(vo
  47         div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
  48         ahb_rate = cpu_rate / div;
  49
  50 -       ath79_set_clk(ATH79_CLK_REF, ref_rate);
  51         ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
  52         ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
  53         ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
  54  }
  55
  56 -static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
  57 +static void __init ar724x_clocks_init(void __iomem *pll_base)
  58  {
  59 -       u32 pll;
  60         u32 mult, div, ddr_div, ahb_div;
  61 +       u32 pll;
  62 +
  63 +       ath79_setup_ref_clk(AR71XX_BASE_FREQ);
  64
  65         pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG);
  66
  67 @@ -130,17 +143,9 @@ static void __init ar724x_clk_init(struc
  68         ath79_set_ff_clk(ATH79_CLK_AHB, "ref", mult, div * ahb_div);
  69  }
  70
  71 -static void __init ar724x_clocks_init(void __iomem *pll_base)
  72 -{
  73 -       struct clk *ref_clk;
  74 -
  75 -       ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ);
  76 -
  77 -       ar724x_clk_init(ref_clk, pll_base);
  78 -}
  79 -
  80 -static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
  81 +static void __init ar933x_clocks_init(void __iomem *pll_base)
  82  {
  83 +       unsigned long ref_rate;
  84         u32 clock_ctrl;
  85         u32 ref_div;
  86         u32 ninit_mul;
  87 @@ -149,6 +154,15 @@ static void __init ar9330_clk_init(struc
  88         u32 cpu_div;
  89         u32 ddr_div;
  90         u32 ahb_div;
  91 +       u32 t;
  92 +
  93 +       t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
  94 +       if (t & AR933X_BOOTSTRAP_REF_CLK_40)
  95 +               ref_rate = (40 * 1000 * 1000);
  96 +       else
  97 +               ref_rate = (25 * 1000 * 1000);
  98 +
  99 +       ath79_setup_ref_clk(ref_rate);
 100
 101         clock_ctrl = __raw_readl(pll_base + AR933X_PLL_CLOCK_CTRL_REG);
 102         if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
 103 @@ -197,23 +211,6 @@ static void __init ar9330_clk_init(struc
 104                          ref_div * out_div * ahb_div);
 105  }
 106
 107 -static void __init ar933x_clocks_init(void __iomem *pll_base)
 108 -{
 109 -       struct clk *ref_clk;
 110 -       unsigned long ref_rate;
 111 -       u32 t;
 112 -
 113 -       t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
 114 -       if (t & AR933X_BOOTSTRAP_REF_CLK_40)
 115 -               ref_rate = (40 * 1000 * 1000);
 116 -       else
 117 -               ref_rate = (25 * 1000 * 1000);
 118 -
 119 -       ref_clk = ath79_set_clk(ATH79_CLK_REF, ref_rate);
 120 -
 121 -       ar9330_clk_init(ref_clk, ath79_pll_base);
 122 -}
 123 -
 124  static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
 125                                       u32 frac, u32 out_div)
 126  {
 127 @@ -253,6 +250,8 @@ static void __init ar934x_clocks_init(vo
 128         else
 129                 ref_rate = 25 * 1000 * 1000;
 130
 131 +       ref_rate = ath79_setup_ref_clk(ref_rate);
 132 +
 133         pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);
 134         if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
 135                 out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
 136 @@ -339,7 +338,6 @@ static void __init ar934x_clocks_init(vo
 137         else
 138                 ahb_rate = cpu_pll / (postdiv + 1);
 139
 140 -       ath79_set_clk(ATH79_CLK_REF, ref_rate);
 141         ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
 142         ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
 143         ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
 144 @@ -363,6 +361,8 @@ static void __init qca953x_clocks_init(v
 145         else
 146                 ref_rate = 25 * 1000 * 1000;
 147
 148 +       ref_rate = ath79_setup_ref_clk(ref_rate);
 149 +
 150         pll = __raw_readl(pll_base + QCA953X_PLL_CPU_CONFIG_REG);
 151         out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
 152                   QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
 153 @@ -423,7 +423,6 @@ static void __init qca953x_clocks_init(v
 154         else
 155                 ahb_rate = cpu_pll / (postdiv + 1);
 156
 157 -       ath79_set_clk(ATH79_CLK_REF, ref_rate);
 158         ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
 159         ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
 160         ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
 161 @@ -445,6 +444,8 @@ static void __init qca955x_clocks_init(v
 162         else
 163                 ref_rate = 25 * 1000 * 1000;
 164
 165 +       ref_rate = ath79_setup_ref_clk(ref_rate);
 166 +
 167         pll = __raw_readl(pll_base + QCA955X_PLL_CPU_CONFIG_REG);
 168         out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
 169                   QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
 170 @@ -505,7 +506,6 @@ static void __init qca955x_clocks_init(v
 171         else
 172                 ahb_rate = cpu_pll / (postdiv + 1);
 173
 174 -       ath79_set_clk(ATH79_CLK_REF, ref_rate);
 175         ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
 176         ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
 177         ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
 178 @@ -537,6 +537,8 @@ static void __init qca956x_clocks_init(v
 179         else
 180                 ref_rate = 25 * 1000 * 1000;
 181
 182 +       ref_rate = ath79_setup_ref_clk(ref_rate);
 183 +
 184         pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG_REG);
 185         out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
 186                   QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
 187 @@ -606,7 +608,6 @@ static void __init qca956x_clocks_init(v
 188         else
 189                 ahb_rate = cpu_pll / (postdiv + 1);
 190
 191 -       ath79_set_clk(ATH79_CLK_REF, ref_rate);
 192         ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
 193         ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
 194         ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
 195 @@ -682,10 +683,8 @@ static void __init ath79_clocks_init_dt_
 196         void __iomem *pll_base;
 197
 198         ref_clk = of_clk_get(np, 0);
 199 -       if (IS_ERR(ref_clk)) {
 200 -               pr_err("%pOF: of_clk_get failed\n", np);
 201 -               goto err;
 202 -       }
 203 +       if (!IS_ERR(ref_clk))
 204 +               clks[ATH79_CLK_REF] = ref_clk;
 205
 206         pll_base = of_iomap(np, 0);
 207         if (!pll_base) {
 208 @@ -694,9 +693,9 @@ static void __init ath79_clocks_init_dt_
 209         }
 210
 211         if (of_device_is_compatible(np, "qca,ar9130-pll"))
 212 -               ar724x_clk_init(ref_clk, pll_base);
 213 +               ar724x_clocks_init(pll_base);
 214         else if (of_device_is_compatible(np, "qca,ar9330-pll"))
 215 -               ar9330_clk_init(ref_clk, pll_base);
 216 +               ar933x_clocks_init(pll_base);
 217         else {
 218                 pr_err("%pOF: could not find any appropriate clk_init()\n", np);
 219                 goto err_iounmap;
 220 @@ -714,9 +713,6 @@ err_iounmap:
 221
 222  err_clk:
 223         clk_put(ref_clk);
 224 -
 225 -err:
 226 -       return;
 227  }
 228  CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt_ng);
 229  CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt_ng);