target/linux/ath79/patches-4.19/0029-MIPS-ath79-drop-legacy-pci-code.patch

   1 From d0f1420702ed47a82572aaf39e7407055518d14e Mon Sep 17 00:00:00 2001
   2 From: John Crispin <john@phrozen.org>
   3 Date: Sat, 23 Jun 2018 15:05:19 +0200
   4 Subject: [PATCH 29/33] MIPS: ath79: drop legacy pci code
   5
   6 With the target now being fully OF based, we can drop the legacy pci
   7 platform code. The only bits that we need to keep is the fixup code
   8 which we move to its own code file.
   9
  10 Signed-off-by: John Crispin <john@phrozen.org>
  11 ---
  12  arch/mips/ath79/Makefile    |   1 -
  13  arch/mips/ath79/pci.c       | 273 --------------------------------------------
  14  arch/mips/ath79/pci.h       |  35 ------
  15  arch/mips/pci/Makefile      |   1 +
  16  arch/mips/pci/fixup-ath79.c |  21 ++++
  17  5 files changed, 22 insertions(+), 309 deletions(-)
  18  delete mode 100644 arch/mips/ath79/pci.c
  19  delete mode 100644 arch/mips/ath79/pci.h
  20  create mode 100644 arch/mips/pci/fixup-ath79.c
  21
  22 --- a/arch/mips/ath79/Makefile
  23 +++ b/arch/mips/ath79/Makefile
  24 @@ -11,7 +11,6 @@
  25  obj-y  := prom.o setup.o common.o clock.o
  26
  27  obj-$(CONFIG_EARLY_PRINTK)             += early_printk.o
  28 -obj-$(CONFIG_PCI)                      += pci.o
  29
  30  #
  31  # Devices
  32 --- a/arch/mips/ath79/pci.c
  33 +++ /dev/null
  34 @@ -1,273 +0,0 @@
  35 -/*
  36 - *  Atheros AR71XX/AR724X specific PCI setup code
  37 - *
  38 - *  Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
  39 - *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
  40 - *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  41 - *
  42 - *  Parts of this file are based on Atheros' 2.6.15 BSP
  43 - *
  44 - *  This program is free software; you can redistribute it and/or modify it
  45 - *  under the terms of the GNU General Public License version 2 as published
  46 - *  by the Free Software Foundation.
  47 - */
  48 -
  49 -#include <linux/init.h>
  50 -#include <linux/pci.h>
  51 -#include <linux/resource.h>
  52 -#include <linux/platform_device.h>
  53 -#include <asm/mach-ath79/ar71xx_regs.h>
  54 -#include <asm/mach-ath79/ath79.h>
  55 -#include <asm/mach-ath79/irq.h>
  56 -#include "pci.h"
  57 -
  58 -static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev);
  59 -static const struct ath79_pci_irq *ath79_pci_irq_map;
  60 -static unsigned ath79_pci_nr_irqs;
  61 -
  62 -static const struct ath79_pci_irq ar71xx_pci_irq_map[] = {
  63 -       {
  64 -               .slot   = 17,
  65 -               .pin    = 1,
  66 -               .irq    = ATH79_PCI_IRQ(0),
  67 -       }, {
  68 -               .slot   = 18,
  69 -               .pin    = 1,
  70 -               .irq    = ATH79_PCI_IRQ(1),
  71 -       }, {
  72 -               .slot   = 19,
  73 -               .pin    = 1,
  74 -               .irq    = ATH79_PCI_IRQ(2),
  75 -       }
  76 -};
  77 -
  78 -static const struct ath79_pci_irq ar724x_pci_irq_map[] = {
  79 -       {
  80 -               .slot   = 0,
  81 -               .pin    = 1,
  82 -               .irq    = ATH79_PCI_IRQ(0),
  83 -       }
  84 -};
  85 -
  86 -static const struct ath79_pci_irq qca955x_pci_irq_map[] = {
  87 -       {
  88 -               .bus    = 0,
  89 -               .slot   = 0,
  90 -               .pin    = 1,
  91 -               .irq    = ATH79_PCI_IRQ(0),
  92 -       },
  93 -       {
  94 -               .bus    = 1,
  95 -               .slot   = 0,
  96 -               .pin    = 1,
  97 -               .irq    = ATH79_PCI_IRQ(1),
  98 -       },
  99 -};
 100 -
 101 -int pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
 102 -{
 103 -       int irq = -1;
 104 -       int i;
 105 -
 106 -       if (ath79_pci_nr_irqs == 0 ||
 107 -           ath79_pci_irq_map == NULL) {
 108 -               if (soc_is_ar71xx()) {
 109 -                       ath79_pci_irq_map = ar71xx_pci_irq_map;
 110 -                       ath79_pci_nr_irqs = ARRAY_SIZE(ar71xx_pci_irq_map);
 111 -               } else if (soc_is_ar724x() ||
 112 -                          soc_is_ar9342() ||
 113 -                          soc_is_ar9344()) {
 114 -                       ath79_pci_irq_map = ar724x_pci_irq_map;
 115 -                       ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map);
 116 -               } else if (soc_is_qca955x()) {
 117 -                       ath79_pci_irq_map = qca955x_pci_irq_map;
 118 -                       ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map);
 119 -               } else {
 120 -                       pr_crit("pci %s: invalid irq map\n",
 121 -                               pci_name((struct pci_dev *) dev));
 122 -                       return irq;
 123 -               }
 124 -       }
 125 -
 126 -       for (i = 0; i < ath79_pci_nr_irqs; i++) {
 127 -               const struct ath79_pci_irq *entry;
 128 -
 129 -               entry = &ath79_pci_irq_map[i];
 130 -               if (entry->bus == dev->bus->number &&
 131 -                   entry->slot == slot &&
 132 -                   entry->pin == pin) {
 133 -                       irq = entry->irq;
 134 -                       break;
 135 -               }
 136 -       }
 137 -
 138 -       if (irq < 0)
 139 -               pr_crit("pci %s: no irq found for pin %u\n",
 140 -                       pci_name((struct pci_dev *) dev), pin);
 141 -       else
 142 -               pr_info("pci %s: using irq %d for pin %u\n",
 143 -                       pci_name((struct pci_dev *) dev), irq, pin);
 144 -
 145 -       return irq;
 146 -}
 147 -
 148 -int pcibios_plat_dev_init(struct pci_dev *dev)
 149 -{
 150 -       if (ath79_pci_plat_dev_init)
 151 -               return ath79_pci_plat_dev_init(dev);
 152 -
 153 -       return 0;
 154 -}
 155 -
 156 -void __init ath79_pci_set_irq_map(unsigned nr_irqs,
 157 -                                 const struct ath79_pci_irq *map)
 158 -{
 159 -       ath79_pci_nr_irqs = nr_irqs;
 160 -       ath79_pci_irq_map = map;
 161 -}
 162 -
 163 -void __init ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev))
 164 -{
 165 -       ath79_pci_plat_dev_init = func;
 166 -}
 167 -
 168 -static struct platform_device *
 169 -ath79_register_pci_ar71xx(void)
 170 -{
 171 -       struct platform_device *pdev;
 172 -       struct resource res[4];
 173 -
 174 -       memset(res, 0, sizeof(res));
 175 -
 176 -       res[0].name = "cfg_base";
 177 -       res[0].flags = IORESOURCE_MEM;
 178 -       res[0].start = AR71XX_PCI_CFG_BASE;
 179 -       res[0].end = AR71XX_PCI_CFG_BASE + AR71XX_PCI_CFG_SIZE - 1;
 180 -
 181 -       res[1].flags = IORESOURCE_IRQ;
 182 -       res[1].start = ATH79_CPU_IRQ(2);
 183 -       res[1].end = ATH79_CPU_IRQ(2);
 184 -
 185 -       res[2].name = "io_base";
 186 -       res[2].flags = IORESOURCE_IO;
 187 -       res[2].start = 0;
 188 -       res[2].end = 0;
 189 -
 190 -       res[3].name = "mem_base";
 191 -       res[3].flags = IORESOURCE_MEM;
 192 -       res[3].start = AR71XX_PCI_MEM_BASE;
 193 -       res[3].end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1;
 194 -
 195 -       pdev = platform_device_register_simple("ar71xx-pci", -1,
 196 -                                              res, ARRAY_SIZE(res));
 197 -       return pdev;
 198 -}
 199 -
 200 -static struct platform_device *
 201 -ath79_register_pci_ar724x(int id,
 202 -                         unsigned long cfg_base,
 203 -                         unsigned long ctrl_base,
 204 -                         unsigned long crp_base,
 205 -                         unsigned long mem_base,
 206 -                         unsigned long mem_size,
 207 -                         unsigned long io_base,
 208 -                         int irq)
 209 -{
 210 -       struct platform_device *pdev;
 211 -       struct resource res[6];
 212 -
 213 -       memset(res, 0, sizeof(res));
 214 -
 215 -       res[0].name = "cfg_base";
 216 -       res[0].flags = IORESOURCE_MEM;
 217 -       res[0].start = cfg_base;
 218 -       res[0].end = cfg_base + AR724X_PCI_CFG_SIZE - 1;
 219 -
 220 -       res[1].name = "ctrl_base";
 221 -       res[1].flags = IORESOURCE_MEM;
 222 -       res[1].start = ctrl_base;
 223 -       res[1].end = ctrl_base + AR724X_PCI_CTRL_SIZE - 1;
 224 -
 225 -       res[2].flags = IORESOURCE_IRQ;
 226 -       res[2].start = irq;
 227 -       res[2].end = irq;
 228 -
 229 -       res[3].name = "mem_base";
 230 -       res[3].flags = IORESOURCE_MEM;
 231 -       res[3].start = mem_base;
 232 -       res[3].end = mem_base + mem_size - 1;
 233 -
 234 -       res[4].name = "io_base";
 235 -       res[4].flags = IORESOURCE_IO;
 236 -       res[4].start = io_base;
 237 -       res[4].end = io_base;
 238 -
 239 -       res[5].name = "crp_base";
 240 -       res[5].flags = IORESOURCE_MEM;
 241 -       res[5].start = crp_base;
 242 -       res[5].end = crp_base + AR724X_PCI_CRP_SIZE - 1;
 243 -
 244 -       pdev = platform_device_register_simple("ar724x-pci", id,
 245 -                                              res, ARRAY_SIZE(res));
 246 -       return pdev;
 247 -}
 248 -
 249 -int __init ath79_register_pci(void)
 250 -{
 251 -       struct platform_device *pdev = NULL;
 252 -
 253 -       if (soc_is_ar71xx()) {
 254 -               pdev = ath79_register_pci_ar71xx();
 255 -       } else if (soc_is_ar724x()) {
 256 -               pdev = ath79_register_pci_ar724x(-1,
 257 -                                                AR724X_PCI_CFG_BASE,
 258 -                                                AR724X_PCI_CTRL_BASE,
 259 -                                                AR724X_PCI_CRP_BASE,
 260 -                                                AR724X_PCI_MEM_BASE,
 261 -                                                AR724X_PCI_MEM_SIZE,
 262 -                                                0,
 263 -                                                ATH79_CPU_IRQ(2));
 264 -       } else if (soc_is_ar9342() ||
 265 -                  soc_is_ar9344()) {
 266 -               u32 bootstrap;
 267 -
 268 -               bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
 269 -               if ((bootstrap & AR934X_BOOTSTRAP_PCIE_RC) == 0)
 270 -                       return -ENODEV;
 271 -
 272 -               pdev = ath79_register_pci_ar724x(-1,
 273 -                                                AR724X_PCI_CFG_BASE,
 274 -                                                AR724X_PCI_CTRL_BASE,
 275 -                                                AR724X_PCI_CRP_BASE,
 276 -                                                AR724X_PCI_MEM_BASE,
 277 -                                                AR724X_PCI_MEM_SIZE,
 278 -                                                0,
 279 -                                                ATH79_IP2_IRQ(0));
 280 -       } else if (soc_is_qca9558()) {
 281 -               pdev = ath79_register_pci_ar724x(0,
 282 -                                                QCA955X_PCI_CFG_BASE0,
 283 -                                                QCA955X_PCI_CTRL_BASE0,
 284 -                                                QCA955X_PCI_CRP_BASE0,
 285 -                                                QCA955X_PCI_MEM_BASE0,
 286 -                                                QCA955X_PCI_MEM_SIZE,
 287 -                                                0,
 288 -                                                ATH79_IP2_IRQ(0));
 289 -
 290 -               pdev = ath79_register_pci_ar724x(1,
 291 -                                                QCA955X_PCI_CFG_BASE1,
 292 -                                                QCA955X_PCI_CTRL_BASE1,
 293 -                                                QCA955X_PCI_CRP_BASE1,
 294 -                                                QCA955X_PCI_MEM_BASE1,
 295 -                                                QCA955X_PCI_MEM_SIZE,
 296 -                                                1,
 297 -                                                ATH79_IP3_IRQ(2));
 298 -       } else {
 299 -               /* No PCI support */
 300 -               return -ENODEV;
 301 -       }
 302 -
 303 -       if (!pdev)
 304 -               pr_err("unable to register PCI controller device\n");
 305 -
 306 -       return pdev ? 0 : -ENODEV;
 307 -}
 308 --- a/arch/mips/ath79/pci.h
 309 +++ /dev/null
 310 @@ -1,35 +0,0 @@
 311 -/*
 312 - *  Atheros AR71XX/AR724X PCI support
 313 - *
 314 - *  Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
 315 - *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
 316 - *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
 317 - *
 318 - *  This program is free software; you can redistribute it and/or modify it
 319 - *  under the terms of the GNU General Public License version 2 as published
 320 - *  by the Free Software Foundation.
 321 - */
 322 -
 323 -#ifndef _ATH79_PCI_H
 324 -#define _ATH79_PCI_H
 325 -
 326 -struct ath79_pci_irq {
 327 -       int     bus;
 328 -       u8      slot;
 329 -       u8      pin;
 330 -       int     irq;
 331 -};
 332 -
 333 -#ifdef CONFIG_PCI
 334 -void ath79_pci_set_irq_map(unsigned nr_irqs, const struct ath79_pci_irq *map);
 335 -void ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev));
 336 -int ath79_register_pci(void);
 337 -#else
 338 -static inline void
 339 -ath79_pci_set_irq_map(unsigned nr_irqs, const struct ath79_pci_irq *map) {}
 340 -static inline void
 341 -ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *)) {}
 342 -static inline int ath79_register_pci(void) { return 0; }
 343 -#endif
 344 -
 345 -#endif /* _ATH79_PCI_H */
 346 --- a/arch/mips/pci/Makefile
 347 +++ b/arch/mips/pci/Makefile
 348 @@ -29,6 +29,7 @@ obj-$(CONFIG_MIPS_PCI_VIRTIO) += pci-vir
 349  #
 350  # These are still pretty much in the old state, watch, go blind.
 351  #
 352 +obj-$(CONFIG_ATH79)            += fixup-ath79.o
 353  obj-$(CONFIG_LASAT)            += pci-lasat.o
 354  obj-$(CONFIG_MIPS_COBALT)      += fixup-cobalt.o
 355  obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o
 356 --- /dev/null
 357 +++ b/arch/mips/pci/fixup-ath79.c
 358 @@ -0,0 +1,21 @@
 359 +/*
 360 + *  Copyright (C) 2018 John Crispin <john@phrozen.org>
 361 + *
 362 + *  This program is free software; you can redistribute it and/or modify it
 363 + *  under the terms of the GNU General Public License version 2 as published
 364 + *  by the Free Software Foundation.
 365 + */
 366 +
 367 +#include <linux/pci.h>
 368 +//#include <linux/of_irq.h>
 369 +#include <linux/of_pci.h>
 370 +
 371 +int pcibios_plat_dev_init(struct pci_dev *dev)
 372 +{
 373 +       return PCIBIOS_SUCCESSFUL;
 374 +}
 375 +
 376 +int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 377 +{
 378 +       return of_irq_parse_and_map_pci(dev, slot, pin);
 379 +}