target/linux/ath79/patches-4.19/0031-MIPS-ath79-drop-OF-clock-code.patch

   1 From 00e4313da4609074fff134e61dd9ffe3fd37474d Mon Sep 17 00:00:00 2001
   2 From: John Crispin <john@phrozen.org>
   3 Date: Sun, 24 Jun 2018 09:39:41 +0200
   4 Subject: [PATCH 31/33] MIPS: ath79: drop !OF clock code
   5
   6 With the target now being fully OF based, we can drop the legacy clock
   7 registration code. All clocks are now probed via devicetree.
   8
   9 Signed-off-by: John Crispin <john@phrozen.org>
  10 ---
  11  arch/mips/ath79/clock.c  | 56 ------------------------------------------------
  12  arch/mips/ath79/common.h |  3 ---
  13  2 files changed, 59 deletions(-)
  14
  15 --- a/arch/mips/ath79/clock.c
  16 +++ b/arch/mips/ath79/clock.c
  17 @@ -617,60 +617,6 @@ static void __init qca956x_clocks_init(v
  18         ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
  19  }
  20
  21 -void __init ath79_clocks_init(void)
  22 -{
  23 -       const char *wdt;
  24 -       const char *uart;
  25 -
  26 -       if (soc_is_ar71xx())
  27 -               ar71xx_clocks_init(ath79_pll_base);
  28 -       else if (soc_is_ar724x() || soc_is_ar913x())
  29 -               ar724x_clocks_init(ath79_pll_base);
  30 -       else if (soc_is_ar933x())
  31 -               ar933x_clocks_init(ath79_pll_base);
  32 -       else if (soc_is_ar934x())
  33 -               ar934x_clocks_init(ath79_pll_base);
  34 -       else if (soc_is_qca953x())
  35 -               qca953x_clocks_init(ath79_pll_base);
  36 -       else if (soc_is_qca955x())
  37 -               qca955x_clocks_init(ath79_pll_base);
  38 -       else if (soc_is_qca956x() || soc_is_tp9343())
  39 -               qca956x_clocks_init(ath79_pll_base);
  40 -       else
  41 -               BUG();
  42 -
  43 -       if (soc_is_ar71xx() || soc_is_ar724x() || soc_is_ar913x()) {
  44 -               wdt = "ahb";
  45 -               uart = "ahb";
  46 -       } else if (soc_is_ar933x()) {
  47 -               wdt = "ahb";
  48 -               uart = "ref";
  49 -       } else {
  50 -               wdt = "ref";
  51 -               uart = "ref";
  52 -       }
  53 -
  54 -       clk_add_alias("wdt", NULL, wdt, NULL);
  55 -       clk_add_alias("uart", NULL, uart, NULL);
  56 -}
  57 -
  58 -unsigned long __init
  59 -ath79_get_sys_clk_rate(const char *id)
  60 -{
  61 -       struct clk *clk;
  62 -       unsigned long rate;
  63 -
  64 -       clk = clk_get(NULL, id);
  65 -       if (IS_ERR(clk))
  66 -               panic("unable to get %s clock, err=%d", id, (int) PTR_ERR(clk));
  67 -
  68 -       rate = clk_get_rate(clk);
  69 -       clk_put(clk);
  70 -
  71 -       return rate;
  72 -}
  73 -
  74 -#ifdef CONFIG_OF
  75  static void __init ath79_clocks_init_dt(struct device_node *np)
  76  {
  77         struct clk *ref_clk;
  78 @@ -727,5 +673,3 @@ CLK_OF_DECLARE(ar9340_clk, "qca,ar9340-p
  79  CLK_OF_DECLARE(ar9530_clk, "qca,qca9530-pll", ath79_clocks_init_dt);
  80  CLK_OF_DECLARE(ar9550_clk, "qca,qca9550-pll", ath79_clocks_init_dt);
  81  CLK_OF_DECLARE(ar9560_clk, "qca,qca9560-pll", ath79_clocks_init_dt);
  82 -
  83 -#endif
  84 --- a/arch/mips/ath79/common.h
  85 +++ b/arch/mips/ath79/common.h
  86 @@ -19,9 +19,6 @@
  87  #define ATH79_MEM_SIZE_MIN     (2 * 1024 * 1024)
  88  #define ATH79_MEM_SIZE_MAX     (256 * 1024 * 1024)
  89
  90 -void ath79_clocks_init(void);
  91 -unsigned long ath79_get_sys_clk_rate(const char *id);
  92 -
  93  void ath79_ddr_ctrl_init(void);
  94
  95  #endif /* __ATH79_COMMON_H */