target/linux/ath79/patches-4.19/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch

   1 --- /dev/null
   2 +++ b/arch/mips/include/asm/mach-ath79/mangle-port.h
   3 @@ -0,0 +1,37 @@
   4 +/*
   5 + *  Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
   6 + *
   7 + *  This file was derived from: inlude/asm-mips/mach-generic/mangle-port.h
   8 + *      Copyright (C) 2003, 2004 Ralf Baechle
   9 + *
  10 + *  This program is free software; you can redistribute it and/or modify it
  11 + *  under the terms of the GNU General Public License version 2 as published
  12 + *  by the Free Software Foundation.
  13 + */
  14 +
  15 +#ifndef __ASM_MACH_ATH79_MANGLE_PORT_H
  16 +#define __ASM_MACH_ATH79_MANGLE_PORT_H
  17 +
  18 +#ifdef CONFIG_PCI_AR71XX
  19 +extern unsigned long (ath79_pci_swizzle_b)(unsigned long port);
  20 +extern unsigned long (ath79_pci_swizzle_w)(unsigned long port);
  21 +#else
  22 +#define ath79_pci_swizzle_b(port) (port)
  23 +#define ath79_pci_swizzle_w(port) (port)
  24 +#endif
  25 +
  26 +#define __swizzle_addr_b(port) ath79_pci_swizzle_b(port)
  27 +#define __swizzle_addr_w(port) ath79_pci_swizzle_w(port)
  28 +#define __swizzle_addr_l(port) (port)
  29 +#define __swizzle_addr_q(port) (port)
  30 +
  31 +# define ioswabb(a, x)           (x)
  32 +# define __mem_ioswabb(a, x)     (x)
  33 +# define ioswabw(a, x)           (x)
  34 +# define __mem_ioswabw(a, x)     cpu_to_le16(x)
  35 +# define ioswabl(a, x)           (x)
  36 +# define __mem_ioswabl(a, x)     cpu_to_le32(x)
  37 +# define ioswabq(a, x)           (x)
  38 +# define __mem_ioswabq(a, x)     cpu_to_le64(x)
  39 +
  40 +#endif /* __ASM_MACH_ATH79_MANGLE_PORT_H */
  41 --- a/arch/mips/pci/pci-ar71xx.c
  42 +++ b/arch/mips/pci/pci-ar71xx.c
  43 @@ -71,6 +71,45 @@ static const u32 ar71xx_pci_read_mask[8]
  44         0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0
  45  };
  46
  47 +static unsigned long (*__ath79_pci_swizzle_b)(unsigned long port);
  48 +static unsigned long (*__ath79_pci_swizzle_w)(unsigned long port);
  49 +
  50 +static inline bool ar71xx_is_pci_addr(unsigned long port)
  51 +{
  52 +       unsigned long phys = CPHYSADDR(port);
  53 +
  54 +       return (phys >= AR71XX_PCI_MEM_BASE &&
  55 +               phys < AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE);
  56 +}
  57 +
  58 +static unsigned long ar71xx_pci_swizzle_b(unsigned long port)
  59 +{
  60 +       return ar71xx_is_pci_addr(port) ? port ^ 3 : port;
  61 +}
  62 +
  63 +static unsigned long ar71xx_pci_swizzle_w(unsigned long port)
  64 +{
  65 +       return ar71xx_is_pci_addr(port) ? port ^ 2 : port;
  66 +}
  67 +
  68 +unsigned long ath79_pci_swizzle_b(unsigned long port)
  69 +{
  70 +       if (__ath79_pci_swizzle_b)
  71 +               return __ath79_pci_swizzle_b(port);
  72 +
  73 +       return port;
  74 +}
  75 +EXPORT_SYMBOL(ath79_pci_swizzle_b);
  76 +
  77 +unsigned long ath79_pci_swizzle_w(unsigned long port)
  78 +{
  79 +       if (__ath79_pci_swizzle_w)
  80 +               return __ath79_pci_swizzle_w(port);
  81 +
  82 +       return port;
  83 +}
  84 +EXPORT_SYMBOL(ath79_pci_swizzle_w);
  85 +
  86  static inline u32 ar71xx_pci_get_ble(int where, int size, int local)
  87  {
  88         u32 t;
  89 @@ -279,6 +318,9 @@ static int ar71xx_pci_probe(struct platf
  90
  91         register_pci_controller(&apc->pci_ctrl);
  92
  93 +       __ath79_pci_swizzle_b = ar71xx_pci_swizzle_b;
  94 +       __ath79_pci_swizzle_w = ar71xx_pci_swizzle_w;
  95 +
  96         return 0;
  97  }
  98