target/linux/atheros/patches-3.10/120-spiflash.patch

   1 --- a/drivers/mtd/devices/Kconfig
   2 +++ b/drivers/mtd/devices/Kconfig
   3 @@ -135,6 +135,10 @@ config MTD_BCM47XXSFLASH
   4           registered by bcma as platform devices. This enables driver for
   5           serial flash memories (only read-only mode is implemented).
   6
   7 +config MTD_AR2315
   8 +       tristate "Atheros AR2315+ SPI Flash support"
   9 +       depends on ATHEROS_AR2315
  10 +
  11  config MTD_SLRAM
  12         tristate "Uncached system RAM"
  13         help
  14 --- a/drivers/mtd/devices/Makefile
  15 +++ b/drivers/mtd/devices/Makefile
  16 @@ -15,6 +15,7 @@ obj-$(CONFIG_MTD_M25P80)      += m25p80.o
  17  obj-$(CONFIG_MTD_NAND_OMAP_BCH)        += elm.o
  18  obj-$(CONFIG_MTD_SPEAR_SMI)    += spear_smi.o
  19  obj-$(CONFIG_MTD_SST25L)       += sst25l.o
  20 +obj-$(CONFIG_MTD_AR2315)       += ar2315.o
  21  obj-$(CONFIG_MTD_BCM47XXSFLASH)        += bcm47xxsflash.o
  22
  23
  24 --- /dev/null
  25 +++ b/drivers/mtd/devices/ar2315.c
  26 @@ -0,0 +1,540 @@
  27 +
  28 +/*
  29 + * MTD driver for the SPI Flash Memory support on Atheros AR2315
  30 + *
  31 + * Copyright (c) 2005-2006 Atheros Communications Inc.
  32 + * Copyright (C) 2006-2007 FON Technology, SL.
  33 + * Copyright (C) 2006-2007 Imre Kaloz <kaloz@openwrt.org>
  34 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
  35 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
  36 + *
  37 + * This code is free software; you can redistribute it and/or modify
  38 + * it under the terms of the GNU General Public License version 2 as
  39 + * published by the Free Software Foundation.
  40 + *
  41 + */
  42 +
  43 +#include <linux/kernel.h>
  44 +#include <linux/module.h>
  45 +#include <linux/types.h>
  46 +#include <linux/version.h>
  47 +#include <linux/errno.h>
  48 +#include <linux/slab.h>
  49 +#include <linux/mtd/mtd.h>
  50 +#include <linux/mtd/partitions.h>
  51 +#include <linux/platform_device.h>
  52 +#include <linux/sched.h>
  53 +#include <linux/root_dev.h>
  54 +#include <linux/delay.h>
  55 +#include <linux/io.h>
  56 +
  57 +#include <ar2315_spiflash.h>
  58 +#include <ar231x_platform.h>
  59 +#include <ar231x.h>
  60 +
  61 +
  62 +#define SPIFLASH "spiflash: "
  63 +#define busy_wait(_priv, _condition, _wait) do { \
  64 +       while (_condition) { \
  65 +               spin_unlock_bh(&_priv->lock); \
  66 +               if (_wait > 1) \
  67 +                       msleep(_wait); \
  68 +               else if ((_wait == 1) && need_resched()) \
  69 +                       schedule(); \
  70 +               else \
  71 +                       udelay(1); \
  72 +               spin_lock_bh(&_priv->lock); \
  73 +       } \
  74 +} while (0)
  75 +
  76 +enum {
  77 +       FLASH_NONE,
  78 +       FLASH_1MB,
  79 +       FLASH_2MB,
  80 +       FLASH_4MB,
  81 +       FLASH_8MB,
  82 +       FLASH_16MB,
  83 +};
  84 +
  85 +/* Flash configuration table */
  86 +struct flashconfig {
  87 +       u32 byte_cnt;
  88 +       u32 sector_cnt;
  89 +       u32 sector_size;
  90 +};
  91 +
  92 +const struct flashconfig flashconfig_tbl[] = {
  93 +       [FLASH_NONE] = { 0, 0, 0},
  94 +       [FLASH_1MB]  = { STM_1MB_BYTE_COUNT, STM_1MB_SECTOR_COUNT,
  95 +                        STM_1MB_SECTOR_SIZE},
  96 +       [FLASH_2MB]  = { STM_2MB_BYTE_COUNT, STM_2MB_SECTOR_COUNT,
  97 +                        STM_2MB_SECTOR_SIZE},
  98 +       [FLASH_4MB]  = { STM_4MB_BYTE_COUNT, STM_4MB_SECTOR_COUNT,
  99 +                        STM_4MB_SECTOR_SIZE},
 100 +       [FLASH_8MB]  = { STM_8MB_BYTE_COUNT, STM_8MB_SECTOR_COUNT,
 101 +                        STM_8MB_SECTOR_SIZE},
 102 +       [FLASH_16MB] = { STM_16MB_BYTE_COUNT, STM_16MB_SECTOR_COUNT,
 103 +                        STM_16MB_SECTOR_SIZE}
 104 +};
 105 +
 106 +/* Mapping of generic opcodes to STM serial flash opcodes */
 107 +enum {
 108 +       SPI_WRITE_ENABLE,
 109 +       SPI_WRITE_DISABLE,
 110 +       SPI_RD_STATUS,
 111 +       SPI_WR_STATUS,
 112 +       SPI_RD_DATA,
 113 +       SPI_FAST_RD_DATA,
 114 +       SPI_PAGE_PROGRAM,
 115 +       SPI_SECTOR_ERASE,
 116 +       SPI_BULK_ERASE,
 117 +       SPI_DEEP_PWRDOWN,
 118 +       SPI_RD_SIG,
 119 +};
 120 +
 121 +struct opcodes {
 122 +       __u16 code;
 123 +       __s8 tx_cnt;
 124 +       __s8 rx_cnt;
 125 +};
 126 +
 127 +const struct opcodes stm_opcodes[] = {
 128 +       [SPI_WRITE_ENABLE] = {STM_OP_WR_ENABLE, 1, 0},
 129 +       [SPI_WRITE_DISABLE] = {STM_OP_WR_DISABLE, 1, 0},
 130 +       [SPI_RD_STATUS] = {STM_OP_RD_STATUS, 1, 1},
 131 +       [SPI_WR_STATUS] = {STM_OP_WR_STATUS, 1, 0},
 132 +       [SPI_RD_DATA] = {STM_OP_RD_DATA, 4, 4},
 133 +       [SPI_FAST_RD_DATA] = {STM_OP_FAST_RD_DATA, 5, 0},
 134 +       [SPI_PAGE_PROGRAM] = {STM_OP_PAGE_PGRM, 8, 0},
 135 +       [SPI_SECTOR_ERASE] = {STM_OP_SECTOR_ERASE, 4, 0},
 136 +       [SPI_BULK_ERASE] = {STM_OP_BULK_ERASE, 1, 0},
 137 +       [SPI_DEEP_PWRDOWN] = {STM_OP_DEEP_PWRDOWN, 1, 0},
 138 +       [SPI_RD_SIG] = {STM_OP_RD_SIG, 4, 1},
 139 +};
 140 +
 141 +/* Driver private data structure */
 142 +struct spiflash_priv {
 143 +       struct mtd_info mtd;
 144 +       void *readaddr; /* memory mapped data for read  */
 145 +       void *mmraddr;  /* memory mapped register space */
 146 +       wait_queue_head_t wq;
 147 +       spinlock_t lock;
 148 +       int state;
 149 +};
 150 +
 151 +#define to_spiflash(_mtd) container_of(_mtd, struct spiflash_priv, mtd)
 152 +
 153 +enum {
 154 +       FL_READY,
 155 +       FL_READING,
 156 +       FL_ERASING,
 157 +       FL_WRITING
 158 +};
 159 +
 160 +/*****************************************************************************/
 161 +
 162 +static u32
 163 +spiflash_read_reg(struct spiflash_priv *priv, int reg)
 164 +{
 165 +       return ar231x_read_reg((u32) priv->mmraddr + reg);
 166 +}
 167 +
 168 +static void
 169 +spiflash_write_reg(struct spiflash_priv *priv, int reg, u32 data)
 170 +{
 171 +       ar231x_write_reg((u32) priv->mmraddr + reg, data);
 172 +}
 173 +
 174 +static u32
 175 +spiflash_wait_busy(struct spiflash_priv *priv)
 176 +{
 177 +       u32 reg;
 178 +
 179 +       busy_wait(priv, (reg = spiflash_read_reg(priv, SPI_FLASH_CTL)) &
 180 +               SPI_CTL_BUSY, 0);
 181 +       return reg;
 182 +}
 183 +
 184 +static u32
 185 +spiflash_sendcmd(struct spiflash_priv *priv, int opcode, u32 addr)
 186 +{
 187 +       const struct opcodes *op;
 188 +       u32 reg, mask;
 189 +
 190 +       op = &stm_opcodes[opcode];
 191 +       reg = spiflash_wait_busy(priv);
 192 +       spiflash_write_reg(priv, SPI_FLASH_OPCODE,
 193 +               ((u32) op->code) | (addr << 8));
 194 +
 195 +       reg &= ~SPI_CTL_TX_RX_CNT_MASK;
 196 +       reg |= SPI_CTL_START | op->tx_cnt | (op->rx_cnt << 4);
 197 +
 198 +       spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
 199 +       spiflash_wait_busy(priv);
 200 +
 201 +       if (!op->rx_cnt)
 202 +               return 0;
 203 +
 204 +       reg = spiflash_read_reg(priv, SPI_FLASH_DATA);
 205 +
 206 +       switch (op->rx_cnt) {
 207 +       case 1:
 208 +               mask = 0x000000ff;
 209 +               break;
 210 +       case 2:
 211 +               mask = 0x0000ffff;
 212 +               break;
 213 +       case 3:
 214 +               mask = 0x00ffffff;
 215 +               break;
 216 +       default:
 217 +               mask = 0xffffffff;
 218 +               break;
 219 +       }
 220 +       reg &= mask;
 221 +
 222 +       return reg;
 223 +}
 224 +
 225 +
 226 +/*
 227 + * Probe SPI flash device
 228 + * Function returns 0 for failure.
 229 + * and flashconfig_tbl array index for success.
 230 + */
 231 +static int
 232 +spiflash_probe_chip(struct spiflash_priv *priv)
 233 +{
 234 +       u32 sig;
 235 +       int flash_size;
 236 +
 237 +       /* Read the signature on the flash device */
 238 +       spin_lock_bh(&priv->lock);
 239 +       sig = spiflash_sendcmd(priv, SPI_RD_SIG, 0);
 240 +       spin_unlock_bh(&priv->lock);
 241 +
 242 +       switch (sig) {
 243 +       case STM_8MBIT_SIGNATURE:
 244 +               flash_size = FLASH_1MB;
 245 +               break;
 246 +       case STM_16MBIT_SIGNATURE:
 247 +               flash_size = FLASH_2MB;
 248 +               break;
 249 +       case STM_32MBIT_SIGNATURE:
 250 +               flash_size = FLASH_4MB;
 251 +               break;
 252 +       case STM_64MBIT_SIGNATURE:
 253 +               flash_size = FLASH_8MB;
 254 +               break;
 255 +       case STM_128MBIT_SIGNATURE:
 256 +               flash_size = FLASH_16MB;
 257 +               break;
 258 +       default:
 259 +               pr_warn(SPIFLASH "Read of flash device signature failed!\n");
 260 +               return 0;
 261 +       }
 262 +
 263 +       return flash_size;
 264 +}
 265 +
 266 +
 267 +/* wait until the flash chip is ready and grab a lock */
 268 +static int spiflash_wait_ready(struct spiflash_priv *priv, int state)
 269 +{
 270 +       DECLARE_WAITQUEUE(wait, current);
 271 +
 272 +retry:
 273 +       spin_lock_bh(&priv->lock);
 274 +       if (priv->state != FL_READY) {
 275 +               set_current_state(TASK_UNINTERRUPTIBLE);
 276 +               add_wait_queue(&priv->wq, &wait);
 277 +               spin_unlock_bh(&priv->lock);
 278 +               schedule();
 279 +               remove_wait_queue(&priv->wq, &wait);
 280 +
 281 +               if (signal_pending(current))
 282 +                       return 0;
 283 +
 284 +               goto retry;
 285 +       }
 286 +       priv->state = state;
 287 +
 288 +       return 1;
 289 +}
 290 +
 291 +static inline void spiflash_done(struct spiflash_priv *priv)
 292 +{
 293 +       priv->state = FL_READY;
 294 +       spin_unlock_bh(&priv->lock);
 295 +       wake_up(&priv->wq);
 296 +}
 297 +
 298 +static void
 299 +spiflash_wait_complete(struct spiflash_priv *priv, unsigned int timeout)
 300 +{
 301 +       busy_wait(priv, spiflash_sendcmd(priv, SPI_RD_STATUS, 0) &
 302 +               SPI_STATUS_WIP, timeout);
 303 +       spiflash_done(priv);
 304 +}
 305 +
 306 +
 307 +
 308 +static int
 309 +spiflash_erase(struct mtd_info *mtd, struct erase_info *instr)
 310 +{
 311 +       struct spiflash_priv *priv = to_spiflash(mtd);
 312 +       const struct opcodes *op;
 313 +       u32 temp, reg;
 314 +
 315 +       if (instr->addr + instr->len > mtd->size)
 316 +               return -EINVAL;
 317 +
 318 +       if (!spiflash_wait_ready(priv, FL_ERASING))
 319 +               return -EINTR;
 320 +
 321 +       spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0);
 322 +       reg = spiflash_wait_busy(priv);
 323 +
 324 +       op = &stm_opcodes[SPI_SECTOR_ERASE];
 325 +       temp = ((u32)instr->addr << 8) | (u32)(op->code);
 326 +       spiflash_write_reg(priv, SPI_FLASH_OPCODE, temp);
 327 +
 328 +       reg &= ~SPI_CTL_TX_RX_CNT_MASK;
 329 +       reg |= op->tx_cnt | SPI_CTL_START;
 330 +       spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
 331 +
 332 +       spiflash_wait_complete(priv, 20);
 333 +
 334 +       instr->state = MTD_ERASE_DONE;
 335 +       mtd_erase_callback(instr);
 336 +
 337 +       return 0;
 338 +}
 339 +
 340 +static int
 341 +spiflash_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen,
 342 +             u_char *buf)
 343 +{
 344 +       struct spiflash_priv *priv = to_spiflash(mtd);
 345 +       u8 *read_addr;
 346 +
 347 +       if (!len)
 348 +               return 0;
 349 +
 350 +       if (from + len > mtd->size)
 351 +               return -EINVAL;
 352 +
 353 +       *retlen = len;
 354 +
 355 +       if (!spiflash_wait_ready(priv, FL_READING))
 356 +               return -EINTR;
 357 +
 358 +       read_addr = (u8 *)(priv->readaddr + from);
 359 +       memcpy_fromio(buf, read_addr, len);
 360 +       spiflash_done(priv);
 361 +
 362 +       return 0;
 363 +}
 364 +
 365 +static int
 366 +spiflash_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen,
 367 +              const u8 *buf)
 368 +{
 369 +       struct spiflash_priv *priv = to_spiflash(mtd);
 370 +       u32 opcode, bytes_left;
 371 +
 372 +       *retlen = 0;
 373 +
 374 +       if (!len)
 375 +               return 0;
 376 +
 377 +       if (to + len > mtd->size)
 378 +               return -EINVAL;
 379 +
 380 +       bytes_left = len;
 381 +
 382 +       do {
 383 +               u32 read_len, reg, page_offset, spi_data = 0;
 384 +
 385 +               read_len = min(bytes_left, sizeof(u32));
 386 +
 387 +               /* 32-bit writes cannot span across a page boundary
 388 +                * (256 bytes). This types of writes require two page
 389 +                * program operations to handle it correctly. The STM part
 390 +                * will write the overflow data to the beginning of the
 391 +                * current page as opposed to the subsequent page.
 392 +                */
 393 +               page_offset = (to & (STM_PAGE_SIZE - 1)) + read_len;
 394 +
 395 +               if (page_offset > STM_PAGE_SIZE)
 396 +                       read_len -= (page_offset - STM_PAGE_SIZE);
 397 +
 398 +               if (!spiflash_wait_ready(priv, FL_WRITING))
 399 +                       return -EINTR;
 400 +
 401 +               spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0);
 402 +               spi_data = 0;
 403 +               switch (read_len) {
 404 +               case 4:
 405 +                       spi_data |= buf[3] << 24;
 406 +                       /* fall through */
 407 +               case 3:
 408 +                       spi_data |= buf[2] << 16;
 409 +                       /* fall through */
 410 +               case 2:
 411 +                       spi_data |= buf[1] << 8;
 412 +                       /* fall through */
 413 +               case 1:
 414 +                       spi_data |= buf[0] & 0xff;
 415 +                       break;
 416 +               default:
 417 +                       break;
 418 +               }
 419 +
 420 +               spiflash_write_reg(priv, SPI_FLASH_DATA, spi_data);
 421 +               opcode = stm_opcodes[SPI_PAGE_PROGRAM].code |
 422 +                       (to & 0x00ffffff) << 8;
 423 +               spiflash_write_reg(priv, SPI_FLASH_OPCODE, opcode);
 424 +
 425 +               reg = spiflash_read_reg(priv, SPI_FLASH_CTL);
 426 +               reg &= ~SPI_CTL_TX_RX_CNT_MASK;
 427 +               reg |= (read_len + 4) | SPI_CTL_START;
 428 +               spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
 429 +
 430 +               spiflash_wait_complete(priv, 1);
 431 +
 432 +               bytes_left -= read_len;
 433 +               to += read_len;
 434 +               buf += read_len;
 435 +
 436 +               *retlen += read_len;
 437 +       } while (bytes_left != 0);
 438 +
 439 +       return 0;
 440 +}
 441 +
 442 +
 443 +#if defined CONFIG_MTD_REDBOOT_PARTS || CONFIG_MTD_MYLOADER_PARTS
 444 +static const char * const part_probe_types[] = {
 445 +       "cmdlinepart", "RedBoot", "MyLoader", NULL
 446 +};
 447 +#endif
 448 +
 449 +
 450 +static int
 451 +spiflash_probe(struct platform_device *pdev)
 452 +{
 453 +       struct spiflash_priv *priv;
 454 +       struct mtd_info *mtd;
 455 +       struct resource *res;
 456 +       int index;
 457 +       int result = 0;
 458 +
 459 +       priv = kzalloc(sizeof(struct spiflash_priv), GFP_KERNEL);
 460 +       spin_lock_init(&priv->lock);
 461 +       init_waitqueue_head(&priv->wq);
 462 +       priv->state = FL_READY;
 463 +       mtd = &priv->mtd;
 464 +
 465 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 466 +       if (!res) {
 467 +               dev_err(&pdev->dev, "No MMR resource found\n");
 468 +               goto error;
 469 +       }
 470 +
 471 +       priv->mmraddr = ioremap_nocache(res->start, resource_size(res));
 472 +       if (!priv->mmraddr) {
 473 +               dev_warn(&pdev->dev, SPIFLASH "Failed to map flash device\n");
 474 +               goto error;
 475 +       }
 476 +
 477 +       index = spiflash_probe_chip(priv);
 478 +       if (!index) {
 479 +               dev_warn(&pdev->dev, SPIFLASH "Found no flash device\n");
 480 +               goto error;
 481 +       }
 482 +
 483 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 484 +       if (!res) {
 485 +               dev_err(&pdev->dev, "No flash readmem resource found\n");
 486 +               goto error;
 487 +       }
 488 +
 489 +       priv->readaddr = ioremap_nocache(res->start,
 490 +                                        flashconfig_tbl[index].byte_cnt);
 491 +       if (!priv->readaddr) {
 492 +               dev_warn(&pdev->dev, SPIFLASH "Failed to map flash device\n");
 493 +               goto error;
 494 +       }
 495 +
 496 +       platform_set_drvdata(pdev, priv);
 497 +       mtd->name = "spiflash";
 498 +       mtd->type = MTD_NORFLASH;
 499 +       mtd->flags = (MTD_CAP_NORFLASH|MTD_WRITEABLE);
 500 +       mtd->size = flashconfig_tbl[index].byte_cnt;
 501 +       mtd->erasesize = flashconfig_tbl[index].sector_size;
 502 +       mtd->writesize = 1;
 503 +       mtd->numeraseregions = 0;
 504 +       mtd->eraseregions = NULL;
 505 +       mtd->_erase = spiflash_erase;
 506 +       mtd->_read = spiflash_read;
 507 +       mtd->_write = spiflash_write;
 508 +       mtd->owner = THIS_MODULE;
 509 +
 510 +       dev_info(&pdev->dev, "%lld Kbytes flash detected\n", mtd->size >> 10);
 511 +
 512 +#if defined CONFIG_MTD_REDBOOT_PARTS || CONFIG_MTD_MYLOADER_PARTS
 513 +       /* parse redboot partitions */
 514 +
 515 +       result = mtd_device_parse_register(mtd, part_probe_types,
 516 +                       NULL, NULL, 0);
 517 +#endif
 518 +
 519 +       return result;
 520 +
 521 +error:
 522 +       if (priv->mmraddr)
 523 +               iounmap(priv->mmraddr);
 524 +       kfree(priv);
 525 +       return -ENXIO;
 526 +}
 527 +
 528 +static int
 529 +spiflash_remove(struct platform_device *pdev)
 530 +{
 531 +       struct spiflash_priv *priv = platform_get_drvdata(pdev);
 532 +       struct mtd_info *mtd = &priv->mtd;
 533 +
 534 +       mtd_device_unregister(mtd);
 535 +       iounmap(priv->mmraddr);
 536 +       iounmap(priv->readaddr);
 537 +       kfree(priv);
 538 +
 539 +       return 0;
 540 +}
 541 +
 542 +struct platform_driver spiflash_driver = {
 543 +       .driver.name = "spiflash",
 544 +       .probe = spiflash_probe,
 545 +       .remove = spiflash_remove,
 546 +};
 547 +
 548 +int __init
 549 +spiflash_init(void)
 550 +{
 551 +       return platform_driver_register(&spiflash_driver);
 552 +}
 553 +
 554 +void __exit
 555 +spiflash_exit(void)
 556 +{
 557 +       return platform_driver_unregister(&spiflash_driver);
 558 +}
 559 +
 560 +module_init(spiflash_init);
 561 +module_exit(spiflash_exit);
 562 +
 563 +MODULE_LICENSE("GPL");
 564 +MODULE_AUTHOR("OpenWrt.org, Atheros Communications Inc");
 565 +MODULE_DESCRIPTION("MTD driver for SPI Flash on Atheros SOC");
 566 +
 567 --- /dev/null
 568 +++ b/arch/mips/include/asm/mach-ar231x/ar2315_spiflash.h
 569 @@ -0,0 +1,116 @@
 570 +/*
 571 + * SPI Flash Memory support header file.
 572 + *
 573 + * Copyright (c) 2005, Atheros Communications Inc.
 574 + * Copyright (C) 2006 FON Technology, SL.
 575 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
 576 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
 577 + *
 578 + * This code is free software; you can redistribute it and/or modify
 579 + * it under the terms of the GNU General Public License version 2 as
 580 + * published by the Free Software Foundation.
 581 + *
 582 + */
 583 +#ifndef __AR2315_SPIFLASH_H
 584 +#define __AR2315_SPIFLASH_H
 585 +
 586 +#define STM_PAGE_SIZE           256
 587 +
 588 +#define SFI_WRITE_BUFFER_SIZE   4
 589 +#define SFI_FLASH_ADDR_MASK     0x00ffffff
 590 +
 591 +#define STM_8MBIT_SIGNATURE     0x13
 592 +#define STM_M25P80_BYTE_COUNT   1048576
 593 +#define STM_M25P80_SECTOR_COUNT 16
 594 +#define STM_M25P80_SECTOR_SIZE  0x10000
 595 +
 596 +#define STM_16MBIT_SIGNATURE    0x14
 597 +#define STM_M25P16_BYTE_COUNT   2097152
 598 +#define STM_M25P16_SECTOR_COUNT 32
 599 +#define STM_M25P16_SECTOR_SIZE  0x10000
 600 +
 601 +#define STM_32MBIT_SIGNATURE    0x15
 602 +#define STM_M25P32_BYTE_COUNT   4194304
 603 +#define STM_M25P32_SECTOR_COUNT 64
 604 +#define STM_M25P32_SECTOR_SIZE  0x10000
 605 +
 606 +#define STM_64MBIT_SIGNATURE    0x16
 607 +#define STM_M25P64_BYTE_COUNT   8388608
 608 +#define STM_M25P64_SECTOR_COUNT 128
 609 +#define STM_M25P64_SECTOR_SIZE  0x10000
 610 +
 611 +#define STM_128MBIT_SIGNATURE   0x17
 612 +#define STM_M25P128_BYTE_COUNT   16777216
 613 +#define STM_M25P128_SECTOR_COUNT 256
 614 +#define STM_M25P128_SECTOR_SIZE  0x10000
 615 +
 616 +#define STM_1MB_BYTE_COUNT   STM_M25P80_BYTE_COUNT
 617 +#define STM_1MB_SECTOR_COUNT STM_M25P80_SECTOR_COUNT
 618 +#define STM_1MB_SECTOR_SIZE  STM_M25P80_SECTOR_SIZE
 619 +#define STM_2MB_BYTE_COUNT   STM_M25P16_BYTE_COUNT
 620 +#define STM_2MB_SECTOR_COUNT STM_M25P16_SECTOR_COUNT
 621 +#define STM_2MB_SECTOR_SIZE  STM_M25P16_SECTOR_SIZE
 622 +#define STM_4MB_BYTE_COUNT   STM_M25P32_BYTE_COUNT
 623 +#define STM_4MB_SECTOR_COUNT STM_M25P32_SECTOR_COUNT
 624 +#define STM_4MB_SECTOR_SIZE  STM_M25P32_SECTOR_SIZE
 625 +#define STM_8MB_BYTE_COUNT   STM_M25P64_BYTE_COUNT
 626 +#define STM_8MB_SECTOR_COUNT STM_M25P64_SECTOR_COUNT
 627 +#define STM_8MB_SECTOR_SIZE  STM_M25P64_SECTOR_SIZE
 628 +#define STM_16MB_BYTE_COUNT   STM_M25P128_BYTE_COUNT
 629 +#define STM_16MB_SECTOR_COUNT STM_M25P128_SECTOR_COUNT
 630 +#define STM_16MB_SECTOR_SIZE  STM_M25P128_SECTOR_SIZE
 631 +
 632 +/*
 633 + * ST Microelectronics Opcodes for Serial Flash
 634 + */
 635 +
 636 +#define STM_OP_WR_ENABLE       0x06     /* Write Enable */
 637 +#define STM_OP_WR_DISABLE      0x04     /* Write Disable */
 638 +#define STM_OP_RD_STATUS       0x05     /* Read Status */
 639 +#define STM_OP_WR_STATUS       0x01     /* Write Status */
 640 +#define STM_OP_RD_DATA         0x03     /* Read Data */
 641 +#define STM_OP_FAST_RD_DATA    0x0b     /* Fast Read Data */
 642 +#define STM_OP_PAGE_PGRM       0x02     /* Page Program */
 643 +#define STM_OP_SECTOR_ERASE    0xd8     /* Sector Erase */
 644 +#define STM_OP_BULK_ERASE      0xc7     /* Bulk Erase */
 645 +#define STM_OP_DEEP_PWRDOWN    0xb9     /* Deep Power-Down Mode */
 646 +#define STM_OP_RD_SIG          0xab     /* Read Electronic Signature */
 647 +
 648 +#define STM_STATUS_WIP       0x01       /* Write-In-Progress */
 649 +#define STM_STATUS_WEL       0x02       /* Write Enable Latch */
 650 +#define STM_STATUS_BP0       0x04       /* Block Protect 0 */
 651 +#define STM_STATUS_BP1       0x08       /* Block Protect 1 */
 652 +#define STM_STATUS_BP2       0x10       /* Block Protect 2 */
 653 +#define STM_STATUS_SRWD      0x80       /* Status Register Write Disable */
 654 +
 655 +/*
 656 + * SPI Flash Interface Registers
 657 + */
 658 +#define AR531XPLUS_SPI_READ     0x08000000
 659 +#define AR531XPLUS_SPI_MMR      0x11300000
 660 +#define AR531XPLUS_SPI_MMR_SIZE 12
 661 +
 662 +#define AR531XPLUS_SPI_CTL      0x00
 663 +#define AR531XPLUS_SPI_OPCODE   0x04
 664 +#define AR531XPLUS_SPI_DATA     0x08
 665 +
 666 +#define SPI_FLASH_READ          AR531XPLUS_SPI_READ
 667 +#define SPI_FLASH_MMR           AR531XPLUS_SPI_MMR
 668 +#define SPI_FLASH_MMR_SIZE      AR531XPLUS_SPI_MMR_SIZE
 669 +#define SPI_FLASH_CTL           AR531XPLUS_SPI_CTL
 670 +#define SPI_FLASH_OPCODE        AR531XPLUS_SPI_OPCODE
 671 +#define SPI_FLASH_DATA          AR531XPLUS_SPI_DATA
 672 +
 673 +#define SPI_CTL_START           0x00000100
 674 +#define SPI_CTL_BUSY            0x00010000
 675 +#define SPI_CTL_TXCNT_MASK      0x0000000f
 676 +#define SPI_CTL_RXCNT_MASK      0x000000f0
 677 +#define SPI_CTL_TX_RX_CNT_MASK  0x000000ff
 678 +#define SPI_CTL_SIZE_MASK       0x00060000
 679 +
 680 +#define SPI_CTL_CLK_SEL_MASK    0x03000000
 681 +#define SPI_OPCODE_MASK         0x000000ff
 682 +
 683 +#define SPI_STATUS_WIP         STM_STATUS_WIP
 684 +
 685 +#endif