24533574bc8e24a32127c12ca1ffc7bff0dca64a
[openwrt/openwrt.git] / target / linux / atheros / patches-3.14 / 100-board.patch
1 --- a/arch/mips/Kconfig
2 +++ b/arch/mips/Kconfig
3 @@ -144,6 +144,19 @@ config BCM63XX
4 help
5 Support for BCM63XX based boards
6
7 +config ATHEROS_AR231X
8 + bool "Atheros 231x/531x SoC support"
9 + select CEVT_R4K
10 + select CSRC_R4K
11 + select DMA_NONCOHERENT
12 + select IRQ_CPU
13 + select SYS_HAS_CPU_MIPS32_R1
14 + select SYS_SUPPORTS_BIG_ENDIAN
15 + select SYS_SUPPORTS_32BIT_KERNEL
16 + select ARCH_REQUIRE_GPIOLIB
17 + help
18 + Support for AR231x and AR531x based boards
19 +
20 config MIPS_COBALT
21 bool "Cobalt Server"
22 select CEVT_R4K
23 @@ -795,6 +808,7 @@ config NLM_XLP_BOARD
24
25 endchoice
26
27 +source "arch/mips/ar231x/Kconfig"
28 source "arch/mips/alchemy/Kconfig"
29 source "arch/mips/ath79/Kconfig"
30 source "arch/mips/bcm47xx/Kconfig"
31 --- a/arch/mips/Kbuild.platforms
32 +++ b/arch/mips/Kbuild.platforms
33 @@ -6,6 +6,7 @@ platforms += ath79
34 platforms += bcm47xx
35 platforms += bcm63xx
36 platforms += cavium-octeon
37 +platforms += ar231x
38 platforms += cobalt
39 platforms += dec
40 platforms += emma
41 --- /dev/null
42 +++ b/arch/mips/ar231x/Platform
43 @@ -0,0 +1,6 @@
44 +#
45 +# Atheros AR531X/AR231X WiSoC
46 +#
47 +platform-$(CONFIG_ATHEROS_AR231X) += ar231x/
48 +cflags-$(CONFIG_ATHEROS_AR231X) += -I$(srctree)/arch/mips/include/asm/mach-ar231x
49 +load-$(CONFIG_ATHEROS_AR231X) += 0xffffffff80041000
50 --- /dev/null
51 +++ b/arch/mips/ar231x/Kconfig
52 @@ -0,0 +1,16 @@
53 +config ATHEROS_AR5312
54 + bool "Atheros 5312/2312+ support"
55 + depends on ATHEROS_AR231X
56 + default y
57 +
58 +config ATHEROS_AR2315
59 + bool "Atheros 2315+ support"
60 + depends on ATHEROS_AR231X
61 + select DMA_NONCOHERENT
62 + select CEVT_R4K
63 + select CSRC_R4K
64 + select IRQ_CPU
65 + select SYS_HAS_CPU_MIPS32_R1
66 + select SYS_SUPPORTS_32BIT_KERNEL
67 + select SYS_SUPPORTS_BIG_ENDIAN
68 + default y
69 --- /dev/null
70 +++ b/arch/mips/ar231x/Makefile
71 @@ -0,0 +1,13 @@
72 +#
73 +# This file is subject to the terms and conditions of the GNU General Public
74 +# License. See the file "COPYING" in the main directory of this archive
75 +# for more details.
76 +#
77 +# Copyright (C) 2006 FON Technology, SL.
78 +# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
79 +# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
80 +#
81 +
82 +obj-y += board.o prom.o devices.o
83 +obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o
84 +obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o
85 --- /dev/null
86 +++ b/arch/mips/ar231x/board.c
87 @@ -0,0 +1,229 @@
88 +/*
89 + * This file is subject to the terms and conditions of the GNU General Public
90 + * License. See the file "COPYING" in the main directory of this archive
91 + * for more details.
92 + *
93 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
94 + * Copyright (C) 2006 FON Technology, SL.
95 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
96 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
97 + */
98 +
99 +#include <generated/autoconf.h>
100 +#include <linux/init.h>
101 +#include <linux/module.h>
102 +#include <linux/types.h>
103 +#include <linux/string.h>
104 +#include <linux/platform_device.h>
105 +#include <linux/kernel.h>
106 +#include <linux/random.h>
107 +#include <linux/etherdevice.h>
108 +#include <linux/irq.h>
109 +#include <linux/io.h>
110 +#include <asm/irq_cpu.h>
111 +#include <asm/reboot.h>
112 +#include <asm/bootinfo.h>
113 +#include <asm/time.h>
114 +
115 +#include <ar231x_platform.h>
116 +#include "devices.h"
117 +#include "ar5312.h"
118 +#include "ar2315.h"
119 +
120 +void (*ar231x_irq_dispatch)(void);
121 +
122 +static inline bool check_radio_magic(u8 *addr)
123 +{
124 + addr += 0x7a; /* offset for flash magic */
125 + return (addr[0] == 0x5a) && (addr[1] == 0xa5);
126 +}
127 +
128 +static inline bool check_notempty(u8 *addr)
129 +{
130 + return *(u32 *)addr != 0xffffffff;
131 +}
132 +
133 +static inline bool check_board_data(u8 *flash_limit, u8 *addr, bool broken)
134 +{
135 + /* config magic found */
136 + if (*((u32 *)addr) == AR231X_BD_MAGIC)
137 + return true;
138 +
139 + if (!broken)
140 + return false;
141 +
142 + if (check_radio_magic(addr + 0xf8))
143 + ar231x_board.radio = addr + 0xf8;
144 + if ((addr < flash_limit + 0x10000) &&
145 + check_radio_magic(addr + 0x10000))
146 + ar231x_board.radio = addr + 0x10000;
147 +
148 + if (ar231x_board.radio) {
149 + /* broken board data detected, use radio data to find the
150 + * offset, user will fix this */
151 + return true;
152 + }
153 +
154 + return false;
155 +}
156 +
157 +static u8 * __init find_board_config(u8 *flash_limit, bool broken)
158 +{
159 + u8 *addr;
160 + u8 *begin = flash_limit - 0x1000;
161 + u8 *end = flash_limit - 0x30000;
162 +
163 + for (addr = begin; addr >= end; addr -= 0x1000)
164 + if (check_board_data(flash_limit, addr, broken))
165 + return addr;
166 +
167 + return NULL;
168 +}
169 +
170 +static u8 * __init find_radio_config(u8 *flash_limit, u8 *bcfg)
171 +{
172 + u8 *rcfg, *begin, *end;
173 +
174 + /*
175 + * Now find the start of Radio Configuration data, using heuristics:
176 + * Search forward from Board Configuration data by 0x1000 bytes
177 + * at a time until we find non-0xffffffff.
178 + */
179 + begin = bcfg + 0x1000;
180 + end = flash_limit;
181 + for (rcfg = begin; rcfg < end; rcfg += 0x1000)
182 + if (check_notempty(rcfg) && check_radio_magic(rcfg))
183 + return rcfg;
184 +
185 + /* AR2316 relocates radio config to new location */
186 + begin = bcfg + 0xf8;
187 + end = flash_limit - 0x1000 + 0xf8;
188 + for (rcfg = begin; rcfg < end; rcfg += 0x1000)
189 + if (check_notempty(rcfg) && check_radio_magic(rcfg))
190 + return rcfg;
191 +
192 + pr_warn("WARNING: Could not find Radio Configuration data\n");
193 +
194 + return NULL;
195 +}
196 +
197 +int __init ar231x_find_config(u8 *flash_limit)
198 +{
199 + struct ar231x_boarddata *config;
200 + unsigned int rcfg_size;
201 + int broken_boarddata = 0;
202 + u8 *bcfg, *rcfg;
203 + u8 *board_data;
204 + u8 *radio_data;
205 + u8 *mac_addr;
206 + u32 offset;
207 +
208 + ar231x_board.config = NULL;
209 + ar231x_board.radio = NULL;
210 + /* Copy the board and radio data to RAM, because accessing the mapped
211 + * memory of the flash directly after booting is not safe */
212 +
213 + /* Try to find valid board and radio data */
214 + bcfg = find_board_config(flash_limit, false);
215 +
216 + /* If that fails, try to at least find valid radio data */
217 + if (!bcfg) {
218 + bcfg = find_board_config(flash_limit, true);
219 + broken_boarddata = 1;
220 + }
221 +
222 + if (!bcfg) {
223 + pr_warn("WARNING: No board configuration data found!\n");
224 + return -ENODEV;
225 + }
226 +
227 + board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
228 + ar231x_board.config = (struct ar231x_boarddata *)board_data;
229 + memcpy(board_data, bcfg, 0x100);
230 + if (broken_boarddata) {
231 + pr_warn("WARNING: broken board data detected\n");
232 + config = ar231x_board.config;
233 + if (is_zero_ether_addr(config->enet0_mac)) {
234 + pr_info("Fixing up empty mac addresses\n");
235 + config->reset_config_gpio = 0xffff;
236 + config->sys_led_gpio = 0xffff;
237 + random_ether_addr(config->wlan0_mac);
238 + config->wlan0_mac[0] &= ~0x06;
239 + random_ether_addr(config->enet0_mac);
240 + random_ether_addr(config->enet1_mac);
241 + }
242 + }
243 +
244 + /* Radio config starts 0x100 bytes after board config, regardless
245 + * of what the physical layout on the flash chip looks like */
246 +
247 + if (ar231x_board.radio)
248 + rcfg = (u8 *)ar231x_board.radio;
249 + else
250 + rcfg = find_radio_config(flash_limit, bcfg);
251 +
252 + if (!rcfg)
253 + return -ENODEV;
254 +
255 + radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
256 + ar231x_board.radio = radio_data;
257 + offset = radio_data - board_data;
258 + pr_info("Radio config found at offset 0x%x (0x%x)\n", rcfg - bcfg,
259 + offset);
260 + rcfg_size = BOARD_CONFIG_BUFSZ - offset;
261 + memcpy(radio_data, rcfg, rcfg_size);
262 +
263 + mac_addr = &radio_data[0x1d * 2];
264 + if (is_broadcast_ether_addr(mac_addr)) {
265 + pr_info("Radio MAC is blank; using board-data\n");
266 + ether_addr_copy(mac_addr, ar231x_board.config->wlan0_mac);
267 + }
268 +
269 + return 0;
270 +}
271 +
272 +static void ar231x_halt(void)
273 +{
274 + local_irq_disable();
275 + while (1)
276 + ;
277 +}
278 +
279 +void __init plat_mem_setup(void)
280 +{
281 + _machine_halt = ar231x_halt;
282 + pm_power_off = ar231x_halt;
283 +
284 + ar5312_plat_setup();
285 + ar2315_plat_setup();
286 +
287 + /* Disable data watchpoints */
288 + write_c0_watchlo0(0);
289 +}
290 +
291 +asmlinkage void plat_irq_dispatch(void)
292 +{
293 + ar231x_irq_dispatch();
294 +}
295 +
296 +void __init plat_time_init(void)
297 +{
298 + ar5312_time_init();
299 + ar2315_time_init();
300 +}
301 +
302 +unsigned int __cpuinit get_c0_compare_int(void)
303 +{
304 + return CP0_LEGACY_COMPARE_IRQ;
305 +}
306 +
307 +void __init arch_init_irq(void)
308 +{
309 + clear_c0_status(ST0_IM);
310 + mips_cpu_irq_init();
311 +
312 + /* Initialize interrupt controllers */
313 + ar5312_irq_init();
314 + ar2315_irq_init();
315 +}
316 +
317 --- /dev/null
318 +++ b/arch/mips/ar231x/prom.c
319 @@ -0,0 +1,37 @@
320 +/*
321 + * This file is subject to the terms and conditions of the GNU General Public
322 + * License. See the file "COPYING" in the main directory of this archive
323 + * for more details.
324 + *
325 + * Copyright MontaVista Software Inc
326 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
327 + * Copyright (C) 2006 FON Technology, SL.
328 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
329 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
330 + */
331 +
332 +/*
333 + * Prom setup file for ar231x
334 + */
335 +
336 +#include <linux/init.h>
337 +#include <generated/autoconf.h>
338 +#include <linux/kernel.h>
339 +#include <linux/string.h>
340 +#include <linux/mm.h>
341 +#include <linux/bootmem.h>
342 +
343 +#include <asm/bootinfo.h>
344 +#include <asm/addrspace.h>
345 +#include "ar5312.h"
346 +#include "ar2315.h"
347 +
348 +void __init prom_init(void)
349 +{
350 + ar5312_prom_init();
351 + ar2315_prom_init();
352 +}
353 +
354 +void __init prom_free_prom_memory(void)
355 +{
356 +}
357 --- /dev/null
358 +++ b/arch/mips/include/asm/mach-ar231x/ar231x_platform.h
359 @@ -0,0 +1,85 @@
360 +#ifndef __ASM_MACH_AR231X_PLATFORM_H
361 +#define __ASM_MACH_AR231X_PLATFORM_H
362 +
363 +#include <linux/etherdevice.h>
364 +
365 +/*
366 + * This is board-specific data that is stored in a "fixed" location in flash.
367 + * It is shared across operating systems, so it should not be changed lightly.
368 + * The main reason we need it is in order to extract the ethernet MAC
369 + * address(es).
370 + */
371 +struct ar231x_boarddata {
372 + u32 magic; /* board data is valid */
373 +#define AR231X_BD_MAGIC 0x35333131 /* "5311", for all 531x/231x platforms */
374 + u16 cksum; /* checksum (starting with BD_REV 2) */
375 + u16 rev; /* revision of this struct */
376 +#define BD_REV 4
377 + char board_name[64]; /* Name of board */
378 + u16 major; /* Board major number */
379 + u16 minor; /* Board minor number */
380 + u32 flags; /* Board configuration */
381 +#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
382 +#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
383 +#define BD_UART1 0x00000004 /* UART1 is stuffed */
384 +#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
385 +#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
386 +#define BD_SYSLED 0x00000020 /* System LED stuffed */
387 +#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
388 +#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
389 +#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
390 +#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
391 +#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ mem_cap for testing */
392 +#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
393 +#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
394 +#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
395 +#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
396 +#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
397 +#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
398 +#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
399 + u16 reset_config_gpio; /* Reset factory GPIO pin */
400 + u16 sys_led_gpio; /* System LED GPIO pin */
401 +
402 + u32 cpu_freq; /* CPU core frequency in Hz */
403 + u32 sys_freq; /* System frequency in Hz */
404 + u32 cnt_freq; /* Calculated C0_COUNT frequency */
405 +
406 + u8 wlan0_mac[ETH_ALEN];
407 + u8 enet0_mac[ETH_ALEN];
408 + u8 enet1_mac[ETH_ALEN];
409 +
410 + u16 pci_id; /* Pseudo PCIID for common code */
411 + u16 mem_cap; /* cap bank1 in MB */
412 +
413 + /* version 3 */
414 + u8 wlan1_mac[ETH_ALEN]; /* (ar5212) */
415 +};
416 +
417 +#define BOARD_CONFIG_BUFSZ 0x1000
418 +
419 +/*
420 + * Platform device information for the Wireless MAC
421 + */
422 +struct ar231x_board_config {
423 + u16 devid;
424 +
425 + /* board config data */
426 + struct ar231x_boarddata *config;
427 +
428 + /* radio calibration data */
429 + const char *radio;
430 +};
431 +
432 +/*
433 + * Platform device information for the Ethernet MAC
434 + */
435 +struct ar231x_eth {
436 + void (*reset_set)(u32);
437 + void (*reset_clear)(u32);
438 + u32 reset_mac;
439 + u32 reset_phy;
440 + struct ar231x_board_config *config;
441 + char *macaddr;
442 +};
443 +
444 +#endif /* __ASM_MACH_AR231X_PLATFORM_H */
445 --- /dev/null
446 +++ b/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h
447 @@ -0,0 +1,84 @@
448 +/*
449 + * Atheros AR231x/AR531x SoC specific CPU feature overrides
450 + *
451 + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
452 + *
453 + * This file was derived from: include/asm-mips/cpu-features.h
454 + * Copyright (C) 2003, 2004 Ralf Baechle
455 + * Copyright (C) 2004 Maciej W. Rozycki
456 + *
457 + * This program is free software; you can redistribute it and/or modify it
458 + * under the terms of the GNU General Public License version 2 as published
459 + * by the Free Software Foundation.
460 + *
461 + */
462 +#ifndef __ASM_MACH_AR231X_CPU_FEATURE_OVERRIDES_H
463 +#define __ASM_MACH_AR231X_CPU_FEATURE_OVERRIDES_H
464 +
465 +/*
466 + * The Atheros AR531x/AR231x SoCs have MIPS 4Kc/4KEc core.
467 + */
468 +#define cpu_has_tlb 1
469 +#define cpu_has_4kex 1
470 +#define cpu_has_3k_cache 0
471 +#define cpu_has_4k_cache 1
472 +#define cpu_has_tx39_cache 0
473 +#define cpu_has_sb1_cache 0
474 +#define cpu_has_fpu 0
475 +#define cpu_has_32fpr 0
476 +#define cpu_has_counter 1
477 +/* #define cpu_has_watch ? */
478 +/* #define cpu_has_divec ? */
479 +/* #define cpu_has_vce ? */
480 +/* #define cpu_has_cache_cdex_p ? */
481 +/* #define cpu_has_cache_cdex_s ? */
482 +/* #define cpu_has_prefetch ? */
483 +/* #define cpu_has_mcheck ? */
484 +#define cpu_has_ejtag 1
485 +
486 +#if !defined(CONFIG_ATHEROS_AR5312)
487 +# define cpu_has_llsc 1
488 +#else
489 +/*
490 + * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
491 + * ll/sc instructions.
492 + */
493 +# define cpu_has_llsc 0
494 +#endif
495 +
496 +#define cpu_has_mips16 0
497 +#define cpu_has_mdmx 0
498 +#define cpu_has_mips3d 0
499 +#define cpu_has_smartmips 0
500 +
501 +/* #define cpu_has_vtag_icache ? */
502 +/* #define cpu_has_dc_aliases ? */
503 +/* #define cpu_has_ic_fills_f_dc ? */
504 +/* #define cpu_has_pindexed_dcache ? */
505 +
506 +/* #define cpu_icache_snoops_remote_store ? */
507 +
508 +#define cpu_has_mips32r1 1
509 +
510 +#if !defined(CONFIG_ATHEROS_AR5312)
511 +# define cpu_has_mips32r2 1
512 +#endif
513 +
514 +#define cpu_has_mips64r1 0
515 +#define cpu_has_mips64r2 0
516 +
517 +#define cpu_has_dsp 0
518 +#define cpu_has_mipsmt 0
519 +
520 +/* #define cpu_has_nofpuex ? */
521 +#define cpu_has_64bits 0
522 +#define cpu_has_64bit_zero_reg 0
523 +#define cpu_has_64bit_gp_regs 0
524 +#define cpu_has_64bit_addresses 0
525 +
526 +/* #define cpu_has_inclusive_pcaches ? */
527 +
528 +/* #define cpu_dcache_line_size() ? */
529 +/* #define cpu_icache_line_size() ? */
530 +
531 +#endif /* __ASM_MACH_AR231X_CPU_FEATURE_OVERRIDES_H */
532 --- /dev/null
533 +++ b/arch/mips/include/asm/mach-ar231x/dma-coherence.h
534 @@ -0,0 +1,77 @@
535 +/*
536 + * This file is subject to the terms and conditions of the GNU General Public
537 + * License. See the file "COPYING" in the main directory of this archive
538 + * for more details.
539 + *
540 + * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
541 + * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
542 + *
543 + */
544 +#ifndef __ASM_MACH_AR231X_DMA_COHERENCE_H
545 +#define __ASM_MACH_AR231X_DMA_COHERENCE_H
546 +
547 +#define PCI_DMA_OFFSET 0x20000000
548 +
549 +#include <linux/device.h>
550 +
551 +static inline dma_addr_t ar231x_dev_offset(struct device *dev)
552 +{
553 +#ifdef CONFIG_PCI
554 + extern struct bus_type pci_bus_type;
555 +
556 + if (dev && dev->bus == &pci_bus_type)
557 + return PCI_DMA_OFFSET;
558 +#endif
559 + return 0;
560 +}
561 +
562 +static inline dma_addr_t
563 +plat_map_dma_mem(struct device *dev, void *addr, size_t size)
564 +{
565 + return virt_to_phys(addr) + ar231x_dev_offset(dev);
566 +}
567 +
568 +static inline dma_addr_t
569 +plat_map_dma_mem_page(struct device *dev, struct page *page)
570 +{
571 + return page_to_phys(page) + ar231x_dev_offset(dev);
572 +}
573 +
574 +static inline unsigned long
575 +plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
576 +{
577 + return dma_addr - ar231x_dev_offset(dev);
578 +}
579 +
580 +static inline void
581 +plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, size_t size,
582 + enum dma_data_direction direction)
583 +{
584 +}
585 +
586 +static inline int plat_dma_supported(struct device *dev, u64 mask)
587 +{
588 + return 1;
589 +}
590 +
591 +static inline void plat_extra_sync_for_device(struct device *dev)
592 +{
593 +}
594 +
595 +static inline int plat_dma_mapping_error(struct device *dev,
596 + dma_addr_t dma_addr)
597 +{
598 + return 0;
599 +}
600 +
601 +static inline int plat_device_is_coherent(struct device *dev)
602 +{
603 +#ifdef CONFIG_DMA_COHERENT
604 + return 1;
605 +#endif
606 +#ifdef CONFIG_DMA_NONCOHERENT
607 + return 0;
608 +#endif
609 +}
610 +
611 +#endif /* __ASM_MACH_AR231X_DMA_COHERENCE_H */
612 --- /dev/null
613 +++ b/arch/mips/include/asm/mach-ar231x/gpio.h
614 @@ -0,0 +1,30 @@
615 +#ifndef __ASM_MACH_AR231X_GPIO_H
616 +#define __ASM_MACH_AR231X_GPIO_H
617 +
618 +#include <ar231x.h>
619 +
620 +#define gpio_get_value __gpio_get_value
621 +#define gpio_set_value __gpio_set_value
622 +#define gpio_cansleep __gpio_cansleep
623 +
624 +/*
625 + * Wrappers for the generic GPIO layer
626 + */
627 +
628 +/* not sure if these are used? */
629 +
630 +/* Returns IRQ to attach for gpio. Unchecked function */
631 +static inline int gpio_to_irq(unsigned gpio)
632 +{
633 + return AR231X_GPIO_IRQ(gpio);
634 +}
635 +
636 +/* Returns gpio for IRQ attached. Unchecked function */
637 +static inline int irq_to_gpio(unsigned irq)
638 +{
639 + return irq - AR231X_GPIO_IRQ(0);
640 +}
641 +
642 +#include <asm-generic/gpio.h> /* cansleep wrappers */
643 +
644 +#endif /* __ASM_MACH_AR231X_GPIO_H */
645 --- /dev/null
646 +++ b/arch/mips/include/asm/mach-ar231x/reset.h
647 @@ -0,0 +1,6 @@
648 +#ifndef __ASM_MACH_AR231X_RESET_H
649 +#define __ASM_MACH_AR231X_RESET_H
650 +
651 +void ar231x_disable_reset_button(void);
652 +
653 +#endif /* __ASM_MACH_AR231X_RESET_H */
654 --- /dev/null
655 +++ b/arch/mips/include/asm/mach-ar231x/war.h
656 @@ -0,0 +1,25 @@
657 +/*
658 + * This file is subject to the terms and conditions of the GNU General Public
659 + * License. See the file "COPYING" in the main directory of this archive
660 + * for more details.
661 + *
662 + * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
663 + */
664 +#ifndef __ASM_MACH_AR231X_WAR_H
665 +#define __ASM_MACH_AR231X_WAR_H
666 +
667 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
668 +#define R4600_V1_HIT_CACHEOP_WAR 0
669 +#define R4600_V2_HIT_CACHEOP_WAR 0
670 +#define R5432_CP0_INTERRUPT_WAR 0
671 +#define BCM1250_M3_WAR 0
672 +#define SIBYTE_1956_WAR 0
673 +#define MIPS4K_ICACHE_REFILL_WAR 0
674 +#define MIPS_CACHE_SYNC_WAR 0
675 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
676 +#define RM9000_CDEX_SMP_WAR 0
677 +#define ICACHE_REFILLS_WORKAROUND_WAR 0
678 +#define R10000_LLSC_WAR 0
679 +#define MIPS34K_MISSED_ITLB_WAR 0
680 +
681 +#endif /* __ASM_MACH_AR231X_WAR_H */
682 --- /dev/null
683 +++ b/arch/mips/include/asm/mach-ar231x/ar2315_regs.h
684 @@ -0,0 +1,617 @@
685 +/*
686 + * Register definitions for AR2315+
687 + *
688 + * This file is subject to the terms and conditions of the GNU General Public
689 + * License. See the file "COPYING" in the main directory of this archive
690 + * for more details.
691 + *
692 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
693 + * Copyright (C) 2006 FON Technology, SL.
694 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
695 + * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
696 + */
697 +
698 +#ifndef __ASM_MACH_AR231X_AR2315_REGS_H
699 +#define __ASM_MACH_AR231X_AR2315_REGS_H
700 +
701 +/*
702 + * IRQs
703 + */
704 +#define AR2315_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
705 +#define AR2315_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
706 +#define AR2315_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
707 +#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
708 +#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
709 +
710 +
711 +/*
712 + * Miscellaneous interrupts, which share IP2.
713 + */
714 +#define AR2315_MISC_IRQ_NONE (AR231X_MISC_IRQ_BASE+0)
715 +#define AR2315_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+1)
716 +#define AR2315_MISC_IRQ_I2C_RSVD (AR231X_MISC_IRQ_BASE+2)
717 +#define AR2315_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+3)
718 +#define AR2315_MISC_IRQ_AHB (AR231X_MISC_IRQ_BASE+4)
719 +#define AR2315_MISC_IRQ_APB (AR231X_MISC_IRQ_BASE+5)
720 +#define AR2315_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+6)
721 +#define AR2315_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+7)
722 +#define AR2315_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+8)
723 +#define AR2315_MISC_IRQ_IR_RSVD (AR231X_MISC_IRQ_BASE+9)
724 +#define AR2315_MISC_IRQ_COUNT 10
725 +
726 +
727 +/*
728 + * Address map
729 + */
730 +#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */
731 +#define AR2315_WLAN0 0x10000000 /* Wireless MMR */
732 +#define AR2315_PCI 0x10100000 /* PCI MMR */
733 +#define AR2315_SDRAMCTL 0x10300000 /* SDRAM MMR */
734 +#define AR2315_LOCAL 0x10400000 /* LOCAL BUS MMR */
735 +#define AR2315_ENET0 0x10500000 /* ETHERNET MMR */
736 +#define AR2315_DSLBASE 0x11000000 /* RESET CONTROL MMR */
737 +#define AR2315_UART0 0x11100000 /* UART MMR */
738 +#define AR2315_SPI_MMR 0x11300000 /* SPI FLASH MMR */
739 +#define AR2315_PCIEXT 0x80000000 /* pci external */
740 +
741 +/* MII registers offset inside Ethernet MMR region */
742 +#define AR2315_ENET0_MII (AR2315_ENET0 + 0x14)
743 +
744 +/*
745 + * Reset Register
746 + */
747 +#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000)
748 +
749 +#define AR2315_RESET_COLD_AHB 0x00000001
750 +#define AR2315_RESET_COLD_APB 0x00000002
751 +#define AR2315_RESET_COLD_CPU 0x00000004
752 +#define AR2315_RESET_COLD_CPUWARM 0x00000008
753 +#define AR2315_RESET_SYSTEM \
754 + (RESET_COLD_CPU |\
755 + RESET_COLD_APB |\
756 + RESET_COLD_AHB) /* full system */
757 +#define AR2317_RESET_SYSTEM 0x00000010
758 +
759 +
760 +#define AR2315_RESET (AR2315_DSLBASE + 0x0004)
761 +
762 +/* warm reset WLAN0 MAC */
763 +#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001
764 +/* warm reset WLAN0 BaseBand */
765 +#define AR2315_RESET_WARM_WLAN0_BB 0x00000002
766 +/* warm reset MPEG-TS */
767 +#define AR2315_RESET_MPEGTS_RSVD 0x00000004
768 +/* warm reset PCI ahb/dma */
769 +#define AR2315_RESET_PCIDMA 0x00000008
770 +/* warm reset memory controller */
771 +#define AR2315_RESET_MEMCTL 0x00000010
772 +/* warm reset local bus */
773 +#define AR2315_RESET_LOCAL 0x00000020
774 +/* warm reset I2C bus */
775 +#define AR2315_RESET_I2C_RSVD 0x00000040
776 +/* warm reset SPI interface */
777 +#define AR2315_RESET_SPI 0x00000080
778 +/* warm reset UART0 */
779 +#define AR2315_RESET_UART0 0x00000100
780 +/* warm reset IR interface */
781 +#define AR2315_RESET_IR_RSVD 0x00000200
782 +/* cold reset ENET0 phy */
783 +#define AR2315_RESET_EPHY0 0x00000400
784 +/* cold reset ENET0 mac */
785 +#define AR2315_RESET_ENET0 0x00000800
786 +
787 +/*
788 + * AHB master arbitration control
789 + */
790 +#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008)
791 +
792 +/* CPU, default */
793 +#define AR2315_ARB_CPU 0x00000001
794 +/* WLAN */
795 +#define AR2315_ARB_WLAN 0x00000002
796 +/* MPEG-TS */
797 +#define AR2315_ARB_MPEGTS_RSVD 0x00000004
798 +/* LOCAL */
799 +#define AR2315_ARB_LOCAL 0x00000008
800 +/* PCI */
801 +#define AR2315_ARB_PCI 0x00000010
802 +/* Ethernet */
803 +#define AR2315_ARB_ETHERNET 0x00000020
804 +/* retry policy, debug only */
805 +#define AR2315_ARB_RETRY 0x00000100
806 +
807 +/*
808 + * Config Register
809 + */
810 +#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c)
811 +
812 +/* EC - AHB bridge endianess */
813 +#define AR2315_CONFIG_AHB 0x00000001
814 +/* WLAN byteswap */
815 +#define AR2315_CONFIG_WLAN 0x00000002
816 +/* MPEG-TS byteswap */
817 +#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004
818 +/* PCI byteswap */
819 +#define AR2315_CONFIG_PCI 0x00000008
820 +/* Memory controller endianess */
821 +#define AR2315_CONFIG_MEMCTL 0x00000010
822 +/* Local bus byteswap */
823 +#define AR2315_CONFIG_LOCAL 0x00000020
824 +/* Ethernet byteswap */
825 +#define AR2315_CONFIG_ETHERNET 0x00000040
826 +
827 +/* CPU write buffer merge */
828 +#define AR2315_CONFIG_MERGE 0x00000200
829 +/* CPU big endian */
830 +#define AR2315_CONFIG_CPU 0x00000400
831 +#define AR2315_CONFIG_PCIAHB 0x00000800
832 +#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
833 +/* SPI byteswap */
834 +#define AR2315_CONFIG_SPI 0x00008000
835 +#define AR2315_CONFIG_CPU_DRAM 0x00010000
836 +#define AR2315_CONFIG_CPU_PCI 0x00020000
837 +#define AR2315_CONFIG_CPU_MMR 0x00040000
838 +#define AR2315_CONFIG_BIG 0x00000400
839 +
840 +
841 +/*
842 + * NMI control
843 + */
844 +#define AR2315_NMI_CTL (AR2315_DSLBASE + 0x0010)
845 +
846 +#define AR2315_NMI_EN 1
847 +
848 +/*
849 + * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR231X 1.0).
850 + */
851 +#define AR2315_SREV (AR2315_DSLBASE + 0x0014)
852 +
853 +#define AR2315_REV_MAJ 0x00f0
854 +#define AR2315_REV_MAJ_S 4
855 +#define AR2315_REV_MIN 0x000f
856 +#define AR2315_REV_MIN_S 0
857 +#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN)
858 +
859 +/*
860 + * Interface Enable
861 + */
862 +#define AR2315_IF_CTL (AR2315_DSLBASE + 0x0018)
863 +
864 +#define AR2315_IF_MASK 0x00000007
865 +#define AR2315_IF_DISABLED 0
866 +#define AR2315_IF_PCI 1
867 +#define AR2315_IF_TS_LOCAL 2
868 +/* only for emulation with separate pins */
869 +#define AR2315_IF_ALL 3
870 +#define AR2315_IF_LOCAL_HOST 0x00000008
871 +#define AR2315_IF_PCI_HOST 0x00000010
872 +#define AR2315_IF_PCI_INTR 0x00000020
873 +#define AR2315_IF_PCI_CLK_MASK 0x00030000
874 +#define AR2315_IF_PCI_CLK_INPUT 0
875 +#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
876 +#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
877 +#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
878 +#define AR2315_IF_PCI_CLK_SHIFT 16
879 +
880 +/*
881 + * APB Interrupt control
882 + */
883 +
884 +#define AR2315_ISR (AR2315_DSLBASE + 0x0020)
885 +#define AR2315_IMR (AR2315_DSLBASE + 0x0024)
886 +#define AR2315_GISR (AR2315_DSLBASE + 0x0028)
887 +
888 +#define AR2315_ISR_UART0 0x0001 /* high speed UART */
889 +#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */
890 +#define AR2315_ISR_SPI 0x0004 /* SPI bus */
891 +#define AR2315_ISR_AHB 0x0008 /* AHB error */
892 +#define AR2315_ISR_APB 0x0010 /* APB error */
893 +#define AR2315_ISR_TIMER 0x0020 /* timer */
894 +#define AR2315_ISR_GPIO 0x0040 /* GPIO */
895 +#define AR2315_ISR_WD 0x0080 /* watchdog */
896 +#define AR2315_ISR_IR_RSVD 0x0100 /* IR */
897 +
898 +#define AR2315_GISR_MISC 0x0001
899 +#define AR2315_GISR_WLAN0 0x0002
900 +#define AR2315_GISR_MPEGTS_RSVD 0x0004
901 +#define AR2315_GISR_LOCALPCI 0x0008
902 +#define AR2315_GISR_WMACPOLL 0x0010
903 +#define AR2315_GISR_TIMER 0x0020
904 +#define AR2315_GISR_ETHERNET 0x0040
905 +
906 +/*
907 + * Interrupt routing from IO to the processor IP bits
908 + * Define our inter mask and level
909 + */
910 +#define AR2315_INTR_MISCIO SR_IBIT3
911 +#define AR2315_INTR_WLAN0 SR_IBIT4
912 +#define AR2315_INTR_ENET0 SR_IBIT5
913 +#define AR2315_INTR_LOCALPCI SR_IBIT6
914 +#define AR2315_INTR_WMACPOLL SR_IBIT7
915 +#define AR2315_INTR_COMPARE SR_IBIT8
916 +
917 +/*
918 + * Timers
919 + */
920 +#define AR2315_TIMER (AR2315_DSLBASE + 0x0030)
921 +#define AR2315_RELOAD (AR2315_DSLBASE + 0x0034)
922 +#define AR2315_WD (AR2315_DSLBASE + 0x0038)
923 +#define AR2315_WDC (AR2315_DSLBASE + 0x003c)
924 +
925 +#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000
926 +#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */
927 +#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */
928 +
929 +/*
930 + * CPU Performance Counters
931 + */
932 +#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048)
933 +#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c)
934 +
935 +#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */
936 +#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */
937 +#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */
938 +#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */
939 +#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */
940 +#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */
941 +#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */
942 +
943 +#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */
944 +#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */
945 +#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */
946 +#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */
947 +#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */
948 +#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */
949 +#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */
950 +
951 +/*
952 + * AHB Error Reporting.
953 + */
954 +#define AR2315_AHB_ERR0 (AR2315_DSLBASE + 0x0050) /* error */
955 +#define AR2315_AHB_ERR1 (AR2315_DSLBASE + 0x0054) /* haddr */
956 +#define AR2315_AHB_ERR2 (AR2315_DSLBASE + 0x0058) /* hwdata */
957 +#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */
958 +#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */
959 +
960 +#define AHB_ERROR_DET 1 /* AHB Error has been detected, */
961 + /* write 1 to clear all bits in ERR0 */
962 +#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
963 +#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
964 +
965 +#define AR2315_PROCERR_HMAST 0x0000000f
966 +#define AR2315_PROCERR_HMAST_DFLT 0
967 +#define AR2315_PROCERR_HMAST_WMAC 1
968 +#define AR2315_PROCERR_HMAST_ENET 2
969 +#define AR2315_PROCERR_HMAST_PCIENDPT 3
970 +#define AR2315_PROCERR_HMAST_LOCAL 4
971 +#define AR2315_PROCERR_HMAST_CPU 5
972 +#define AR2315_PROCERR_HMAST_PCITGT 6
973 +
974 +#define AR2315_PROCERR_HMAST_S 0
975 +#define AR2315_PROCERR_HWRITE 0x00000010
976 +#define AR2315_PROCERR_HSIZE 0x00000060
977 +#define AR2315_PROCERR_HSIZE_S 5
978 +#define AR2315_PROCERR_HTRANS 0x00000180
979 +#define AR2315_PROCERR_HTRANS_S 7
980 +#define AR2315_PROCERR_HBURST 0x00000e00
981 +#define AR2315_PROCERR_HBURST_S 9
982 +
983 +/*
984 + * Clock Control
985 + */
986 +#define AR2315_PLLC_CTL (AR2315_DSLBASE + 0x0064)
987 +#define AR2315_PLLV_CTL (AR2315_DSLBASE + 0x0068)
988 +#define AR2315_CPUCLK (AR2315_DSLBASE + 0x006c)
989 +#define AR2315_AMBACLK (AR2315_DSLBASE + 0x0070)
990 +#define AR2315_SYNCCLK (AR2315_DSLBASE + 0x0074)
991 +#define AR2315_DSL_SLEEP_CTL (AR2315_DSLBASE + 0x0080)
992 +#define AR2315_DSL_SLEEP_DUR (AR2315_DSLBASE + 0x0084)
993 +
994 +/* PLLc Control fields */
995 +#define PLLC_REF_DIV_M 0x00000003
996 +#define PLLC_REF_DIV_S 0
997 +#define PLLC_FDBACK_DIV_M 0x0000007C
998 +#define PLLC_FDBACK_DIV_S 2
999 +#define PLLC_ADD_FDBACK_DIV_M 0x00000080
1000 +#define PLLC_ADD_FDBACK_DIV_S 7
1001 +#define PLLC_CLKC_DIV_M 0x0001c000
1002 +#define PLLC_CLKC_DIV_S 14
1003 +#define PLLC_CLKM_DIV_M 0x00700000
1004 +#define PLLC_CLKM_DIV_S 20
1005 +
1006 +/* CPU CLK Control fields */
1007 +#define CPUCLK_CLK_SEL_M 0x00000003
1008 +#define CPUCLK_CLK_SEL_S 0
1009 +#define CPUCLK_CLK_DIV_M 0x0000000c
1010 +#define CPUCLK_CLK_DIV_S 2
1011 +
1012 +/* AMBA CLK Control fields */
1013 +#define AMBACLK_CLK_SEL_M 0x00000003
1014 +#define AMBACLK_CLK_SEL_S 0
1015 +#define AMBACLK_CLK_DIV_M 0x0000000c
1016 +#define AMBACLK_CLK_DIV_S 2
1017 +
1018 +/*
1019 + * GPIO
1020 + */
1021 +#define AR2315_GPIO_DI (AR2315_DSLBASE + 0x0088)
1022 +#define AR2315_GPIO_DO (AR2315_DSLBASE + 0x0090)
1023 +#define AR2315_GPIO_DIR (AR2315_DSLBASE + 0x0098)
1024 +#define AR2315_GPIO_INT (AR2315_DSLBASE + 0x00a0)
1025 +
1026 +#define AR2315_GPIO_DIR_M(x) (1 << (x)) /* mask for i/o */
1027 +#define AR2315_GPIO_DIR_O(x) (1 << (x)) /* output */
1028 +#define AR2315_GPIO_DIR_I(x) (0) /* input */
1029 +
1030 +#define AR2315_GPIO_INT_S(x) (x) /* interrupt enable */
1031 +#define AR2315_GPIO_INT_M (0x3F) /* mask for int */
1032 +#define AR2315_GPIO_INT_LVL(x) ((x) << 6) /* interrupt level */
1033 +#define AR2315_GPIO_INT_LVL_M ((0x3) << 6) /* mask for int level */
1034 +
1035 +#define AR2315_GPIO_INT_MAX_Y 1 /* Maximum value of Y for
1036 + * AR2315_GPIO_INT_* macros */
1037 +#define AR2315_GPIO_INT_LVL_OFF 0 /* Triggerring off */
1038 +#define AR2315_GPIO_INT_LVL_LOW 1 /* Low Level Triggered */
1039 +#define AR2315_GPIO_INT_LVL_HIGH 2 /* High Level Triggered */
1040 +#define AR2315_GPIO_INT_LVL_EDGE 3 /* Edge Triggered */
1041 +
1042 +#define AR2315_RESET_GPIO 5
1043 +#define AR2315_NUM_GPIO 22
1044 +
1045 +/*
1046 + * PCI Clock Control
1047 + */
1048 +#define AR2315_PCICLK (AR2315_DSLBASE + 0x00a4)
1049 +
1050 +#define AR2315_PCICLK_INPUT_M 0x3
1051 +#define AR2315_PCICLK_INPUT_S 0
1052 +
1053 +#define AR2315_PCICLK_PLLC_CLKM 0
1054 +#define AR2315_PCICLK_PLLC_CLKM1 1
1055 +#define AR2315_PCICLK_PLLC_CLKC 2
1056 +#define AR2315_PCICLK_REF_CLK 3
1057 +
1058 +#define AR2315_PCICLK_DIV_M 0xc
1059 +#define AR2315_PCICLK_DIV_S 2
1060 +
1061 +#define AR2315_PCICLK_IN_FREQ 0
1062 +#define AR2315_PCICLK_IN_FREQ_DIV_6 1
1063 +#define AR2315_PCICLK_IN_FREQ_DIV_8 2
1064 +#define AR2315_PCICLK_IN_FREQ_DIV_10 3
1065 +
1066 +/*
1067 + * Observation Control Register
1068 + */
1069 +#define AR2315_OCR (AR2315_DSLBASE + 0x00b0)
1070 +#define OCR_GPIO0_IRIN 0x0040
1071 +#define OCR_GPIO1_IROUT 0x0080
1072 +#define OCR_GPIO3_RXCLR 0x0200
1073 +
1074 +/*
1075 + * General Clock Control
1076 + */
1077 +
1078 +#define AR2315_MISCCLK (AR2315_DSLBASE + 0x00b4)
1079 +#define MISCCLK_PLLBYPASS_EN 0x00000001
1080 +#define MISCCLK_PROCREFCLK 0x00000002
1081 +
1082 +/*
1083 + * SDRAM Controller
1084 + * - No read or write buffers are included.
1085 + */
1086 +#define AR2315_MEM_CFG (AR2315_SDRAMCTL + 0x00)
1087 +#define AR2315_MEM_CTRL (AR2315_SDRAMCTL + 0x0c)
1088 +#define AR2315_MEM_REF (AR2315_SDRAMCTL + 0x10)
1089 +
1090 +#define SDRAM_DATA_WIDTH_M 0x00006000
1091 +#define SDRAM_DATA_WIDTH_S 13
1092 +
1093 +#define SDRAM_COL_WIDTH_M 0x00001E00
1094 +#define SDRAM_COL_WIDTH_S 9
1095 +
1096 +#define SDRAM_ROW_WIDTH_M 0x000001E0
1097 +#define SDRAM_ROW_WIDTH_S 5
1098 +
1099 +#define SDRAM_BANKADDR_BITS_M 0x00000018
1100 +#define SDRAM_BANKADDR_BITS_S 3
1101 +
1102 +/*
1103 + * PCI Bus Interface Registers
1104 + */
1105 +#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008)
1106 +#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1107 +
1108 +#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c)
1109 +#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
1110 +#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* mem or config cycles */
1111 +#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
1112 +#define AR2315_PCIMISC_RST_MODE 0x00000030
1113 +#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
1114 +#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
1115 +#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
1116 +#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
1117 +#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
1118 +#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
1119 +#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
1120 +#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache
1121 + * disable */
1122 +
1123 +#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010)
1124 +
1125 +#define AR2315_PCI_UNCACHE_CFG (AR2315_PCI + 0x0014)
1126 +
1127 +#define AR2315_PCI_IN_EN (AR2315_PCI + 0x0100)
1128 +#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
1129 +#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
1130 +#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
1131 +#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
1132 +
1133 +#define AR2315_PCI_IN_DIS (AR2315_PCI + 0x0104)
1134 +#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
1135 +#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
1136 +#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
1137 +#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
1138 +
1139 +#define AR2315_PCI_IN_PTR (AR2315_PCI + 0x0200)
1140 +
1141 +#define AR2315_PCI_OUT_EN (AR2315_PCI + 0x0400)
1142 +#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
1143 +
1144 +#define AR2315_PCI_OUT_DIS (AR2315_PCI + 0x0404)
1145 +#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
1146 +
1147 +#define AR2315_PCI_OUT_PTR (AR2315_PCI + 0x0408)
1148 +
1149 +#define AR2315_PCI_INT_STATUS (AR2315_PCI + 0x0500) /* write one to clr */
1150 +#define AR2315_PCI_TXINT 0x00000001 /* Desc In Completed */
1151 +#define AR2315_PCI_TXOK 0x00000002 /* Desc In OK */
1152 +#define AR2315_PCI_TXERR 0x00000004 /* Desc In ERR */
1153 +#define AR2315_PCI_TXEOL 0x00000008 /* Desc In End-of-List */
1154 +#define AR2315_PCI_RXINT 0x00000010 /* Desc Out Completed */
1155 +#define AR2315_PCI_RXOK 0x00000020 /* Desc Out OK */
1156 +#define AR2315_PCI_RXERR 0x00000040 /* Desc Out ERR */
1157 +#define AR2315_PCI_RXEOL 0x00000080 /* Desc Out EOL */
1158 +#define AR2315_PCI_TXOOD 0x00000200 /* Desc In Out-of-Desc */
1159 +#define AR2315_PCI_MASK 0x0000FFFF /* Desc Mask */
1160 +#define AR2315_PCI_EXT_INT 0x02000000
1161 +#define AR2315_PCI_ABORT_INT 0x04000000
1162 +
1163 +#define AR2315_PCI_INT_MASK (AR2315_PCI + 0x0504) /* same as INT_STATUS */
1164 +
1165 +#define AR2315_PCI_INTEN_REG (AR2315_PCI + 0x0508)
1166 +#define AR2315_PCI_INT_DISABLE 0x00 /* disable pci interrupts */
1167 +#define AR2315_PCI_INT_ENABLE 0x01 /* enable pci interrupts */
1168 +
1169 +#define AR2315_PCI_HOST_IN_EN (AR2315_PCI + 0x0800)
1170 +#define AR2315_PCI_HOST_IN_DIS (AR2315_PCI + 0x0804)
1171 +#define AR2315_PCI_HOST_IN_PTR (AR2315_PCI + 0x0810)
1172 +#define AR2315_PCI_HOST_OUT_EN (AR2315_PCI + 0x0900)
1173 +#define AR2315_PCI_HOST_OUT_DIS (AR2315_PCI + 0x0904)
1174 +#define AR2315_PCI_HOST_OUT_PTR (AR2315_PCI + 0x0908)
1175 +
1176 +
1177 +/*
1178 + * Local Bus Interface Registers
1179 + */
1180 +#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000)
1181 +#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
1182 +#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
1183 +#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
1184 +#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
1185 +#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
1186 +#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
1187 +#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
1188 +#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
1189 +#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
1190 +#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
1191 +#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
1192 +#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
1193 +#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
1194 +#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
1195 +#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
1196 +#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
1197 +#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
1198 +#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
1199 +#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
1200 +#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
1201 +#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
1202 +#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */
1203 +#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
1204 +#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
1205 +#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
1206 +
1207 +#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004)
1208 +#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */
1209 +
1210 +#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008)
1211 +#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1212 +
1213 +#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C)
1214 +#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
1215 +#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
1216 +#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
1217 +#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
1218 +#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
1219 +#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80
1220 +#define AR2315_LBM_TIMEOUT_SHFT 7
1221 +#define AR2315_LBM_PORTMUX 0x07000000
1222 +
1223 +
1224 +#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010)
1225 +
1226 +#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100)
1227 +#define AR2315_LB_TXEN_0 0x01
1228 +#define AR2315_LB_TXEN_1 0x02
1229 +#define AR2315_LB_TXEN_2 0x04
1230 +#define AR2315_LB_TXEN_3 0x08
1231 +
1232 +#define AR2315_LB_TX_CHAIN_DIS (AR2315_LOCAL + 0x0104)
1233 +#define AR2315_LB_TX_DESC_PTR (AR2315_LOCAL + 0x0200)
1234 +
1235 +#define AR2315_LB_RX_CHAIN_EN (AR2315_LOCAL + 0x0400)
1236 +#define AR2315_LB_RXEN 0x01
1237 +
1238 +#define AR2315_LB_RX_CHAIN_DIS (AR2315_LOCAL + 0x0404)
1239 +#define AR2315_LB_RX_DESC_PTR (AR2315_LOCAL + 0x0408)
1240 +
1241 +#define AR2315_LB_INT_STATUS (AR2315_LOCAL + 0x0500)
1242 +#define AR2315_INT_TX_DESC 0x0001
1243 +#define AR2315_INT_TX_OK 0x0002
1244 +#define AR2315_INT_TX_ERR 0x0004
1245 +#define AR2315_INT_TX_EOF 0x0008
1246 +#define AR2315_INT_RX_DESC 0x0010
1247 +#define AR2315_INT_RX_OK 0x0020
1248 +#define AR2315_INT_RX_ERR 0x0040
1249 +#define AR2315_INT_RX_EOF 0x0080
1250 +#define AR2315_INT_TX_TRUNC 0x0100
1251 +#define AR2315_INT_TX_STARVE 0x0200
1252 +#define AR2315_INT_LB_TIMEOUT 0x0400
1253 +#define AR2315_INT_LB_ERR 0x0800
1254 +#define AR2315_INT_MBOX_WR 0x1000
1255 +#define AR2315_INT_MBOX_RD 0x2000
1256 +
1257 +/* Bit definitions for INT MASK are the same as INT_STATUS */
1258 +#define AR2315_LB_INT_MASK (AR2315_LOCAL + 0x0504)
1259 +
1260 +#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508)
1261 +#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600)
1262 +
1263 +/*
1264 + * IR Interface Registers
1265 + */
1266 +#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000)
1267 +
1268 +#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */
1269 +
1270 +#define AR2315_IR_CONTROL (AR2315_IR + 0x0800)
1271 +#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */
1272 +#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */
1273 +#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor */
1274 +#define AR2315_IRCTL_SAMPLECLK_SHFT 1
1275 +#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk div */
1276 +#define AR2315_IRCTL_OUTPUTCLK_SHFT 14
1277 +
1278 +#define AR2315_IR_STATUS (AR2315_IR + 0x0804)
1279 +#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */
1280 +#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */
1281 +
1282 +#define AR2315_IR_CONFIG (AR2315_IR + 0x0808)
1283 +#define AR2315_IRCFG_INVIN 0x00000001 /* invert in polarity */
1284 +#define AR2315_IRCFG_INVOUT 0x00000002 /* invert out polarity */
1285 +#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */
1286 +#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0
1287 +#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100
1288 +#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00
1289 +#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000
1290 +#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000
1291 +#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000
1292 +
1293 +#define HOST_PCI_DEV_ID 3
1294 +#define HOST_PCI_MBAR0 0x10000000
1295 +#define HOST_PCI_MBAR1 0x20000000
1296 +#define HOST_PCI_MBAR2 0x30000000
1297 +
1298 +#define HOST_PCI_SDRAM_BASEADDR HOST_PCI_MBAR1
1299 +#define PCI_DEVICE_MEM_SPACE 0x800000
1300 +
1301 +#endif /* __ASM_MACH_AR231X_AR2315_REGS_H */
1302 --- /dev/null
1303 +++ b/arch/mips/include/asm/mach-ar231x/ar5312_regs.h
1304 @@ -0,0 +1,253 @@
1305 +/*
1306 + * This file is subject to the terms and conditions of the GNU General Public
1307 + * License. See the file "COPYING" in the main directory of this archive
1308 + * for more details.
1309 + *
1310 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1311 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1312 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1313 + */
1314 +
1315 +#ifndef __ASM_MACH_AR231X_AR5312_REGS_H
1316 +#define __ASM_MACH_AR231X_AR5312_REGS_H
1317 +
1318 +#include <asm/addrspace.h>
1319 +
1320 +/*
1321 + * IRQs
1322 + */
1323 +
1324 +#define AR5312_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
1325 +#define AR5312_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
1326 +#define AR5312_IRQ_ENET1_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
1327 +#define AR5312_IRQ_WLAN1_INTRS (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
1328 +#define AR5312_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
1329 +
1330 +
1331 +/*
1332 + * Miscellaneous interrupts, which share IP6.
1333 + */
1334 +#define AR5312_MISC_IRQ_NONE (AR231X_MISC_IRQ_BASE+0)
1335 +#define AR5312_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+1)
1336 +#define AR5312_MISC_IRQ_AHB_PROC (AR231X_MISC_IRQ_BASE+2)
1337 +#define AR5312_MISC_IRQ_AHB_DMA (AR231X_MISC_IRQ_BASE+3)
1338 +#define AR5312_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+4)
1339 +#define AR5312_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+5)
1340 +#define AR5312_MISC_IRQ_UART0_DMA (AR231X_MISC_IRQ_BASE+6)
1341 +#define AR5312_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+7)
1342 +#define AR5312_MISC_IRQ_LOCAL (AR231X_MISC_IRQ_BASE+8)
1343 +#define AR5312_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+9)
1344 +#define AR5312_MISC_IRQ_COUNT 10
1345 +
1346 +
1347 +/* Address Map */
1348 +#define AR5312_WLAN0 0x18000000
1349 +#define AR5312_WLAN1 0x18500000
1350 +#define AR5312_ENET0 0x18100000
1351 +#define AR5312_ENET1 0x18200000
1352 +#define AR5312_SDRAMCTL 0x18300000
1353 +#define AR5312_FLASHCTL 0x18400000
1354 +#define AR5312_APBBASE 0x1c000000
1355 +#define AR5312_UART0 0x1c000000 /* UART MMR */
1356 +#define AR5312_FLASH 0x1e000000
1357 +
1358 +/*
1359 + * AR5312_NUM_ENET_MAC defines the number of ethernet MACs that
1360 + * should be considered available. The AR5312 supports 2 enet MACS,
1361 + * even though many reference boards only actually use 1 of them
1362 + * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch.
1363 + * The AR2312 supports 1 enet MAC.
1364 + */
1365 +#define AR5312_NUM_ENET_MAC 2
1366 +
1367 +/*
1368 + * Need these defines to determine true number of ethernet MACs
1369 + */
1370 +#define AR5312_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
1371 +#define AR5312_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
1372 +#define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
1373 +
1374 +/* MII registers offset inside Ethernet MMR region */
1375 +#define AR5312_ENET0_MII (AR5312_ENET0 + 0x14)
1376 +#define AR5312_ENET1_MII (AR5312_ENET1 + 0x14)
1377 +
1378 +/*
1379 + * AR5312_NUM_WMAC defines the number of Wireless MACs that\
1380 + * should be considered available.
1381 + */
1382 +#define AR5312_NUM_WMAC 2
1383 +
1384 +/* Reset/Timer Block Address Map */
1385 +#define AR5312_RESETTMR (AR5312_APBBASE + 0x3000)
1386 +#define AR5312_TIMER (AR5312_RESETTMR + 0x0000) /* countdown timer */
1387 +#define AR5312_WD_CTRL (AR5312_RESETTMR + 0x0008) /* watchdog cntrl */
1388 +#define AR5312_WD_TIMER (AR5312_RESETTMR + 0x000c) /* watchdog timer */
1389 +#define AR5312_ISR (AR5312_RESETTMR + 0x0010) /* Intr Status Reg */
1390 +#define AR5312_IMR (AR5312_RESETTMR + 0x0014) /* Intr Mask Reg */
1391 +#define AR5312_RESET (AR5312_RESETTMR + 0x0020)
1392 +#define AR5312_CLOCKCTL1 (AR5312_RESETTMR + 0x0064)
1393 +#define AR5312_SCRATCH (AR5312_RESETTMR + 0x006c)
1394 +#define AR5312_PROCADDR (AR5312_RESETTMR + 0x0070)
1395 +#define AR5312_PROC1 (AR5312_RESETTMR + 0x0074)
1396 +#define AR5312_DMAADDR (AR5312_RESETTMR + 0x0078)
1397 +#define AR5312_DMA1 (AR5312_RESETTMR + 0x007c)
1398 +#define AR5312_ENABLE (AR5312_RESETTMR + 0x0080) /* interface enb */
1399 +#define AR5312_REV (AR5312_RESETTMR + 0x0090) /* revision */
1400 +
1401 +/* AR5312_WD_CTRL register bit field definitions */
1402 +#define AR5312_WD_CTRL_IGNORE_EXPIRATION 0x0000
1403 +#define AR5312_WD_CTRL_NMI 0x0001
1404 +#define AR5312_WD_CTRL_RESET 0x0002
1405 +
1406 +/* AR5312_ISR register bit field definitions */
1407 +#define AR5312_ISR_NONE 0x0000
1408 +#define AR5312_ISR_TIMER 0x0001
1409 +#define AR5312_ISR_AHBPROC 0x0002
1410 +#define AR5312_ISR_AHBDMA 0x0004
1411 +#define AR5312_ISR_GPIO 0x0008
1412 +#define AR5312_ISR_UART0 0x0010
1413 +#define AR5312_ISR_UART0DMA 0x0020
1414 +#define AR5312_ISR_WD 0x0040
1415 +#define AR5312_ISR_LOCAL 0x0080
1416 +
1417 +/* AR5312_RESET register bit field definitions */
1418 +#define AR5312_RESET_SYSTEM 0x00000001 /* cold reset full system */
1419 +#define AR5312_RESET_PROC 0x00000002 /* cold reset MIPS core */
1420 +#define AR5312_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
1421 +#define AR5312_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
1422 +#define AR5312_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
1423 +#define AR5312_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
1424 +#define AR5312_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
1425 +#define AR5312_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */
1426 +#define AR5312_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
1427 +#define AR5312_RESET_APB 0x00000400 /* cold reset APB (ar5312) */
1428 +#define AR5312_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
1429 +#define AR5312_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
1430 +#define AR5312_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */
1431 +#define AR5312_RESET_NMI 0x00010000 /* send an NMI to the processor */
1432 +#define AR5312_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */
1433 +#define AR5312_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */
1434 +#define AR5312_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
1435 +#define AR5312_RESET_WDOG 0x00100000 /* last reset was a watchdog */
1436 +
1437 +#define AR5312_RESET_WMAC0_BITS \
1438 + (AR5312_RESET_WLAN0 |\
1439 + AR5312_RESET_WARM_WLAN0_MAC |\
1440 + AR5312_RESET_WARM_WLAN0_BB)
1441 +
1442 +#define AR5312_RESET_WMAC1_BITS \
1443 + (AR5312_RESET_WLAN1 |\
1444 + AR5312_RESET_WARM_WLAN1_MAC |\
1445 + AR5312_RESET_WARM_WLAN1_BB)
1446 +
1447 +/* AR5312_CLOCKCTL1 register bit field definitions */
1448 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1449 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1450 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1451 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1452 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1453 +
1454 +/* Valid for AR5312 and AR2312 */
1455 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1456 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1457 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1458 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1459 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1460 +
1461 +/* Valid for AR2313 */
1462 +#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
1463 +#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
1464 +#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
1465 +#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
1466 +#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
1467 +
1468 +
1469 +/* AR5312_ENABLE register bit field definitions */
1470 +#define AR5312_ENABLE_WLAN0 0x0001
1471 +#define AR5312_ENABLE_ENET0 0x0002
1472 +#define AR5312_ENABLE_ENET1 0x0004
1473 +#define AR5312_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */
1474 +#define AR5312_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */
1475 +#define AR5312_ENABLE_WLAN1 \
1476 + (AR5312_ENABLE_UART_AND_WLAN1_PIO |\
1477 + AR5312_ENABLE_WLAN1_DMA)
1478 +
1479 +/* AR5312_REV register bit field definitions */
1480 +#define AR5312_REV_WMAC_MAJ 0xf000
1481 +#define AR5312_REV_WMAC_MAJ_S 12
1482 +#define AR5312_REV_WMAC_MIN 0x0f00
1483 +#define AR5312_REV_WMAC_MIN_S 8
1484 +#define AR5312_REV_MAJ 0x00f0
1485 +#define AR5312_REV_MAJ_S 4
1486 +#define AR5312_REV_MIN 0x000f
1487 +#define AR5312_REV_MIN_S 0
1488 +#define AR5312_REV_CHIP (AR5312_REV_MAJ|AR5312_REV_MIN)
1489 +
1490 +/* Major revision numbers, bits 7..4 of Revision ID register */
1491 +#define AR5312_REV_MAJ_AR5312 0x4
1492 +#define AR5312_REV_MAJ_AR2313 0x5
1493 +
1494 +/* Minor revision numbers, bits 3..0 of Revision ID register */
1495 +#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
1496 +#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
1497 +
1498 +/* AR5312_FLASHCTL register bit field definitions */
1499 +#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */
1500 +#define FLASHCTL_IDCY_S 0
1501 +#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
1502 +#define FLASHCTL_WST1_S 5
1503 +#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
1504 +#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
1505 +#define FLASHCTL_WST2_S 11
1506 +#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */
1507 +#define FLASHCTL_AC_S 16
1508 +#define FLASHCTL_AC_128K 0x00000000
1509 +#define FLASHCTL_AC_256K 0x00010000
1510 +#define FLASHCTL_AC_512K 0x00020000
1511 +#define FLASHCTL_AC_1M 0x00030000
1512 +#define FLASHCTL_AC_2M 0x00040000
1513 +#define FLASHCTL_AC_4M 0x00050000
1514 +#define FLASHCTL_AC_8M 0x00060000
1515 +#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
1516 +#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
1517 +#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */
1518 +#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */
1519 +#define FLASHCTL_WP 0x04000000 /* Write protect */
1520 +#define FLASHCTL_BM 0x08000000 /* Burst mode */
1521 +#define FLASHCTL_MW 0x30000000 /* Memory width */
1522 +#define FLASHCTL_MW8 0x00000000 /* Memory width x8 */
1523 +#define FLASHCTL_MW16 0x10000000 /* Memory width x16 */
1524 +#define FLASHCTL_MW32 0x20000000 /* Memory width x32 (not supported) */
1525 +#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */
1526 +#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */
1527 +#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */
1528 +
1529 +/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
1530 +#define AR5312_FLASHCTL0 (AR5312_FLASHCTL + 0x00)
1531 +#define AR5312_FLASHCTL1 (AR5312_FLASHCTL + 0x04)
1532 +#define AR5312_FLASHCTL2 (AR5312_FLASHCTL + 0x08)
1533 +
1534 +/* ARM SDRAM Controller -- just enough to determine memory size */
1535 +#define AR5312_MEM_CFG1 (AR5312_SDRAMCTL + 0x04)
1536 +#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */
1537 +#define MEM_CFG1_AC0_S 8
1538 +#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */
1539 +#define MEM_CFG1_AC1_S 12
1540 +
1541 +/* GPIO Address Map */
1542 +#define AR5312_GPIO (AR5312_APBBASE + 0x2000)
1543 +#define AR5312_GPIO_DO (AR5312_GPIO + 0x00) /* output register */
1544 +#define AR5312_GPIO_DI (AR5312_GPIO + 0x04) /* intput register */
1545 +#define AR5312_GPIO_CR (AR5312_GPIO + 0x08) /* control register */
1546 +
1547 +/* GPIO Control Register bit field definitions */
1548 +#define AR5312_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
1549 +#define AR5312_GPIO_CR_O(x) (0 << (x)) /* mask for output */
1550 +#define AR5312_GPIO_CR_I(x) (1 << (x)) /* mask for input */
1551 +#define AR5312_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt*/
1552 +#define AR5312_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */
1553 +#define AR5312_NUM_GPIO 8
1554 +
1555 +
1556 +#endif /* __ASM_MACH_AR231X_AR5312_REGS_H */
1557 +
1558 --- /dev/null
1559 +++ b/arch/mips/ar231x/ar5312.c
1560 @@ -0,0 +1,541 @@
1561 +/*
1562 + * This file is subject to the terms and conditions of the GNU General Public
1563 + * License. See the file "COPYING" in the main directory of this archive
1564 + * for more details.
1565 + *
1566 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1567 + * Copyright (C) 2006 FON Technology, SL.
1568 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1569 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1570 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1571 + */
1572 +
1573 +/*
1574 + * Platform devices for Atheros SoCs
1575 + */
1576 +
1577 +#include <generated/autoconf.h>
1578 +#include <linux/init.h>
1579 +#include <linux/module.h>
1580 +#include <linux/types.h>
1581 +#include <linux/string.h>
1582 +#include <linux/mtd/physmap.h>
1583 +#include <linux/platform_device.h>
1584 +#include <linux/kernel.h>
1585 +#include <linux/reboot.h>
1586 +#include <linux/leds.h>
1587 +#include <linux/gpio.h>
1588 +#include <asm/bootinfo.h>
1589 +#include <asm/reboot.h>
1590 +#include <asm/time.h>
1591 +#include <linux/irq.h>
1592 +#include <linux/io.h>
1593 +
1594 +#include <ar231x_platform.h>
1595 +#include <ar5312_regs.h>
1596 +#include <ar231x.h>
1597 +#include "devices.h"
1598 +#include "ar5312.h"
1599 +
1600 +static void ar5312_misc_irq_handler(unsigned irq, struct irq_desc *desc)
1601 +{
1602 + unsigned int ar231x_misc_intrs = ar231x_read_reg(AR5312_ISR) &
1603 + ar231x_read_reg(AR5312_IMR);
1604 +
1605 + if (ar231x_misc_intrs & AR5312_ISR_TIMER) {
1606 + do_IRQ(AR5312_MISC_IRQ_TIMER);
1607 + (void)ar231x_read_reg(AR5312_TIMER);
1608 + } else if (ar231x_misc_intrs & AR5312_ISR_AHBPROC)
1609 + do_IRQ(AR5312_MISC_IRQ_AHB_PROC);
1610 + else if ((ar231x_misc_intrs & AR5312_ISR_UART0))
1611 + do_IRQ(AR5312_MISC_IRQ_UART0);
1612 + else if (ar231x_misc_intrs & AR5312_ISR_WD)
1613 + do_IRQ(AR5312_MISC_IRQ_WATCHDOG);
1614 + else
1615 + do_IRQ(AR5312_MISC_IRQ_NONE);
1616 +}
1617 +
1618 +static asmlinkage void
1619 +ar5312_irq_dispatch(void)
1620 +{
1621 + int pending = read_c0_status() & read_c0_cause();
1622 +
1623 + if (pending & CAUSEF_IP2)
1624 + do_IRQ(AR5312_IRQ_WLAN0_INTRS);
1625 + else if (pending & CAUSEF_IP3)
1626 + do_IRQ(AR5312_IRQ_ENET0_INTRS);
1627 + else if (pending & CAUSEF_IP4)
1628 + do_IRQ(AR5312_IRQ_ENET1_INTRS);
1629 + else if (pending & CAUSEF_IP5)
1630 + do_IRQ(AR5312_IRQ_WLAN1_INTRS);
1631 + else if (pending & CAUSEF_IP6)
1632 + do_IRQ(AR5312_IRQ_MISC_INTRS);
1633 + else if (pending & CAUSEF_IP7)
1634 + do_IRQ(AR231X_IRQ_CPU_CLOCK);
1635 +}
1636 +
1637 +
1638 +/* Enable the specified AR5312_MISC_IRQ interrupt */
1639 +static void
1640 +ar5312_misc_irq_unmask(struct irq_data *d)
1641 +{
1642 + unsigned int imr;
1643 +
1644 + imr = ar231x_read_reg(AR5312_IMR);
1645 + imr |= (1 << (d->irq - AR231X_MISC_IRQ_BASE - 1));
1646 + ar231x_write_reg(AR5312_IMR, imr);
1647 +}
1648 +
1649 +/* Disable the specified AR5312_MISC_IRQ interrupt */
1650 +static void
1651 +ar5312_misc_irq_mask(struct irq_data *d)
1652 +{
1653 + unsigned int imr;
1654 +
1655 + imr = ar231x_read_reg(AR5312_IMR);
1656 + imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE - 1));
1657 + ar231x_write_reg(AR5312_IMR, imr);
1658 + ar231x_read_reg(AR5312_IMR); /* flush write buffer */
1659 +}
1660 +
1661 +static struct irq_chip ar5312_misc_irq_chip = {
1662 + .name = "AR5312-MISC",
1663 + .irq_unmask = ar5312_misc_irq_unmask,
1664 + .irq_mask = ar5312_misc_irq_mask,
1665 +};
1666 +
1667 +
1668 +static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id)
1669 +{
1670 + u32 proc1 = ar231x_read_reg(AR5312_PROC1);
1671 + u32 proc_addr = ar231x_read_reg(AR5312_PROCADDR); /* clears error */
1672 + u32 dma1 = ar231x_read_reg(AR5312_DMA1);
1673 + u32 dma_addr = ar231x_read_reg(AR5312_DMAADDR); /* clears error */
1674 +
1675 + pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
1676 + proc_addr, proc1, dma_addr, dma1);
1677 +
1678 + machine_restart("AHB error"); /* Catastrophic failure */
1679 + return IRQ_HANDLED;
1680 +}
1681 +
1682 +
1683 +static struct irqaction ar5312_ahb_proc_interrupt = {
1684 + .handler = ar5312_ahb_proc_handler,
1685 + .name = "ar5312_ahb_proc_interrupt",
1686 +};
1687 +
1688 +
1689 +void __init ar5312_irq_init(void)
1690 +{
1691 + int i;
1692 +
1693 + if (!is_5312())
1694 + return;
1695 +
1696 + ar231x_irq_dispatch = ar5312_irq_dispatch;
1697 + for (i = 0; i < AR5312_MISC_IRQ_COUNT; i++) {
1698 + int irq = AR231X_MISC_IRQ_BASE + i;
1699 +
1700 + irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip,
1701 + handle_level_irq);
1702 + }
1703 + setup_irq(AR5312_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt);
1704 + irq_set_chained_handler(AR5312_IRQ_MISC_INTRS, ar5312_misc_irq_handler);
1705 +}
1706 +
1707 +/*
1708 + * gpiolib implementations
1709 + */
1710 +static int
1711 +ar5312_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
1712 +{
1713 + return (ar231x_read_reg(AR5312_GPIO_DI) >> gpio) & 1;
1714 +}
1715 +
1716 +static void
1717 +ar5312_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
1718 +{
1719 + u32 reg = ar231x_read_reg(AR5312_GPIO_DO);
1720 +
1721 + reg = value ? reg | (1 << gpio) : reg & ~(1 << gpio);
1722 + ar231x_write_reg(AR5312_GPIO_DO, reg);
1723 +}
1724 +
1725 +static int
1726 +ar5312_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
1727 +{
1728 + ar231x_mask_reg(AR5312_GPIO_CR, 0, 1 << gpio);
1729 + return 0;
1730 +}
1731 +
1732 +static int
1733 +ar5312_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
1734 +{
1735 + ar231x_mask_reg(AR5312_GPIO_CR, 1 << gpio, 0);
1736 + ar5312_gpio_set_value(chip, gpio, value);
1737 + return 0;
1738 +}
1739 +
1740 +static struct gpio_chip ar5312_gpio_chip = {
1741 + .label = "ar5312-gpio",
1742 + .direction_input = ar5312_gpio_direction_input,
1743 + .direction_output = ar5312_gpio_direction_output,
1744 + .set = ar5312_gpio_set_value,
1745 + .get = ar5312_gpio_get_value,
1746 + .base = 0,
1747 + .ngpio = AR5312_NUM_GPIO, /* 8 */
1748 +};
1749 +
1750 +/* end of gpiolib */
1751 +
1752 +static void ar5312_device_reset_set(u32 mask)
1753 +{
1754 + u32 val;
1755 +
1756 + val = ar231x_read_reg(AR5312_RESET);
1757 + ar231x_write_reg(AR5312_RESET, val | mask);
1758 +}
1759 +
1760 +static void ar5312_device_reset_clear(u32 mask)
1761 +{
1762 + u32 val;
1763 +
1764 + val = ar231x_read_reg(AR5312_RESET);
1765 + ar231x_write_reg(AR5312_RESET, val & ~mask);
1766 +}
1767 +
1768 +static struct physmap_flash_data ar5312_flash_data = {
1769 + .width = 2,
1770 +};
1771 +
1772 +static struct resource ar5312_flash_resource = {
1773 + .start = AR5312_FLASH,
1774 + .end = AR5312_FLASH + 0x800000 - 1,
1775 + .flags = IORESOURCE_MEM,
1776 +};
1777 +
1778 +static struct ar231x_eth ar5312_eth0_data = {
1779 + .reset_set = ar5312_device_reset_set,
1780 + .reset_clear = ar5312_device_reset_clear,
1781 + .reset_mac = AR5312_RESET_ENET0,
1782 + .reset_phy = AR5312_RESET_EPHY0,
1783 + .config = &ar231x_board,
1784 +};
1785 +
1786 +static struct ar231x_eth ar5312_eth1_data = {
1787 + .reset_set = ar5312_device_reset_set,
1788 + .reset_clear = ar5312_device_reset_clear,
1789 + .reset_mac = AR5312_RESET_ENET1,
1790 + .reset_phy = AR5312_RESET_EPHY1,
1791 + .config = &ar231x_board,
1792 +};
1793 +
1794 +static struct platform_device ar5312_physmap_flash = {
1795 + .name = "physmap-flash",
1796 + .id = 0,
1797 + .dev.platform_data = &ar5312_flash_data,
1798 + .resource = &ar5312_flash_resource,
1799 + .num_resources = 1,
1800 +};
1801 +
1802 +#ifdef CONFIG_LEDS_GPIO
1803 +static struct gpio_led ar5312_leds[] = {
1804 + { .name = "wlan", .gpio = 0, .active_low = 1, },
1805 +};
1806 +
1807 +static const struct gpio_led_platform_data ar5312_led_data = {
1808 + .num_leds = ARRAY_SIZE(ar5312_leds),
1809 + .leds = (void *)ar5312_leds,
1810 +};
1811 +
1812 +static struct platform_device ar5312_gpio_leds = {
1813 + .name = "leds-gpio",
1814 + .id = -1,
1815 + .dev.platform_data = (void *)&ar5312_led_data,
1816 +};
1817 +#endif
1818 +
1819 +/*
1820 + * NB: This mapping size is larger than the actual flash size,
1821 + * but this shouldn't be a problem here, because the flash
1822 + * will simply be mapped multiple times.
1823 + */
1824 +static char __init *ar5312_flash_limit(void)
1825 +{
1826 + u32 ctl;
1827 + /*
1828 + * Configure flash bank 0.
1829 + * Assume 8M window size. Flash will be aliased if it's smaller
1830 + */
1831 + ctl = FLASHCTL_E |
1832 + FLASHCTL_AC_8M |
1833 + FLASHCTL_RBLE |
1834 + (0x01 << FLASHCTL_IDCY_S) |
1835 + (0x07 << FLASHCTL_WST1_S) |
1836 + (0x07 << FLASHCTL_WST2_S) |
1837 + (ar231x_read_reg(AR5312_FLASHCTL0) & FLASHCTL_MW);
1838 +
1839 + ar231x_write_reg(AR5312_FLASHCTL0, ctl);
1840 +
1841 + /* Disable other flash banks */
1842 + ar231x_write_reg(AR5312_FLASHCTL1,
1843 + ar231x_read_reg(AR5312_FLASHCTL1) &
1844 + ~(FLASHCTL_E | FLASHCTL_AC));
1845 +
1846 + ar231x_write_reg(AR5312_FLASHCTL2,
1847 + ar231x_read_reg(AR5312_FLASHCTL2) &
1848 + ~(FLASHCTL_E | FLASHCTL_AC));
1849 +
1850 + return (char *)KSEG1ADDR(AR5312_FLASH + 0x800000);
1851 +}
1852 +
1853 +int __init ar5312_init_devices(void)
1854 +{
1855 + struct ar231x_boarddata *config;
1856 + u32 fctl = 0;
1857 + u8 *c;
1858 +
1859 + if (!is_5312())
1860 + return 0;
1861 +
1862 + /* Locate board/radio config data */
1863 + ar231x_find_config(ar5312_flash_limit());
1864 + config = ar231x_board.config;
1865 +
1866 + /* AR2313 has CPU minor rev. 10 */
1867 + if ((current_cpu_data.processor_id & 0xff) == 0x0a)
1868 + ar231x_devtype = DEV_TYPE_AR2313;
1869 +
1870 + /* AR2312 shares the same Silicon ID as AR5312 */
1871 + else if (config->flags & BD_ISCASPER)
1872 + ar231x_devtype = DEV_TYPE_AR2312;
1873 +
1874 + /* Everything else is probably AR5312 or compatible */
1875 + else
1876 + ar231x_devtype = DEV_TYPE_AR5312;
1877 +
1878 + /* fixup flash width */
1879 + fctl = ar231x_read_reg(AR5312_FLASHCTL) & FLASHCTL_MW;
1880 + switch (fctl) {
1881 + case FLASHCTL_MW16:
1882 + ar5312_flash_data.width = 2;
1883 + break;
1884 + case FLASHCTL_MW8:
1885 + default:
1886 + ar5312_flash_data.width = 1;
1887 + break;
1888 + }
1889 +
1890 + platform_device_register(&ar5312_physmap_flash);
1891 +
1892 +#ifdef CONFIG_LEDS_GPIO
1893 + ar5312_leds[0].gpio = config->sys_led_gpio;
1894 + platform_device_register(&ar5312_gpio_leds);
1895 +#endif
1896 +
1897 + /* Fix up MAC addresses if necessary */
1898 + if (is_broadcast_ether_addr(config->enet0_mac))
1899 + ether_addr_copy(config->enet0_mac, config->enet1_mac);
1900 +
1901 + /* If ENET0 and ENET1 have the same mac address,
1902 + * increment the one from ENET1 */
1903 + if (ether_addr_equal(config->enet0_mac, config->enet1_mac)) {
1904 + c = config->enet1_mac + 5;
1905 + while ((c >= config->enet1_mac) && !(++(*c)))
1906 + c--;
1907 + }
1908 +
1909 + switch (ar231x_devtype) {
1910 + case DEV_TYPE_AR5312:
1911 + ar5312_eth0_data.macaddr = config->enet0_mac;
1912 + ar231x_add_ethernet(0, AR5312_ENET0, "eth0_mii",
1913 + AR5312_ENET0_MII, AR5312_IRQ_ENET0_INTRS,
1914 + &ar5312_eth0_data);
1915 +
1916 + ar5312_eth1_data.macaddr = config->enet1_mac;
1917 + ar231x_add_ethernet(1, AR5312_ENET1, "eth1_mii",
1918 + AR5312_ENET1_MII, AR5312_IRQ_ENET1_INTRS,
1919 + &ar5312_eth1_data);
1920 +
1921 + if (!ar231x_board.radio)
1922 + return 0;
1923 +
1924 + if (!(config->flags & BD_WLAN0))
1925 + break;
1926 +
1927 + ar231x_add_wmac(0, AR5312_WLAN0, AR5312_IRQ_WLAN0_INTRS);
1928 + break;
1929 + /*
1930 + * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
1931 + * of ENET1. Atheros calls it 'twisted' for a reason :)
1932 + */
1933 + case DEV_TYPE_AR2312:
1934 + case DEV_TYPE_AR2313:
1935 + ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
1936 + ar5312_eth1_data.macaddr = config->enet0_mac;
1937 + ar231x_add_ethernet(1, AR5312_ENET1, "eth0_mii",
1938 + AR5312_ENET0_MII, AR5312_IRQ_ENET1_INTRS,
1939 + &ar5312_eth1_data);
1940 +
1941 + if (!ar231x_board.radio)
1942 + return 0;
1943 + break;
1944 + default:
1945 + break;
1946 + }
1947 +
1948 + if (config->flags & BD_WLAN1)
1949 + ar231x_add_wmac(1, AR5312_WLAN1, AR5312_IRQ_WLAN1_INTRS);
1950 +
1951 + return 0;
1952 +}
1953 +
1954 +
1955 +static void ar5312_restart(char *command)
1956 +{
1957 + /* reset the system */
1958 + local_irq_disable();
1959 + while (1)
1960 + ar231x_write_reg(AR5312_RESET, AR5312_RESET_SYSTEM);
1961 +}
1962 +
1963 +
1964 +/*
1965 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
1966 + * to determine the predevisor value.
1967 + */
1968 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
1969 +
1970 +
1971 +static int __init
1972 +ar5312_cpu_frequency(void)
1973 +{
1974 + unsigned int scratch;
1975 + unsigned int predivide_mask, predivide_shift;
1976 + unsigned int multiplier_mask, multiplier_shift;
1977 + unsigned int clock_ctl1, predivide_select, predivisor, multiplier;
1978 + unsigned int doubler_mask;
1979 + u16 devid;
1980 +
1981 + /* Trust the bootrom's idea of cpu frequency. */
1982 + scratch = ar231x_read_reg(AR5312_SCRATCH);
1983 + if (scratch)
1984 + return scratch;
1985 +
1986 + devid = ar231x_read_reg(AR5312_REV);
1987 + devid &= AR5312_REV_MAJ;
1988 + devid >>= AR5312_REV_MAJ_S;
1989 + if (devid == AR5312_REV_MAJ_AR2313) {
1990 + predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
1991 + predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
1992 + multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
1993 + multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
1994 + doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
1995 + } else { /* AR5312 and AR2312 */
1996 + predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
1997 + predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
1998 + multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
1999 + multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
2000 + doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
2001 + }
2002 +
2003 + /*
2004 + * Clocking is derived from a fixed 40MHz input clock.
2005 + *
2006 + * cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
2007 + * sys_freq = cpu_freq / 4 (used for APB clock, serial,
2008 + * flash, Timer, Watchdog Timer)
2009 + *
2010 + * cnt_freq = cpu_freq / 2 (use for CPU count/compare)
2011 + *
2012 + * So, for example, with a PLL multiplier of 5, we have
2013 + *
2014 + * cpu_freq = 200MHz
2015 + * sys_freq = 50MHz
2016 + * cnt_freq = 100MHz
2017 + *
2018 + * We compute the CPU frequency, based on PLL settings.
2019 + */
2020 +
2021 + clock_ctl1 = ar231x_read_reg(AR5312_CLOCKCTL1);
2022 + predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
2023 + predivisor = clockctl1_predivide_table[predivide_select];
2024 + multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
2025 +
2026 + if (clock_ctl1 & doubler_mask)
2027 + multiplier = multiplier << 1;
2028 +
2029 + return (40000000 / predivisor) * multiplier;
2030 +}
2031 +
2032 +static inline int
2033 +ar5312_sys_frequency(void)
2034 +{
2035 + return ar5312_cpu_frequency() / 4;
2036 +}
2037 +
2038 +void __init
2039 +ar5312_time_init(void)
2040 +{
2041 + if (!is_5312())
2042 + return;
2043 +
2044 + mips_hpt_frequency = ar5312_cpu_frequency() / 2;
2045 +}
2046 +
2047 +static int __init
2048 +ar5312_gpio_init(void)
2049 +{
2050 + int ret = gpiochip_add(&ar5312_gpio_chip);
2051 +
2052 + if (ret) {
2053 + pr_err("%s: failed to add gpiochip\n", ar5312_gpio_chip.label);
2054 + return ret;
2055 + }
2056 + pr_info("%s: registered %d GPIOs\n", ar5312_gpio_chip.label,
2057 + ar5312_gpio_chip.ngpio);
2058 + return ret;
2059 +}
2060 +
2061 +void __init
2062 +ar5312_prom_init(void)
2063 +{
2064 + u32 memsize, memcfg, bank0AC, bank1AC;
2065 + u32 devid;
2066 +
2067 + if (!is_5312())
2068 + return;
2069 +
2070 + /* Detect memory size */
2071 + memcfg = ar231x_read_reg(AR5312_MEM_CFG1);
2072 + bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
2073 + bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
2074 + memsize = (bank0AC ? (1 << (bank0AC+1)) : 0) +
2075 + (bank1AC ? (1 << (bank1AC+1)) : 0);
2076 + memsize <<= 20;
2077 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2078 +
2079 + devid = ar231x_read_reg(AR5312_REV);
2080 + devid >>= AR5312_REV_WMAC_MIN_S;
2081 + devid &= AR5312_REV_CHIP;
2082 + ar231x_board.devid = (u16) devid;
2083 + ar5312_gpio_init();
2084 +}
2085 +
2086 +void __init
2087 +ar5312_plat_setup(void)
2088 +{
2089 + if (!is_5312())
2090 + return;
2091 +
2092 + /* Clear any lingering AHB errors */
2093 + ar231x_read_reg(AR5312_PROCADDR);
2094 + ar231x_read_reg(AR5312_DMAADDR);
2095 + ar231x_write_reg(AR5312_WD_CTRL, AR5312_WD_CTRL_IGNORE_EXPIRATION);
2096 +
2097 + _machine_restart = ar5312_restart;
2098 + ar231x_serial_setup(AR5312_UART0, AR5312_MISC_IRQ_UART0,
2099 + ar5312_sys_frequency());
2100 +}
2101 +
2102 --- /dev/null
2103 +++ b/arch/mips/ar231x/ar2315.c
2104 @@ -0,0 +1,559 @@
2105 +/*
2106 + * This file is subject to the terms and conditions of the GNU General Public
2107 + * License. See the file "COPYING" in the main directory of this archive
2108 + * for more details.
2109 + *
2110 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
2111 + * Copyright (C) 2006 FON Technology, SL.
2112 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
2113 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
2114 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
2115 + */
2116 +
2117 +/*
2118 + * Platform devices for Atheros SoCs
2119 + */
2120 +
2121 +#include <generated/autoconf.h>
2122 +#include <linux/init.h>
2123 +#include <linux/module.h>
2124 +#include <linux/types.h>
2125 +#include <linux/string.h>
2126 +#include <linux/platform_device.h>
2127 +#include <linux/kernel.h>
2128 +#include <linux/reboot.h>
2129 +#include <linux/delay.h>
2130 +#include <linux/leds.h>
2131 +#include <linux/gpio.h>
2132 +#include <asm/bootinfo.h>
2133 +#include <asm/reboot.h>
2134 +#include <asm/time.h>
2135 +#include <linux/irq.h>
2136 +#include <linux/io.h>
2137 +
2138 +#include <ar231x_platform.h>
2139 +#include <ar2315_regs.h>
2140 +#include <ar231x.h>
2141 +#include "devices.h"
2142 +#include "ar2315.h"
2143 +
2144 +static u32 gpiointmask, gpiointval;
2145 +
2146 +static void ar2315_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
2147 +{
2148 + u32 pend;
2149 + int bit = -1;
2150 +
2151 + /* only do one gpio interrupt at a time */
2152 + pend = (ar231x_read_reg(AR2315_GPIO_DI) ^ gpiointval) & gpiointmask;
2153 +
2154 + if (pend) {
2155 + bit = fls(pend) - 1;
2156 + pend &= ~(1 << bit);
2157 + gpiointval ^= (1 << bit);
2158 + }
2159 +
2160 + if (!pend)
2161 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO);
2162 +
2163 + /* Enable interrupt with edge detection */
2164 + if ((ar231x_read_reg(AR2315_GPIO_DIR) & AR2315_GPIO_DIR_M(bit)) !=
2165 + AR2315_GPIO_DIR_I(bit))
2166 + return;
2167 +
2168 + if (bit >= 0)
2169 + do_IRQ(AR231X_GPIO_IRQ_BASE + bit);
2170 +}
2171 +
2172 +static void ar2315_misc_irq_handler(unsigned irq, struct irq_desc *desc)
2173 +{
2174 + unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) &
2175 + ar231x_read_reg(AR2315_IMR);
2176 +
2177 + if (misc_intr & AR2315_ISR_SPI)
2178 + do_IRQ(AR2315_MISC_IRQ_SPI);
2179 + else if (misc_intr & AR2315_ISR_TIMER)
2180 + do_IRQ(AR2315_MISC_IRQ_TIMER);
2181 + else if (misc_intr & AR2315_ISR_AHB)
2182 + do_IRQ(AR2315_MISC_IRQ_AHB);
2183 + else if (misc_intr & AR2315_ISR_GPIO)
2184 + do_IRQ(AR2315_MISC_IRQ_GPIO);
2185 + else if (misc_intr & AR2315_ISR_UART0)
2186 + do_IRQ(AR2315_MISC_IRQ_UART0);
2187 + else if (misc_intr & AR2315_ISR_WD) {
2188 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_WD);
2189 + do_IRQ(AR2315_MISC_IRQ_WATCHDOG);
2190 + } else
2191 + do_IRQ(AR2315_MISC_IRQ_NONE);
2192 +}
2193 +
2194 +/*
2195 + * Called when an interrupt is received, this function
2196 + * determines exactly which interrupt it was, and it
2197 + * invokes the appropriate handler.
2198 + *
2199 + * Implicitly, we also define interrupt priority by
2200 + * choosing which to dispatch first.
2201 + */
2202 +static asmlinkage void
2203 +ar2315_irq_dispatch(void)
2204 +{
2205 + int pending = read_c0_status() & read_c0_cause();
2206 +
2207 + if (pending & CAUSEF_IP3)
2208 + do_IRQ(AR2315_IRQ_WLAN0_INTRS);
2209 + else if (pending & CAUSEF_IP4)
2210 + do_IRQ(AR2315_IRQ_ENET0_INTRS);
2211 + else if (pending & CAUSEF_IP2)
2212 + do_IRQ(AR2315_IRQ_MISC_INTRS);
2213 + else if (pending & CAUSEF_IP7)
2214 + do_IRQ(AR231X_IRQ_CPU_CLOCK);
2215 +}
2216 +
2217 +static void ar2315_set_gpiointmask(int gpio, int level)
2218 +{
2219 + u32 reg;
2220 +
2221 + reg = ar231x_read_reg(AR2315_GPIO_INT);
2222 + reg &= ~(AR2315_GPIO_INT_M | AR2315_GPIO_INT_LVL_M);
2223 + reg |= gpio | AR2315_GPIO_INT_LVL(level);
2224 + ar231x_write_reg(AR2315_GPIO_INT, reg);
2225 +}
2226 +
2227 +static void ar2315_gpio_irq_unmask(struct irq_data *d)
2228 +{
2229 + unsigned int gpio = d->irq - AR231X_GPIO_IRQ_BASE;
2230 +
2231 + /* Enable interrupt with edge detection */
2232 + if ((ar231x_read_reg(AR2315_GPIO_DIR) & AR2315_GPIO_DIR_M(gpio)) !=
2233 + AR2315_GPIO_DIR_I(gpio))
2234 + return;
2235 +
2236 + gpiointmask |= (1 << gpio);
2237 + ar2315_set_gpiointmask(gpio, 3);
2238 +}
2239 +
2240 +static void ar2315_gpio_irq_mask(struct irq_data *d)
2241 +{
2242 + unsigned int gpio = d->irq - AR231X_GPIO_IRQ_BASE;
2243 +
2244 + /* Disable interrupt */
2245 + gpiointmask &= ~(1 << gpio);
2246 + ar2315_set_gpiointmask(gpio, 0);
2247 +}
2248 +
2249 +static struct irq_chip ar2315_gpio_irq_chip = {
2250 + .name = "AR2315-GPIO",
2251 + .irq_unmask = ar2315_gpio_irq_unmask,
2252 + .irq_mask = ar2315_gpio_irq_mask,
2253 +};
2254 +
2255 +static void
2256 +ar2315_misc_irq_unmask(struct irq_data *d)
2257 +{
2258 + unsigned int imr;
2259 +
2260 + imr = ar231x_read_reg(AR2315_IMR);
2261 + imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE - 1);
2262 + ar231x_write_reg(AR2315_IMR, imr);
2263 +}
2264 +
2265 +static void
2266 +ar2315_misc_irq_mask(struct irq_data *d)
2267 +{
2268 + unsigned int imr;
2269 +
2270 + imr = ar231x_read_reg(AR2315_IMR);
2271 + imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE - 1));
2272 + ar231x_write_reg(AR2315_IMR, imr);
2273 +}
2274 +
2275 +static struct irq_chip ar2315_misc_irq_chip = {
2276 + .name = "AR2315-MISC",
2277 + .irq_unmask = ar2315_misc_irq_unmask,
2278 + .irq_mask = ar2315_misc_irq_mask,
2279 +};
2280 +
2281 +static irqreturn_t ar2315_ahb_proc_handler(int cpl, void *dev_id)
2282 +{
2283 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2284 + ar231x_read_reg(AR2315_AHB_ERR1);
2285 +
2286 + pr_emerg("AHB fatal error\n");
2287 + machine_restart("AHB error"); /* Catastrophic failure */
2288 +
2289 + return IRQ_HANDLED;
2290 +}
2291 +
2292 +static struct irqaction ar2315_ahb_proc_interrupt = {
2293 + .handler = ar2315_ahb_proc_handler,
2294 + .name = "ar2315_ahb_proc_interrupt",
2295 +};
2296 +
2297 +void
2298 +ar2315_irq_init(void)
2299 +{
2300 + int i;
2301 +
2302 + if (!is_2315())
2303 + return;
2304 +
2305 + ar231x_irq_dispatch = ar2315_irq_dispatch;
2306 + gpiointval = ar231x_read_reg(AR2315_GPIO_DI);
2307 + for (i = 0; i < AR2315_MISC_IRQ_COUNT; i++) {
2308 + int irq = AR231X_MISC_IRQ_BASE + i;
2309 +
2310 + irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip,
2311 + handle_level_irq);
2312 + }
2313 + for (i = 0; i < AR2315_NUM_GPIO; i++) {
2314 + int irq = AR231X_GPIO_IRQ_BASE + i;
2315 +
2316 + irq_set_chip_and_handler(irq, &ar2315_gpio_irq_chip,
2317 + handle_level_irq);
2318 + }
2319 + irq_set_chained_handler(AR2315_MISC_IRQ_GPIO, ar2315_gpio_irq_handler);
2320 + setup_irq(AR2315_MISC_IRQ_AHB, &ar2315_ahb_proc_interrupt);
2321 + irq_set_chained_handler(AR2315_IRQ_MISC_INTRS, ar2315_misc_irq_handler);
2322 +}
2323 +
2324 +/*
2325 + * gpiolib implementation
2326 + */
2327 +static int
2328 +ar2315_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
2329 +{
2330 + return (ar231x_read_reg(AR2315_GPIO_DI) >> gpio) & 1;
2331 +}
2332 +
2333 +static void
2334 +ar2315_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
2335 +{
2336 + u32 reg = ar231x_read_reg(AR2315_GPIO_DO);
2337 +
2338 + reg = value ? reg | (1 << gpio) : reg & ~(1 << gpio);
2339 + ar231x_write_reg(AR2315_GPIO_DO, reg);
2340 +}
2341 +
2342 +static int
2343 +ar2315_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
2344 +{
2345 + ar231x_mask_reg(AR2315_GPIO_DIR, 1 << gpio, 0);
2346 + return 0;
2347 +}
2348 +
2349 +static int
2350 +ar2315_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
2351 +{
2352 + ar231x_mask_reg(AR2315_GPIO_DIR, 0, 1 << gpio);
2353 + ar2315_gpio_set_value(chip, gpio, value);
2354 + return 0;
2355 +}
2356 +
2357 +static struct gpio_chip ar2315_gpio_chip = {
2358 + .label = "ar2315-gpio",
2359 + .direction_input = ar2315_gpio_direction_input,
2360 + .direction_output = ar2315_gpio_direction_output,
2361 + .set = ar2315_gpio_set_value,
2362 + .get = ar2315_gpio_get_value,
2363 + .base = 0,
2364 + .ngpio = AR2315_NUM_GPIO, /* 22 */
2365 +};
2366 +
2367 +/* end of gpiolib */
2368 +
2369 +static void ar2315_device_reset_set(u32 mask)
2370 +{
2371 + u32 val;
2372 +
2373 + val = ar231x_read_reg(AR2315_RESET);
2374 + ar231x_write_reg(AR2315_RESET, val | mask);
2375 +}
2376 +
2377 +static void ar2315_device_reset_clear(u32 mask)
2378 +{
2379 + u32 val;
2380 +
2381 + val = ar231x_read_reg(AR2315_RESET);
2382 + ar231x_write_reg(AR2315_RESET, val & ~mask);
2383 +}
2384 +
2385 +static struct ar231x_eth ar2315_eth_data = {
2386 + .reset_set = ar2315_device_reset_set,
2387 + .reset_clear = ar2315_device_reset_clear,
2388 + .reset_mac = AR2315_RESET_ENET0,
2389 + .reset_phy = AR2315_RESET_EPHY0,
2390 + .config = &ar231x_board,
2391 +};
2392 +
2393 +static struct resource ar2315_spiflash_res[] = {
2394 + {
2395 + .name = "spiflash_read",
2396 + .flags = IORESOURCE_MEM,
2397 + .start = AR2315_SPI_READ,
2398 + .end = AR2315_SPI_READ + 0x1000000 - 1,
2399 + },
2400 + {
2401 + .name = "spiflash_mmr",
2402 + .flags = IORESOURCE_MEM,
2403 + .start = AR2315_SPI_MMR,
2404 + .end = AR2315_SPI_MMR + 12 - 1,
2405 + },
2406 +};
2407 +
2408 +static struct platform_device ar2315_spiflash = {
2409 + .id = 0,
2410 + .name = "ar2315-spiflash",
2411 + .resource = ar2315_spiflash_res,
2412 + .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
2413 +};
2414 +
2415 +static struct resource ar2315_wdt_res[] = {
2416 + {
2417 + .flags = IORESOURCE_MEM,
2418 + .start = AR2315_WD,
2419 + .end = AR2315_WD + 8 - 1,
2420 + },
2421 + {
2422 + .flags = IORESOURCE_IRQ,
2423 + .start = AR2315_MISC_IRQ_WATCHDOG,
2424 + .end = AR2315_MISC_IRQ_WATCHDOG,
2425 + }
2426 +};
2427 +
2428 +static struct platform_device ar2315_wdt = {
2429 + .id = 0,
2430 + .name = "ar2315-wdt",
2431 + .resource = ar2315_wdt_res,
2432 + .num_resources = ARRAY_SIZE(ar2315_wdt_res)
2433 +};
2434 +
2435 +/*
2436 + * NB: We use mapping size that is larger than the actual flash size,
2437 + * but this shouldn't be a problem here, because the flash will simply
2438 + * be mapped multiple times.
2439 + */
2440 +static u8 __init *ar2315_flash_limit(void)
2441 +{
2442 + return (u8 *)KSEG1ADDR(ar2315_spiflash_res[0].end + 1);
2443 +}
2444 +
2445 +#ifdef CONFIG_LEDS_GPIO
2446 +static struct gpio_led ar2315_leds[6];
2447 +static struct gpio_led_platform_data ar2315_led_data = {
2448 + .leds = (void *)ar2315_leds,
2449 +};
2450 +
2451 +static struct platform_device ar2315_gpio_leds = {
2452 + .name = "leds-gpio",
2453 + .id = -1,
2454 + .dev = {
2455 + .platform_data = (void *)&ar2315_led_data,
2456 + }
2457 +};
2458 +
2459 +static void __init
2460 +ar2315_init_gpio_leds(void)
2461 +{
2462 + static char led_names[6][6];
2463 + int i, led = 0;
2464 +
2465 + ar2315_led_data.num_leds = 0;
2466 + for (i = 1; i < 8; i++) {
2467 + if ((i == AR2315_RESET_GPIO) ||
2468 + (i == ar231x_board.config->reset_config_gpio))
2469 + continue;
2470 +
2471 + if (i == ar231x_board.config->sys_led_gpio)
2472 + strcpy(led_names[led], "wlan");
2473 + else
2474 + sprintf(led_names[led], "gpio%d", i);
2475 +
2476 + ar2315_leds[led].name = led_names[led];
2477 + ar2315_leds[led].gpio = i;
2478 + ar2315_leds[led].active_low = 0;
2479 + led++;
2480 + }
2481 + ar2315_led_data.num_leds = led;
2482 + platform_device_register(&ar2315_gpio_leds);
2483 +}
2484 +#else
2485 +static inline void ar2315_init_gpio_leds(void)
2486 +{
2487 +}
2488 +#endif
2489 +
2490 +int __init
2491 +ar2315_init_devices(void)
2492 +{
2493 + if (!is_2315())
2494 + return 0;
2495 +
2496 + /* Find board configuration */
2497 + ar231x_find_config(ar2315_flash_limit());
2498 + ar2315_eth_data.macaddr = ar231x_board.config->enet0_mac;
2499 +
2500 + ar2315_init_gpio_leds();
2501 + platform_device_register(&ar2315_wdt);
2502 + platform_device_register(&ar2315_spiflash);
2503 + ar231x_add_ethernet(0, AR2315_ENET0, "eth0_mii", AR2315_ENET0_MII,
2504 + AR2315_IRQ_ENET0_INTRS, &ar2315_eth_data);
2505 + ar231x_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS);
2506 +
2507 + return 0;
2508 +}
2509 +
2510 +static void
2511 +ar2315_restart(char *command)
2512 +{
2513 + void (*mips_reset_vec)(void) = (void *)0xbfc00000;
2514 +
2515 + local_irq_disable();
2516 +
2517 + /* try reset the system via reset control */
2518 + ar231x_write_reg(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
2519 +
2520 + /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
2521 + * a workaround. Give it some time to attempt a gpio based hardware
2522 + * reset (atheros reference design workaround) */
2523 + gpio_request_one(AR2315_RESET_GPIO, GPIOF_OUT_INIT_LOW, "Reset");
2524 + mdelay(100);
2525 +
2526 + /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
2527 + * workaround. Attempt to jump to the mips reset location -
2528 + * the boot loader itself might be able to recover the system */
2529 + mips_reset_vec();
2530 +}
2531 +
2532 +
2533 +/*
2534 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
2535 + * to determine the predevisor value.
2536 + */
2537 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
2538 +static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
2539 +
2540 +static unsigned int __init
2541 +ar2315_sys_clk(unsigned int clock_ctl)
2542 +{
2543 + unsigned int pllc_ctrl, cpu_div;
2544 + unsigned int pllc_out, refdiv, fdiv, divby2;
2545 + unsigned int clk_div;
2546 +
2547 + pllc_ctrl = ar231x_read_reg(AR2315_PLLC_CTL);
2548 + refdiv = (pllc_ctrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
2549 + refdiv = clockctl1_predivide_table[refdiv];
2550 + fdiv = (pllc_ctrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
2551 + divby2 = (pllc_ctrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
2552 + divby2 += 1;
2553 + pllc_out = (40000000/refdiv)*(2*divby2)*fdiv;
2554 +
2555 + /* clkm input selected */
2556 + switch (clock_ctl & CPUCLK_CLK_SEL_M) {
2557 + case 0:
2558 + case 1:
2559 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKM_DIV_M) >>
2560 + PLLC_CLKM_DIV_S];
2561 + break;
2562 + case 2:
2563 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKC_DIV_M) >>
2564 + PLLC_CLKC_DIV_S];
2565 + break;
2566 + default:
2567 + pllc_out = 40000000;
2568 + clk_div = 1;
2569 + break;
2570 + }
2571 +
2572 + cpu_div = (clock_ctl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
2573 + cpu_div = cpu_div * 2 ?: 1;
2574 +
2575 + return pllc_out / (clk_div * cpu_div);
2576 +}
2577 +
2578 +static inline unsigned int
2579 +ar2315_cpu_frequency(void)
2580 +{
2581 + return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK));
2582 +}
2583 +
2584 +static inline unsigned int
2585 +ar2315_apb_frequency(void)
2586 +{
2587 + return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK));
2588 +}
2589 +
2590 +void __init
2591 +ar2315_time_init(void)
2592 +{
2593 + if (!is_2315())
2594 + return;
2595 +
2596 + mips_hpt_frequency = ar2315_cpu_frequency() / 2;
2597 +}
2598 +
2599 +static int __init
2600 +ar2315_gpio_init(void)
2601 +{
2602 + int ret = gpiochip_add(&ar2315_gpio_chip);
2603 +
2604 + if (ret) {
2605 + pr_err("%s: failed to add gpiochip\n", ar2315_gpio_chip.label);
2606 + return ret;
2607 + }
2608 + pr_info("%s: registered %d GPIOs\n", ar2315_gpio_chip.label,
2609 + ar2315_gpio_chip.ngpio);
2610 + return ret;
2611 +}
2612 +
2613 +
2614 +
2615 +void __init
2616 +ar2315_prom_init(void)
2617 +{
2618 + u32 memsize, memcfg, devid;
2619 +
2620 + if (!is_2315())
2621 + return;
2622 +
2623 + memcfg = ar231x_read_reg(AR2315_MEM_CFG);
2624 + memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
2625 + memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
2626 + memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
2627 + memsize <<= 3;
2628 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2629 +
2630 + /* Detect the hardware based on the device ID */
2631 + devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP;
2632 + switch (devid) {
2633 + case 0x90:
2634 + case 0x91:
2635 + ar231x_devtype = DEV_TYPE_AR2317;
2636 + break;
2637 + default:
2638 + ar231x_devtype = DEV_TYPE_AR2315;
2639 + break;
2640 + }
2641 + ar2315_gpio_init();
2642 + ar231x_board.devid = devid;
2643 +}
2644 +
2645 +void __init
2646 +ar2315_plat_setup(void)
2647 +{
2648 + u32 config;
2649 +
2650 + if (!is_2315())
2651 + return;
2652 +
2653 + /* Clear any lingering AHB errors */
2654 + config = read_c0_config();
2655 + write_c0_config(config & ~0x3);
2656 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2657 + ar231x_read_reg(AR2315_AHB_ERR1);
2658 + ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION);
2659 +
2660 + _machine_restart = ar2315_restart;
2661 + ar231x_serial_setup(AR2315_UART0, AR2315_MISC_IRQ_UART0,
2662 + ar2315_apb_frequency());
2663 +}
2664 --- /dev/null
2665 +++ b/arch/mips/ar231x/ar2315.h
2666 @@ -0,0 +1,37 @@
2667 +#ifndef __AR2315_H
2668 +#define __AR2315_H
2669 +
2670 +#ifdef CONFIG_ATHEROS_AR2315
2671 +
2672 +void ar2315_irq_init(void);
2673 +int ar2315_init_devices(void);
2674 +void ar2315_prom_init(void);
2675 +void ar2315_plat_setup(void);
2676 +void ar2315_time_init(void);
2677 +
2678 +#else
2679 +
2680 +static inline void ar2315_irq_init(void)
2681 +{
2682 +}
2683 +
2684 +static inline int ar2315_init_devices(void)
2685 +{
2686 + return 0;
2687 +}
2688 +
2689 +static inline void ar2315_prom_init(void)
2690 +{
2691 +}
2692 +
2693 +static inline void ar2315_plat_setup(void)
2694 +{
2695 +}
2696 +
2697 +static inline void ar2315_time_init(void)
2698 +{
2699 +}
2700 +
2701 +#endif
2702 +
2703 +#endif
2704 --- /dev/null
2705 +++ b/arch/mips/ar231x/ar5312.h
2706 @@ -0,0 +1,37 @@
2707 +#ifndef __AR5312_H
2708 +#define __AR5312_H
2709 +
2710 +#ifdef CONFIG_ATHEROS_AR5312
2711 +
2712 +void ar5312_irq_init(void);
2713 +int ar5312_init_devices(void);
2714 +void ar5312_prom_init(void);
2715 +void ar5312_plat_setup(void);
2716 +void ar5312_time_init(void);
2717 +
2718 +#else
2719 +
2720 +static inline void ar5312_irq_init(void)
2721 +{
2722 +}
2723 +
2724 +static inline int ar5312_init_devices(void)
2725 +{
2726 + return 0;
2727 +}
2728 +
2729 +static inline void ar5312_prom_init(void)
2730 +{
2731 +}
2732 +
2733 +static inline void ar5312_plat_setup(void)
2734 +{
2735 +}
2736 +
2737 +static inline void ar5312_time_init(void)
2738 +{
2739 +}
2740 +
2741 +#endif
2742 +
2743 +#endif
2744 --- /dev/null
2745 +++ b/arch/mips/include/asm/mach-ar231x/ar231x.h
2746 @@ -0,0 +1,43 @@
2747 +#ifndef __ASM_MACH_AR231X_H
2748 +#define __ASM_MACH_AR231X_H
2749 +
2750 +#include <linux/types.h>
2751 +#include <linux/io.h>
2752 +
2753 +#define AR231X_MISC_IRQ_BASE 0x20
2754 +#define AR231X_GPIO_IRQ_BASE 0x30
2755 +
2756 +/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
2757 +#define AR231X_IRQ_NONE (MIPS_CPU_IRQ_BASE+0)
2758 +#define AR231X_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE+7) /* C0_CAUSE: 0x8000 */
2759 +
2760 +/* GPIO Interrupts, share ARXXXX_MISC_IRQ_GPIO */
2761 +#define AR231X_GPIO_IRQ_NONE (AR231X_GPIO_IRQ_BASE+0)
2762 +#define AR231X_GPIO_IRQ(n) (AR231X_GPIO_IRQ_BASE+n)
2763 +
2764 +static inline u32
2765 +ar231x_read_reg(u32 reg)
2766 +{
2767 + return __raw_readl((void __iomem *)KSEG1ADDR(reg));
2768 +}
2769 +
2770 +static inline void
2771 +ar231x_write_reg(u32 reg, u32 val)
2772 +{
2773 + __raw_writel(val, (void __iomem *)KSEG1ADDR(reg));
2774 +}
2775 +
2776 +static inline u32
2777 +ar231x_mask_reg(u32 reg, u32 mask, u32 val)
2778 +{
2779 + u32 ret;
2780 +
2781 + ret = ar231x_read_reg(reg);
2782 + ret &= ~mask;
2783 + ret |= val;
2784 + ar231x_write_reg(reg, ret);
2785 +
2786 + return ret;
2787 +}
2788 +
2789 +#endif /* __ASM_MACH_AR231X_H */
2790 --- /dev/null
2791 +++ b/arch/mips/ar231x/devices.h
2792 @@ -0,0 +1,38 @@
2793 +#ifndef __AR231X_DEVICES_H
2794 +#define __AR231X_DEVICES_H
2795 +
2796 +enum {
2797 + /* handled by ar5312.c */
2798 + DEV_TYPE_AR2312,
2799 + DEV_TYPE_AR2313,
2800 + DEV_TYPE_AR5312,
2801 +
2802 + /* handled by ar2315.c */
2803 + DEV_TYPE_AR2315,
2804 + DEV_TYPE_AR2316,
2805 + DEV_TYPE_AR2317,
2806 +
2807 + DEV_TYPE_UNKNOWN
2808 +};
2809 +
2810 +extern int ar231x_devtype;
2811 +extern struct ar231x_board_config ar231x_board;
2812 +extern asmlinkage void (*ar231x_irq_dispatch)(void);
2813 +
2814 +int ar231x_find_config(u8 *flash_limit);
2815 +void ar231x_serial_setup(u32 mapbase, int irq, unsigned int uartclk);
2816 +int ar231x_add_wmac(int nr, u32 base, int irq);
2817 +int ar231x_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
2818 + int irq, void *pdata);
2819 +
2820 +static inline bool is_2315(void)
2821 +{
2822 + return (current_cpu_data.cputype == CPU_4KEC);
2823 +}
2824 +
2825 +static inline bool is_5312(void)
2826 +{
2827 + return !is_2315();
2828 +}
2829 +
2830 +#endif
2831 --- /dev/null
2832 +++ b/arch/mips/ar231x/devices.c
2833 @@ -0,0 +1,182 @@
2834 +#include <linux/kernel.h>
2835 +#include <linux/init.h>
2836 +#include <linux/serial.h>
2837 +#include <linux/serial_core.h>
2838 +#include <linux/serial_8250.h>
2839 +#include <linux/platform_device.h>
2840 +#include <asm/bootinfo.h>
2841 +
2842 +#include <ar231x_platform.h>
2843 +#include <ar231x.h>
2844 +#include "devices.h"
2845 +#include "ar5312.h"
2846 +#include "ar2315.h"
2847 +
2848 +struct ar231x_board_config ar231x_board;
2849 +int ar231x_devtype = DEV_TYPE_UNKNOWN;
2850 +
2851 +static struct resource ar231x_eth0_res[] = {
2852 + {
2853 + .name = "eth0_membase",
2854 + .flags = IORESOURCE_MEM,
2855 + },
2856 + {
2857 + .name = "eth0_mii",
2858 + .flags = IORESOURCE_MEM,
2859 + },
2860 + {
2861 + .name = "eth0_irq",
2862 + .flags = IORESOURCE_IRQ,
2863 + }
2864 +};
2865 +
2866 +static struct resource ar231x_eth1_res[] = {
2867 + {
2868 + .name = "eth1_membase",
2869 + .flags = IORESOURCE_MEM,
2870 + },
2871 + {
2872 + .name = "eth1_mii",
2873 + .flags = IORESOURCE_MEM,
2874 + },
2875 + {
2876 + .name = "eth1_irq",
2877 + .flags = IORESOURCE_IRQ,
2878 + }
2879 +};
2880 +
2881 +static struct platform_device ar231x_eth[] = {
2882 + {
2883 + .id = 0,
2884 + .name = "ar231x-eth",
2885 + .resource = ar231x_eth0_res,
2886 + .num_resources = ARRAY_SIZE(ar231x_eth0_res)
2887 + },
2888 + {
2889 + .id = 1,
2890 + .name = "ar231x-eth",
2891 + .resource = ar231x_eth1_res,
2892 + .num_resources = ARRAY_SIZE(ar231x_eth1_res)
2893 + }
2894 +};
2895 +
2896 +static struct resource ar231x_wmac0_res[] = {
2897 + {
2898 + .name = "wmac0_membase",
2899 + .flags = IORESOURCE_MEM,
2900 + },
2901 + {
2902 + .name = "wmac0_irq",
2903 + .flags = IORESOURCE_IRQ,
2904 + }
2905 +};
2906 +
2907 +static struct resource ar231x_wmac1_res[] = {
2908 + {
2909 + .name = "wmac1_membase",
2910 + .flags = IORESOURCE_MEM,
2911 + },
2912 + {
2913 + .name = "wmac1_irq",
2914 + .flags = IORESOURCE_IRQ,
2915 + }
2916 +};
2917 +
2918 +
2919 +static struct platform_device ar231x_wmac[] = {
2920 + {
2921 + .id = 0,
2922 + .name = "ar231x-wmac",
2923 + .resource = ar231x_wmac0_res,
2924 + .num_resources = ARRAY_SIZE(ar231x_wmac0_res),
2925 + .dev.platform_data = &ar231x_board,
2926 + },
2927 + {
2928 + .id = 1,
2929 + .name = "ar231x-wmac",
2930 + .resource = ar231x_wmac1_res,
2931 + .num_resources = ARRAY_SIZE(ar231x_wmac1_res),
2932 + .dev.platform_data = &ar231x_board,
2933 + },
2934 +};
2935 +
2936 +static const char * const devtype_strings[] = {
2937 + [DEV_TYPE_AR5312] = "Atheros AR5312",
2938 + [DEV_TYPE_AR2312] = "Atheros AR2312",
2939 + [DEV_TYPE_AR2313] = "Atheros AR2313",
2940 + [DEV_TYPE_AR2315] = "Atheros AR2315",
2941 + [DEV_TYPE_AR2316] = "Atheros AR2316",
2942 + [DEV_TYPE_AR2317] = "Atheros AR2317",
2943 + [DEV_TYPE_UNKNOWN] = "Atheros (unknown)",
2944 +};
2945 +
2946 +const char *get_system_type(void)
2947 +{
2948 + if ((ar231x_devtype >= ARRAY_SIZE(devtype_strings)) ||
2949 + !devtype_strings[ar231x_devtype])
2950 + return devtype_strings[DEV_TYPE_UNKNOWN];
2951 + return devtype_strings[ar231x_devtype];
2952 +}
2953 +
2954 +
2955 +int __init
2956 +ar231x_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
2957 + int irq, void *pdata)
2958 +{
2959 + struct resource *res;
2960 +
2961 + ar231x_eth[nr].dev.platform_data = pdata;
2962 + res = &ar231x_eth[nr].resource[0];
2963 + res->start = base;
2964 + res->end = base + 0x2000 - 1;
2965 + res++;
2966 + res->name = mii_name;
2967 + res->start = mii_base;
2968 + res->end = mii_base + 8 - 1;
2969 + res++;
2970 + res->start = irq;
2971 + res->end = irq;
2972 + return platform_device_register(&ar231x_eth[nr]);
2973 +}
2974 +
2975 +void __init
2976 +ar231x_serial_setup(u32 mapbase, int irq, unsigned int uartclk)
2977 +{
2978 + struct uart_port s;
2979 +
2980 + memset(&s, 0, sizeof(s));
2981 +
2982 + s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP;
2983 + s.iotype = UPIO_MEM32;
2984 + s.irq = irq;
2985 + s.regshift = 2;
2986 + s.mapbase = mapbase;
2987 + s.uartclk = uartclk;
2988 +
2989 + early_serial_setup(&s);
2990 +}
2991 +
2992 +int __init
2993 +ar231x_add_wmac(int nr, u32 base, int irq)
2994 +{
2995 + struct resource *res;
2996 +
2997 + ar231x_wmac[nr].dev.platform_data = &ar231x_board;
2998 + res = &ar231x_wmac[nr].resource[0];
2999 + res->start = base;
3000 + res->end = base + 0x10000 - 1;
3001 + res++;
3002 + res->start = irq;
3003 + res->end = irq;
3004 + return platform_device_register(&ar231x_wmac[nr]);
3005 +}
3006 +
3007 +static int __init ar231x_register_devices(void)
3008 +{
3009 + ar5312_init_devices();
3010 + ar2315_init_devices();
3011 +
3012 + return 0;
3013 +}
3014 +
3015 +device_initcall(ar231x_register_devices);