4cc0246e8555b53573e68a8ed20573f3d8eaa4fa
[openwrt/openwrt.git] / target / linux / atheros / patches-3.14 / 100-board.patch
1 --- a/arch/mips/Kconfig
2 +++ b/arch/mips/Kconfig
3 @@ -144,6 +144,19 @@ config BCM63XX
4 help
5 Support for BCM63XX based boards
6
7 +config ATHEROS_AR231X
8 + bool "Atheros 231x/531x SoC support"
9 + select CEVT_R4K
10 + select CSRC_R4K
11 + select DMA_NONCOHERENT
12 + select IRQ_CPU
13 + select SYS_HAS_CPU_MIPS32_R1
14 + select SYS_SUPPORTS_BIG_ENDIAN
15 + select SYS_SUPPORTS_32BIT_KERNEL
16 + select ARCH_REQUIRE_GPIOLIB
17 + help
18 + Support for AR231x and AR531x based boards
19 +
20 config MIPS_COBALT
21 bool "Cobalt Server"
22 select CEVT_R4K
23 @@ -795,6 +808,7 @@ config NLM_XLP_BOARD
24
25 endchoice
26
27 +source "arch/mips/ar231x/Kconfig"
28 source "arch/mips/alchemy/Kconfig"
29 source "arch/mips/ath79/Kconfig"
30 source "arch/mips/bcm47xx/Kconfig"
31 --- a/arch/mips/Kbuild.platforms
32 +++ b/arch/mips/Kbuild.platforms
33 @@ -6,6 +6,7 @@ platforms += ath79
34 platforms += bcm47xx
35 platforms += bcm63xx
36 platforms += cavium-octeon
37 +platforms += ar231x
38 platforms += cobalt
39 platforms += dec
40 platforms += emma
41 --- /dev/null
42 +++ b/arch/mips/ar231x/Platform
43 @@ -0,0 +1,6 @@
44 +#
45 +# Atheros AR531X/AR231X WiSoC
46 +#
47 +platform-$(CONFIG_ATHEROS_AR231X) += ar231x/
48 +cflags-$(CONFIG_ATHEROS_AR231X) += -I$(srctree)/arch/mips/include/asm/mach-ar231x
49 +load-$(CONFIG_ATHEROS_AR231X) += 0xffffffff80041000
50 --- /dev/null
51 +++ b/arch/mips/ar231x/Kconfig
52 @@ -0,0 +1,9 @@
53 +config ATHEROS_AR5312
54 + bool "Atheros 5312/2312+ support"
55 + depends on ATHEROS_AR231X
56 + default y
57 +
58 +config ATHEROS_AR2315
59 + bool "Atheros 2315+ support"
60 + depends on ATHEROS_AR231X
61 + default y
62 --- /dev/null
63 +++ b/arch/mips/ar231x/Makefile
64 @@ -0,0 +1,13 @@
65 +#
66 +# This file is subject to the terms and conditions of the GNU General Public
67 +# License. See the file "COPYING" in the main directory of this archive
68 +# for more details.
69 +#
70 +# Copyright (C) 2006 FON Technology, SL.
71 +# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
72 +# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
73 +#
74 +
75 +obj-y += board.o prom.o devices.o
76 +obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o
77 +obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o
78 --- /dev/null
79 +++ b/arch/mips/ar231x/board.c
80 @@ -0,0 +1,229 @@
81 +/*
82 + * This file is subject to the terms and conditions of the GNU General Public
83 + * License. See the file "COPYING" in the main directory of this archive
84 + * for more details.
85 + *
86 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
87 + * Copyright (C) 2006 FON Technology, SL.
88 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
89 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
90 + */
91 +
92 +#include <generated/autoconf.h>
93 +#include <linux/init.h>
94 +#include <linux/module.h>
95 +#include <linux/types.h>
96 +#include <linux/string.h>
97 +#include <linux/platform_device.h>
98 +#include <linux/kernel.h>
99 +#include <linux/random.h>
100 +#include <linux/etherdevice.h>
101 +#include <linux/irq.h>
102 +#include <linux/io.h>
103 +#include <asm/irq_cpu.h>
104 +#include <asm/reboot.h>
105 +#include <asm/bootinfo.h>
106 +#include <asm/time.h>
107 +
108 +#include <ar231x_platform.h>
109 +#include "devices.h"
110 +#include "ar5312.h"
111 +#include "ar2315.h"
112 +
113 +void (*ar231x_irq_dispatch)(void);
114 +
115 +static inline bool check_radio_magic(u8 *addr)
116 +{
117 + addr += 0x7a; /* offset for flash magic */
118 + return (addr[0] == 0x5a) && (addr[1] == 0xa5);
119 +}
120 +
121 +static inline bool check_notempty(u8 *addr)
122 +{
123 + return *(u32 *)addr != 0xffffffff;
124 +}
125 +
126 +static inline bool check_board_data(u8 *flash_limit, u8 *addr, bool broken)
127 +{
128 + /* config magic found */
129 + if (*((u32 *)addr) == AR231X_BD_MAGIC)
130 + return true;
131 +
132 + if (!broken)
133 + return false;
134 +
135 + if (check_radio_magic(addr + 0xf8))
136 + ar231x_board.radio = addr + 0xf8;
137 + if ((addr < flash_limit + 0x10000) &&
138 + check_radio_magic(addr + 0x10000))
139 + ar231x_board.radio = addr + 0x10000;
140 +
141 + if (ar231x_board.radio) {
142 + /* broken board data detected, use radio data to find the
143 + * offset, user will fix this */
144 + return true;
145 + }
146 +
147 + return false;
148 +}
149 +
150 +static u8 * __init find_board_config(u8 *flash_limit, bool broken)
151 +{
152 + u8 *addr;
153 + u8 *begin = flash_limit - 0x1000;
154 + u8 *end = flash_limit - 0x30000;
155 +
156 + for (addr = begin; addr >= end; addr -= 0x1000)
157 + if (check_board_data(flash_limit, addr, broken))
158 + return addr;
159 +
160 + return NULL;
161 +}
162 +
163 +static u8 * __init find_radio_config(u8 *flash_limit, u8 *bcfg)
164 +{
165 + u8 *rcfg, *begin, *end;
166 +
167 + /*
168 + * Now find the start of Radio Configuration data, using heuristics:
169 + * Search forward from Board Configuration data by 0x1000 bytes
170 + * at a time until we find non-0xffffffff.
171 + */
172 + begin = bcfg + 0x1000;
173 + end = flash_limit;
174 + for (rcfg = begin; rcfg < end; rcfg += 0x1000)
175 + if (check_notempty(rcfg) && check_radio_magic(rcfg))
176 + return rcfg;
177 +
178 + /* AR2316 relocates radio config to new location */
179 + begin = bcfg + 0xf8;
180 + end = flash_limit - 0x1000 + 0xf8;
181 + for (rcfg = begin; rcfg < end; rcfg += 0x1000)
182 + if (check_notempty(rcfg) && check_radio_magic(rcfg))
183 + return rcfg;
184 +
185 + pr_warn("WARNING: Could not find Radio Configuration data\n");
186 +
187 + return NULL;
188 +}
189 +
190 +int __init ar231x_find_config(u8 *flash_limit)
191 +{
192 + struct ar231x_boarddata *config;
193 + unsigned int rcfg_size;
194 + int broken_boarddata = 0;
195 + u8 *bcfg, *rcfg;
196 + u8 *board_data;
197 + u8 *radio_data;
198 + u8 *mac_addr;
199 + u32 offset;
200 +
201 + ar231x_board.config = NULL;
202 + ar231x_board.radio = NULL;
203 + /* Copy the board and radio data to RAM, because accessing the mapped
204 + * memory of the flash directly after booting is not safe */
205 +
206 + /* Try to find valid board and radio data */
207 + bcfg = find_board_config(flash_limit, false);
208 +
209 + /* If that fails, try to at least find valid radio data */
210 + if (!bcfg) {
211 + bcfg = find_board_config(flash_limit, true);
212 + broken_boarddata = 1;
213 + }
214 +
215 + if (!bcfg) {
216 + pr_warn("WARNING: No board configuration data found!\n");
217 + return -ENODEV;
218 + }
219 +
220 + board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
221 + ar231x_board.config = (struct ar231x_boarddata *)board_data;
222 + memcpy(board_data, bcfg, 0x100);
223 + if (broken_boarddata) {
224 + pr_warn("WARNING: broken board data detected\n");
225 + config = ar231x_board.config;
226 + if (is_zero_ether_addr(config->enet0_mac)) {
227 + pr_info("Fixing up empty mac addresses\n");
228 + config->reset_config_gpio = 0xffff;
229 + config->sys_led_gpio = 0xffff;
230 + random_ether_addr(config->wlan0_mac);
231 + config->wlan0_mac[0] &= ~0x06;
232 + random_ether_addr(config->enet0_mac);
233 + random_ether_addr(config->enet1_mac);
234 + }
235 + }
236 +
237 + /* Radio config starts 0x100 bytes after board config, regardless
238 + * of what the physical layout on the flash chip looks like */
239 +
240 + if (ar231x_board.radio)
241 + rcfg = (u8 *)ar231x_board.radio;
242 + else
243 + rcfg = find_radio_config(flash_limit, bcfg);
244 +
245 + if (!rcfg)
246 + return -ENODEV;
247 +
248 + radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
249 + ar231x_board.radio = radio_data;
250 + offset = radio_data - board_data;
251 + pr_info("Radio config found at offset 0x%x (0x%x)\n", rcfg - bcfg,
252 + offset);
253 + rcfg_size = BOARD_CONFIG_BUFSZ - offset;
254 + memcpy(radio_data, rcfg, rcfg_size);
255 +
256 + mac_addr = &radio_data[0x1d * 2];
257 + if (is_broadcast_ether_addr(mac_addr)) {
258 + pr_info("Radio MAC is blank; using board-data\n");
259 + ether_addr_copy(mac_addr, ar231x_board.config->wlan0_mac);
260 + }
261 +
262 + return 0;
263 +}
264 +
265 +static void ar231x_halt(void)
266 +{
267 + local_irq_disable();
268 + while (1)
269 + ;
270 +}
271 +
272 +void __init plat_mem_setup(void)
273 +{
274 + _machine_halt = ar231x_halt;
275 + pm_power_off = ar231x_halt;
276 +
277 + ar5312_plat_setup();
278 + ar2315_plat_setup();
279 +
280 + /* Disable data watchpoints */
281 + write_c0_watchlo0(0);
282 +}
283 +
284 +asmlinkage void plat_irq_dispatch(void)
285 +{
286 + ar231x_irq_dispatch();
287 +}
288 +
289 +void __init plat_time_init(void)
290 +{
291 + ar5312_time_init();
292 + ar2315_time_init();
293 +}
294 +
295 +unsigned int __cpuinit get_c0_compare_int(void)
296 +{
297 + return CP0_LEGACY_COMPARE_IRQ;
298 +}
299 +
300 +void __init arch_init_irq(void)
301 +{
302 + clear_c0_status(ST0_IM);
303 + mips_cpu_irq_init();
304 +
305 + /* Initialize interrupt controllers */
306 + ar5312_irq_init();
307 + ar2315_irq_init();
308 +}
309 +
310 --- /dev/null
311 +++ b/arch/mips/ar231x/prom.c
312 @@ -0,0 +1,37 @@
313 +/*
314 + * This file is subject to the terms and conditions of the GNU General Public
315 + * License. See the file "COPYING" in the main directory of this archive
316 + * for more details.
317 + *
318 + * Copyright MontaVista Software Inc
319 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
320 + * Copyright (C) 2006 FON Technology, SL.
321 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
322 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
323 + */
324 +
325 +/*
326 + * Prom setup file for ar231x
327 + */
328 +
329 +#include <linux/init.h>
330 +#include <generated/autoconf.h>
331 +#include <linux/kernel.h>
332 +#include <linux/string.h>
333 +#include <linux/mm.h>
334 +#include <linux/bootmem.h>
335 +
336 +#include <asm/bootinfo.h>
337 +#include <asm/addrspace.h>
338 +#include "ar5312.h"
339 +#include "ar2315.h"
340 +
341 +void __init prom_init(void)
342 +{
343 + ar5312_prom_init();
344 + ar2315_prom_init();
345 +}
346 +
347 +void __init prom_free_prom_memory(void)
348 +{
349 +}
350 --- /dev/null
351 +++ b/arch/mips/include/asm/mach-ar231x/ar231x_platform.h
352 @@ -0,0 +1,85 @@
353 +#ifndef __ASM_MACH_AR231X_PLATFORM_H
354 +#define __ASM_MACH_AR231X_PLATFORM_H
355 +
356 +#include <linux/etherdevice.h>
357 +
358 +/*
359 + * This is board-specific data that is stored in a "fixed" location in flash.
360 + * It is shared across operating systems, so it should not be changed lightly.
361 + * The main reason we need it is in order to extract the ethernet MAC
362 + * address(es).
363 + */
364 +struct ar231x_boarddata {
365 + u32 magic; /* board data is valid */
366 +#define AR231X_BD_MAGIC 0x35333131 /* "5311", for all 531x/231x platforms */
367 + u16 cksum; /* checksum (starting with BD_REV 2) */
368 + u16 rev; /* revision of this struct */
369 +#define BD_REV 4
370 + char board_name[64]; /* Name of board */
371 + u16 major; /* Board major number */
372 + u16 minor; /* Board minor number */
373 + u32 flags; /* Board configuration */
374 +#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
375 +#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
376 +#define BD_UART1 0x00000004 /* UART1 is stuffed */
377 +#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
378 +#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
379 +#define BD_SYSLED 0x00000020 /* System LED stuffed */
380 +#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
381 +#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
382 +#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
383 +#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
384 +#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ mem_cap for testing */
385 +#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
386 +#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
387 +#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
388 +#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
389 +#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
390 +#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
391 +#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
392 + u16 reset_config_gpio; /* Reset factory GPIO pin */
393 + u16 sys_led_gpio; /* System LED GPIO pin */
394 +
395 + u32 cpu_freq; /* CPU core frequency in Hz */
396 + u32 sys_freq; /* System frequency in Hz */
397 + u32 cnt_freq; /* Calculated C0_COUNT frequency */
398 +
399 + u8 wlan0_mac[ETH_ALEN];
400 + u8 enet0_mac[ETH_ALEN];
401 + u8 enet1_mac[ETH_ALEN];
402 +
403 + u16 pci_id; /* Pseudo PCIID for common code */
404 + u16 mem_cap; /* cap bank1 in MB */
405 +
406 + /* version 3 */
407 + u8 wlan1_mac[ETH_ALEN]; /* (ar5212) */
408 +};
409 +
410 +#define BOARD_CONFIG_BUFSZ 0x1000
411 +
412 +/*
413 + * Platform device information for the Wireless MAC
414 + */
415 +struct ar231x_board_config {
416 + u16 devid;
417 +
418 + /* board config data */
419 + struct ar231x_boarddata *config;
420 +
421 + /* radio calibration data */
422 + const char *radio;
423 +};
424 +
425 +/*
426 + * Platform device information for the Ethernet MAC
427 + */
428 +struct ar231x_eth {
429 + void (*reset_set)(u32);
430 + void (*reset_clear)(u32);
431 + u32 reset_mac;
432 + u32 reset_phy;
433 + struct ar231x_board_config *config;
434 + char *macaddr;
435 +};
436 +
437 +#endif /* __ASM_MACH_AR231X_PLATFORM_H */
438 --- /dev/null
439 +++ b/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h
440 @@ -0,0 +1,84 @@
441 +/*
442 + * Atheros AR231x/AR531x SoC specific CPU feature overrides
443 + *
444 + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
445 + *
446 + * This file was derived from: include/asm-mips/cpu-features.h
447 + * Copyright (C) 2003, 2004 Ralf Baechle
448 + * Copyright (C) 2004 Maciej W. Rozycki
449 + *
450 + * This program is free software; you can redistribute it and/or modify it
451 + * under the terms of the GNU General Public License version 2 as published
452 + * by the Free Software Foundation.
453 + *
454 + */
455 +#ifndef __ASM_MACH_AR231X_CPU_FEATURE_OVERRIDES_H
456 +#define __ASM_MACH_AR231X_CPU_FEATURE_OVERRIDES_H
457 +
458 +/*
459 + * The Atheros AR531x/AR231x SoCs have MIPS 4Kc/4KEc core.
460 + */
461 +#define cpu_has_tlb 1
462 +#define cpu_has_4kex 1
463 +#define cpu_has_3k_cache 0
464 +#define cpu_has_4k_cache 1
465 +#define cpu_has_tx39_cache 0
466 +#define cpu_has_sb1_cache 0
467 +#define cpu_has_fpu 0
468 +#define cpu_has_32fpr 0
469 +#define cpu_has_counter 1
470 +/* #define cpu_has_watch ? */
471 +/* #define cpu_has_divec ? */
472 +/* #define cpu_has_vce ? */
473 +/* #define cpu_has_cache_cdex_p ? */
474 +/* #define cpu_has_cache_cdex_s ? */
475 +/* #define cpu_has_prefetch ? */
476 +/* #define cpu_has_mcheck ? */
477 +#define cpu_has_ejtag 1
478 +
479 +#if !defined(CONFIG_ATHEROS_AR5312)
480 +# define cpu_has_llsc 1
481 +#else
482 +/*
483 + * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
484 + * ll/sc instructions.
485 + */
486 +# define cpu_has_llsc 0
487 +#endif
488 +
489 +#define cpu_has_mips16 0
490 +#define cpu_has_mdmx 0
491 +#define cpu_has_mips3d 0
492 +#define cpu_has_smartmips 0
493 +
494 +/* #define cpu_has_vtag_icache ? */
495 +/* #define cpu_has_dc_aliases ? */
496 +/* #define cpu_has_ic_fills_f_dc ? */
497 +/* #define cpu_has_pindexed_dcache ? */
498 +
499 +/* #define cpu_icache_snoops_remote_store ? */
500 +
501 +#define cpu_has_mips32r1 1
502 +
503 +#if !defined(CONFIG_ATHEROS_AR5312)
504 +# define cpu_has_mips32r2 1
505 +#endif
506 +
507 +#define cpu_has_mips64r1 0
508 +#define cpu_has_mips64r2 0
509 +
510 +#define cpu_has_dsp 0
511 +#define cpu_has_mipsmt 0
512 +
513 +/* #define cpu_has_nofpuex ? */
514 +#define cpu_has_64bits 0
515 +#define cpu_has_64bit_zero_reg 0
516 +#define cpu_has_64bit_gp_regs 0
517 +#define cpu_has_64bit_addresses 0
518 +
519 +/* #define cpu_has_inclusive_pcaches ? */
520 +
521 +/* #define cpu_dcache_line_size() ? */
522 +/* #define cpu_icache_line_size() ? */
523 +
524 +#endif /* __ASM_MACH_AR231X_CPU_FEATURE_OVERRIDES_H */
525 --- /dev/null
526 +++ b/arch/mips/include/asm/mach-ar231x/dma-coherence.h
527 @@ -0,0 +1,76 @@
528 +/*
529 + * This file is subject to the terms and conditions of the GNU General Public
530 + * License. See the file "COPYING" in the main directory of this archive
531 + * for more details.
532 + *
533 + * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
534 + * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
535 + *
536 + */
537 +#ifndef __ASM_MACH_AR231X_DMA_COHERENCE_H
538 +#define __ASM_MACH_AR231X_DMA_COHERENCE_H
539 +
540 +#include <linux/device.h>
541 +#include <ar2315_regs.h>
542 +
543 +static inline dma_addr_t ar231x_dev_offset(struct device *dev)
544 +{
545 +#ifdef CONFIG_PCI
546 + extern struct bus_type pci_bus_type;
547 +
548 + if (dev && dev->bus == &pci_bus_type)
549 + return AR2315_PCI_HOST_SDRAM_BASEADDR;
550 +#endif
551 + return 0;
552 +}
553 +
554 +static inline dma_addr_t
555 +plat_map_dma_mem(struct device *dev, void *addr, size_t size)
556 +{
557 + return virt_to_phys(addr) + ar231x_dev_offset(dev);
558 +}
559 +
560 +static inline dma_addr_t
561 +plat_map_dma_mem_page(struct device *dev, struct page *page)
562 +{
563 + return page_to_phys(page) + ar231x_dev_offset(dev);
564 +}
565 +
566 +static inline unsigned long
567 +plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
568 +{
569 + return dma_addr - ar231x_dev_offset(dev);
570 +}
571 +
572 +static inline void
573 +plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, size_t size,
574 + enum dma_data_direction direction)
575 +{
576 +}
577 +
578 +static inline int plat_dma_supported(struct device *dev, u64 mask)
579 +{
580 + return 1;
581 +}
582 +
583 +static inline void plat_extra_sync_for_device(struct device *dev)
584 +{
585 +}
586 +
587 +static inline int plat_dma_mapping_error(struct device *dev,
588 + dma_addr_t dma_addr)
589 +{
590 + return 0;
591 +}
592 +
593 +static inline int plat_device_is_coherent(struct device *dev)
594 +{
595 +#ifdef CONFIG_DMA_COHERENT
596 + return 1;
597 +#endif
598 +#ifdef CONFIG_DMA_NONCOHERENT
599 + return 0;
600 +#endif
601 +}
602 +
603 +#endif /* __ASM_MACH_AR231X_DMA_COHERENCE_H */
604 --- /dev/null
605 +++ b/arch/mips/include/asm/mach-ar231x/gpio.h
606 @@ -0,0 +1,30 @@
607 +#ifndef __ASM_MACH_AR231X_GPIO_H
608 +#define __ASM_MACH_AR231X_GPIO_H
609 +
610 +#include <ar231x.h>
611 +
612 +#define gpio_get_value __gpio_get_value
613 +#define gpio_set_value __gpio_set_value
614 +#define gpio_cansleep __gpio_cansleep
615 +
616 +/*
617 + * Wrappers for the generic GPIO layer
618 + */
619 +
620 +/* not sure if these are used? */
621 +
622 +/* Returns IRQ to attach for gpio. Unchecked function */
623 +static inline int gpio_to_irq(unsigned gpio)
624 +{
625 + return AR231X_GPIO_IRQ(gpio);
626 +}
627 +
628 +/* Returns gpio for IRQ attached. Unchecked function */
629 +static inline int irq_to_gpio(unsigned irq)
630 +{
631 + return irq - AR231X_GPIO_IRQ(0);
632 +}
633 +
634 +#include <asm-generic/gpio.h> /* cansleep wrappers */
635 +
636 +#endif /* __ASM_MACH_AR231X_GPIO_H */
637 --- /dev/null
638 +++ b/arch/mips/include/asm/mach-ar231x/reset.h
639 @@ -0,0 +1,6 @@
640 +#ifndef __ASM_MACH_AR231X_RESET_H
641 +#define __ASM_MACH_AR231X_RESET_H
642 +
643 +void ar231x_disable_reset_button(void);
644 +
645 +#endif /* __ASM_MACH_AR231X_RESET_H */
646 --- /dev/null
647 +++ b/arch/mips/include/asm/mach-ar231x/war.h
648 @@ -0,0 +1,25 @@
649 +/*
650 + * This file is subject to the terms and conditions of the GNU General Public
651 + * License. See the file "COPYING" in the main directory of this archive
652 + * for more details.
653 + *
654 + * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
655 + */
656 +#ifndef __ASM_MACH_AR231X_WAR_H
657 +#define __ASM_MACH_AR231X_WAR_H
658 +
659 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
660 +#define R4600_V1_HIT_CACHEOP_WAR 0
661 +#define R4600_V2_HIT_CACHEOP_WAR 0
662 +#define R5432_CP0_INTERRUPT_WAR 0
663 +#define BCM1250_M3_WAR 0
664 +#define SIBYTE_1956_WAR 0
665 +#define MIPS4K_ICACHE_REFILL_WAR 0
666 +#define MIPS_CACHE_SYNC_WAR 0
667 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
668 +#define RM9000_CDEX_SMP_WAR 0
669 +#define ICACHE_REFILLS_WORKAROUND_WAR 0
670 +#define R10000_LLSC_WAR 0
671 +#define MIPS34K_MISSED_ITLB_WAR 0
672 +
673 +#endif /* __ASM_MACH_AR231X_WAR_H */
674 --- /dev/null
675 +++ b/arch/mips/include/asm/mach-ar231x/ar2315_regs.h
676 @@ -0,0 +1,631 @@
677 +/*
678 + * Register definitions for AR2315+
679 + *
680 + * This file is subject to the terms and conditions of the GNU General Public
681 + * License. See the file "COPYING" in the main directory of this archive
682 + * for more details.
683 + *
684 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
685 + * Copyright (C) 2006 FON Technology, SL.
686 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
687 + * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
688 + */
689 +
690 +#ifndef __ASM_MACH_AR231X_AR2315_REGS_H
691 +#define __ASM_MACH_AR231X_AR2315_REGS_H
692 +
693 +/*
694 + * IRQs
695 + */
696 +#define AR2315_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
697 +#define AR2315_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
698 +#define AR2315_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
699 +#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
700 +#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
701 +
702 +/*
703 + * Miscellaneous interrupts, which share IP2.
704 + */
705 +#define AR2315_MISC_IRQ_NONE (AR231X_MISC_IRQ_BASE+0)
706 +#define AR2315_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+1)
707 +#define AR2315_MISC_IRQ_I2C_RSVD (AR231X_MISC_IRQ_BASE+2)
708 +#define AR2315_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+3)
709 +#define AR2315_MISC_IRQ_AHB (AR231X_MISC_IRQ_BASE+4)
710 +#define AR2315_MISC_IRQ_APB (AR231X_MISC_IRQ_BASE+5)
711 +#define AR2315_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+6)
712 +#define AR2315_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+7)
713 +#define AR2315_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+8)
714 +#define AR2315_MISC_IRQ_IR_RSVD (AR231X_MISC_IRQ_BASE+9)
715 +#define AR2315_MISC_IRQ_COUNT 10
716 +
717 +/*
718 + * PCI interrupts, which share IP5
719 + * Keep ordered according to AR2315_PCI_INT_XXX bits
720 + */
721 +#define AR2315_PCI_IRQ_BASE 0x50
722 +#define AR2315_PCI_IRQ_EXT (AR2315_PCI_IRQ_BASE+0)
723 +#define AR2315_PCI_IRQ_ABORT (AR2315_PCI_IRQ_BASE+1)
724 +#define AR2315_PCI_IRQ_COUNT 2
725 +#define AR2315_PCI_IRQ_SHIFT 25 /* in AR2315_PCI_INT_STATUS */
726 +
727 +/*
728 + * Address map
729 + */
730 +#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */
731 +#define AR2315_WLAN0 0x10000000 /* Wireless MMR */
732 +#define AR2315_PCI 0x10100000 /* PCI MMR */
733 +#define AR2315_SDRAMCTL 0x10300000 /* SDRAM MMR */
734 +#define AR2315_LOCAL 0x10400000 /* LOCAL BUS MMR */
735 +#define AR2315_ENET0 0x10500000 /* ETHERNET MMR */
736 +#define AR2315_DSLBASE 0x11000000 /* RESET CONTROL MMR */
737 +#define AR2315_UART0 0x11100000 /* UART MMR */
738 +#define AR2315_SPI_MMR 0x11300000 /* SPI FLASH MMR */
739 +#define AR2315_PCIEXT 0x80000000 /* pci external */
740 +#define AR2315_PCIEXT_SZ 0x40000000
741 +
742 +/* MII registers offset inside Ethernet MMR region */
743 +#define AR2315_ENET0_MII (AR2315_ENET0 + 0x14)
744 +
745 +/*
746 + * Cold reset register
747 + */
748 +#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000)
749 +
750 +#define AR2315_RESET_COLD_AHB 0x00000001
751 +#define AR2315_RESET_COLD_APB 0x00000002
752 +#define AR2315_RESET_COLD_CPU 0x00000004
753 +#define AR2315_RESET_COLD_CPUWARM 0x00000008
754 +#define AR2315_RESET_SYSTEM \
755 + (RESET_COLD_CPU |\
756 + RESET_COLD_APB |\
757 + RESET_COLD_AHB) /* full system */
758 +#define AR2317_RESET_SYSTEM 0x00000010
759 +
760 +/*
761 + * Reset register
762 + */
763 +#define AR2315_RESET (AR2315_DSLBASE + 0x0004)
764 +
765 +/* warm reset WLAN0 MAC */
766 +#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001
767 +/* warm reset WLAN0 BaseBand */
768 +#define AR2315_RESET_WARM_WLAN0_BB 0x00000002
769 +/* warm reset MPEG-TS */
770 +#define AR2315_RESET_MPEGTS_RSVD 0x00000004
771 +/* warm reset PCI ahb/dma */
772 +#define AR2315_RESET_PCIDMA 0x00000008
773 +/* warm reset memory controller */
774 +#define AR2315_RESET_MEMCTL 0x00000010
775 +/* warm reset local bus */
776 +#define AR2315_RESET_LOCAL 0x00000020
777 +/* warm reset I2C bus */
778 +#define AR2315_RESET_I2C_RSVD 0x00000040
779 +/* warm reset SPI interface */
780 +#define AR2315_RESET_SPI 0x00000080
781 +/* warm reset UART0 */
782 +#define AR2315_RESET_UART0 0x00000100
783 +/* warm reset IR interface */
784 +#define AR2315_RESET_IR_RSVD 0x00000200
785 +/* cold reset ENET0 phy */
786 +#define AR2315_RESET_EPHY0 0x00000400
787 +/* cold reset ENET0 mac */
788 +#define AR2315_RESET_ENET0 0x00000800
789 +
790 +/*
791 + * AHB master arbitration control
792 + */
793 +#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008)
794 +
795 +/* CPU, default */
796 +#define AR2315_ARB_CPU 0x00000001
797 +/* WLAN */
798 +#define AR2315_ARB_WLAN 0x00000002
799 +/* MPEG-TS */
800 +#define AR2315_ARB_MPEGTS_RSVD 0x00000004
801 +/* LOCAL */
802 +#define AR2315_ARB_LOCAL 0x00000008
803 +/* PCI */
804 +#define AR2315_ARB_PCI 0x00000010
805 +/* Ethernet */
806 +#define AR2315_ARB_ETHERNET 0x00000020
807 +/* retry policy, debug only */
808 +#define AR2315_ARB_RETRY 0x00000100
809 +
810 +/*
811 + * Config Register
812 + */
813 +#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c)
814 +
815 +/* EC - AHB bridge endianess */
816 +#define AR2315_CONFIG_AHB 0x00000001
817 +/* WLAN byteswap */
818 +#define AR2315_CONFIG_WLAN 0x00000002
819 +/* MPEG-TS byteswap */
820 +#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004
821 +/* PCI byteswap */
822 +#define AR2315_CONFIG_PCI 0x00000008
823 +/* Memory controller endianess */
824 +#define AR2315_CONFIG_MEMCTL 0x00000010
825 +/* Local bus byteswap */
826 +#define AR2315_CONFIG_LOCAL 0x00000020
827 +/* Ethernet byteswap */
828 +#define AR2315_CONFIG_ETHERNET 0x00000040
829 +
830 +/* CPU write buffer merge */
831 +#define AR2315_CONFIG_MERGE 0x00000200
832 +/* CPU big endian */
833 +#define AR2315_CONFIG_CPU 0x00000400
834 +#define AR2315_CONFIG_PCIAHB 0x00000800
835 +#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
836 +/* SPI byteswap */
837 +#define AR2315_CONFIG_SPI 0x00008000
838 +#define AR2315_CONFIG_CPU_DRAM 0x00010000
839 +#define AR2315_CONFIG_CPU_PCI 0x00020000
840 +#define AR2315_CONFIG_CPU_MMR 0x00040000
841 +#define AR2315_CONFIG_BIG 0x00000400
842 +
843 +/*
844 + * NMI control
845 + */
846 +#define AR2315_NMI_CTL (AR2315_DSLBASE + 0x0010)
847 +
848 +#define AR2315_NMI_EN 1
849 +
850 +/*
851 + * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR231X 1.0).
852 + */
853 +#define AR2315_SREV (AR2315_DSLBASE + 0x0014)
854 +
855 +#define AR2315_REV_MAJ 0x00f0
856 +#define AR2315_REV_MAJ_S 4
857 +#define AR2315_REV_MIN 0x000f
858 +#define AR2315_REV_MIN_S 0
859 +#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN)
860 +
861 +/*
862 + * Interface Enable
863 + */
864 +#define AR2315_IF_CTL (AR2315_DSLBASE + 0x0018)
865 +
866 +#define AR2315_IF_MASK 0x00000007
867 +#define AR2315_IF_DISABLED 0
868 +#define AR2315_IF_PCI 1
869 +#define AR2315_IF_TS_LOCAL 2
870 +/* only for emulation with separate pins */
871 +#define AR2315_IF_ALL 3
872 +#define AR2315_IF_LOCAL_HOST 0x00000008
873 +#define AR2315_IF_PCI_HOST 0x00000010
874 +#define AR2315_IF_PCI_INTR 0x00000020
875 +#define AR2315_IF_PCI_CLK_MASK 0x00030000
876 +#define AR2315_IF_PCI_CLK_INPUT 0
877 +#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
878 +#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
879 +#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
880 +#define AR2315_IF_PCI_CLK_SHIFT 16
881 +
882 +/*
883 + * APB Interrupt control
884 + */
885 +
886 +#define AR2315_ISR (AR2315_DSLBASE + 0x0020)
887 +#define AR2315_IMR (AR2315_DSLBASE + 0x0024)
888 +#define AR2315_GISR (AR2315_DSLBASE + 0x0028)
889 +
890 +#define AR2315_ISR_UART0 0x0001 /* high speed UART */
891 +#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */
892 +#define AR2315_ISR_SPI 0x0004 /* SPI bus */
893 +#define AR2315_ISR_AHB 0x0008 /* AHB error */
894 +#define AR2315_ISR_APB 0x0010 /* APB error */
895 +#define AR2315_ISR_TIMER 0x0020 /* timer */
896 +#define AR2315_ISR_GPIO 0x0040 /* GPIO */
897 +#define AR2315_ISR_WD 0x0080 /* watchdog */
898 +#define AR2315_ISR_IR_RSVD 0x0100 /* IR */
899 +
900 +#define AR2315_GISR_MISC 0x0001
901 +#define AR2315_GISR_WLAN0 0x0002
902 +#define AR2315_GISR_MPEGTS_RSVD 0x0004
903 +#define AR2315_GISR_LOCALPCI 0x0008
904 +#define AR2315_GISR_WMACPOLL 0x0010
905 +#define AR2315_GISR_TIMER 0x0020
906 +#define AR2315_GISR_ETHERNET 0x0040
907 +
908 +/*
909 + * Interrupt routing from IO to the processor IP bits
910 + * Define our inter mask and level
911 + */
912 +#define AR2315_INTR_MISCIO SR_IBIT3
913 +#define AR2315_INTR_WLAN0 SR_IBIT4
914 +#define AR2315_INTR_ENET0 SR_IBIT5
915 +#define AR2315_INTR_LOCALPCI SR_IBIT6
916 +#define AR2315_INTR_WMACPOLL SR_IBIT7
917 +#define AR2315_INTR_COMPARE SR_IBIT8
918 +
919 +/*
920 + * Timers
921 + */
922 +#define AR2315_TIMER (AR2315_DSLBASE + 0x0030)
923 +#define AR2315_RELOAD (AR2315_DSLBASE + 0x0034)
924 +#define AR2315_WD (AR2315_DSLBASE + 0x0038)
925 +#define AR2315_WDC (AR2315_DSLBASE + 0x003c)
926 +
927 +#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000
928 +#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */
929 +#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */
930 +
931 +/*
932 + * CPU Performance Counters
933 + */
934 +#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048)
935 +#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c)
936 +
937 +#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */
938 +#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */
939 +#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */
940 +#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */
941 +#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */
942 +#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */
943 +#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */
944 +
945 +#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */
946 +#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */
947 +#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */
948 +#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */
949 +#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */
950 +#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */
951 +#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */
952 +
953 +/*
954 + * AHB Error Reporting.
955 + */
956 +#define AR2315_AHB_ERR0 (AR2315_DSLBASE + 0x0050) /* error */
957 +#define AR2315_AHB_ERR1 (AR2315_DSLBASE + 0x0054) /* haddr */
958 +#define AR2315_AHB_ERR2 (AR2315_DSLBASE + 0x0058) /* hwdata */
959 +#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */
960 +#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */
961 +
962 +#define AHB_ERROR_DET 1 /* AHB Error has been detected, */
963 + /* write 1 to clear all bits in ERR0 */
964 +#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
965 +#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
966 +
967 +#define AR2315_PROCERR_HMAST 0x0000000f
968 +#define AR2315_PROCERR_HMAST_DFLT 0
969 +#define AR2315_PROCERR_HMAST_WMAC 1
970 +#define AR2315_PROCERR_HMAST_ENET 2
971 +#define AR2315_PROCERR_HMAST_PCIENDPT 3
972 +#define AR2315_PROCERR_HMAST_LOCAL 4
973 +#define AR2315_PROCERR_HMAST_CPU 5
974 +#define AR2315_PROCERR_HMAST_PCITGT 6
975 +
976 +#define AR2315_PROCERR_HMAST_S 0
977 +#define AR2315_PROCERR_HWRITE 0x00000010
978 +#define AR2315_PROCERR_HSIZE 0x00000060
979 +#define AR2315_PROCERR_HSIZE_S 5
980 +#define AR2315_PROCERR_HTRANS 0x00000180
981 +#define AR2315_PROCERR_HTRANS_S 7
982 +#define AR2315_PROCERR_HBURST 0x00000e00
983 +#define AR2315_PROCERR_HBURST_S 9
984 +
985 +/*
986 + * Clock Control
987 + */
988 +#define AR2315_PLLC_CTL (AR2315_DSLBASE + 0x0064)
989 +#define AR2315_PLLV_CTL (AR2315_DSLBASE + 0x0068)
990 +#define AR2315_CPUCLK (AR2315_DSLBASE + 0x006c)
991 +#define AR2315_AMBACLK (AR2315_DSLBASE + 0x0070)
992 +#define AR2315_SYNCCLK (AR2315_DSLBASE + 0x0074)
993 +#define AR2315_DSL_SLEEP_CTL (AR2315_DSLBASE + 0x0080)
994 +#define AR2315_DSL_SLEEP_DUR (AR2315_DSLBASE + 0x0084)
995 +
996 +/* PLLc Control fields */
997 +#define PLLC_REF_DIV_M 0x00000003
998 +#define PLLC_REF_DIV_S 0
999 +#define PLLC_FDBACK_DIV_M 0x0000007C
1000 +#define PLLC_FDBACK_DIV_S 2
1001 +#define PLLC_ADD_FDBACK_DIV_M 0x00000080
1002 +#define PLLC_ADD_FDBACK_DIV_S 7
1003 +#define PLLC_CLKC_DIV_M 0x0001c000
1004 +#define PLLC_CLKC_DIV_S 14
1005 +#define PLLC_CLKM_DIV_M 0x00700000
1006 +#define PLLC_CLKM_DIV_S 20
1007 +
1008 +/* CPU CLK Control fields */
1009 +#define CPUCLK_CLK_SEL_M 0x00000003
1010 +#define CPUCLK_CLK_SEL_S 0
1011 +#define CPUCLK_CLK_DIV_M 0x0000000c
1012 +#define CPUCLK_CLK_DIV_S 2
1013 +
1014 +/* AMBA CLK Control fields */
1015 +#define AMBACLK_CLK_SEL_M 0x00000003
1016 +#define AMBACLK_CLK_SEL_S 0
1017 +#define AMBACLK_CLK_DIV_M 0x0000000c
1018 +#define AMBACLK_CLK_DIV_S 2
1019 +
1020 +/*
1021 + * GPIO
1022 + */
1023 +#define AR2315_GPIO_DI (AR2315_DSLBASE + 0x0088)
1024 +#define AR2315_GPIO_DO (AR2315_DSLBASE + 0x0090)
1025 +#define AR2315_GPIO_DIR (AR2315_DSLBASE + 0x0098)
1026 +#define AR2315_GPIO_INT (AR2315_DSLBASE + 0x00a0)
1027 +
1028 +#define AR2315_GPIO_DIR_M(x) (1 << (x)) /* mask for i/o */
1029 +#define AR2315_GPIO_DIR_O(x) (1 << (x)) /* output */
1030 +#define AR2315_GPIO_DIR_I(x) (0) /* input */
1031 +
1032 +#define AR2315_GPIO_INT_S(x) (x) /* interrupt enable */
1033 +#define AR2315_GPIO_INT_M (0x3F) /* mask for int */
1034 +#define AR2315_GPIO_INT_LVL(x) ((x) << 6) /* interrupt level */
1035 +#define AR2315_GPIO_INT_LVL_M ((0x3) << 6) /* mask for int level */
1036 +
1037 +#define AR2315_GPIO_INT_MAX_Y 1 /* Maximum value of Y for
1038 + * AR2315_GPIO_INT_* macros */
1039 +#define AR2315_GPIO_INT_LVL_OFF 0 /* Triggerring off */
1040 +#define AR2315_GPIO_INT_LVL_LOW 1 /* Low Level Triggered */
1041 +#define AR2315_GPIO_INT_LVL_HIGH 2 /* High Level Triggered */
1042 +#define AR2315_GPIO_INT_LVL_EDGE 3 /* Edge Triggered */
1043 +
1044 +#define AR2315_RESET_GPIO 5
1045 +#define AR2315_NUM_GPIO 22
1046 +
1047 +/*
1048 + * PCI Clock Control
1049 + */
1050 +#define AR2315_PCICLK (AR2315_DSLBASE + 0x00a4)
1051 +
1052 +#define AR2315_PCICLK_INPUT_M 0x3
1053 +#define AR2315_PCICLK_INPUT_S 0
1054 +
1055 +#define AR2315_PCICLK_PLLC_CLKM 0
1056 +#define AR2315_PCICLK_PLLC_CLKM1 1
1057 +#define AR2315_PCICLK_PLLC_CLKC 2
1058 +#define AR2315_PCICLK_REF_CLK 3
1059 +
1060 +#define AR2315_PCICLK_DIV_M 0xc
1061 +#define AR2315_PCICLK_DIV_S 2
1062 +
1063 +#define AR2315_PCICLK_IN_FREQ 0
1064 +#define AR2315_PCICLK_IN_FREQ_DIV_6 1
1065 +#define AR2315_PCICLK_IN_FREQ_DIV_8 2
1066 +#define AR2315_PCICLK_IN_FREQ_DIV_10 3
1067 +
1068 +/*
1069 + * Observation Control Register
1070 + */
1071 +#define AR2315_OCR (AR2315_DSLBASE + 0x00b0)
1072 +#define OCR_GPIO0_IRIN 0x0040
1073 +#define OCR_GPIO1_IROUT 0x0080
1074 +#define OCR_GPIO3_RXCLR 0x0200
1075 +
1076 +/*
1077 + * General Clock Control
1078 + */
1079 +
1080 +#define AR2315_MISCCLK (AR2315_DSLBASE + 0x00b4)
1081 +#define MISCCLK_PLLBYPASS_EN 0x00000001
1082 +#define MISCCLK_PROCREFCLK 0x00000002
1083 +
1084 +/*
1085 + * SDRAM Controller
1086 + * - No read or write buffers are included.
1087 + */
1088 +#define AR2315_MEM_CFG (AR2315_SDRAMCTL + 0x00)
1089 +#define AR2315_MEM_CTRL (AR2315_SDRAMCTL + 0x0c)
1090 +#define AR2315_MEM_REF (AR2315_SDRAMCTL + 0x10)
1091 +
1092 +#define SDRAM_DATA_WIDTH_M 0x00006000
1093 +#define SDRAM_DATA_WIDTH_S 13
1094 +
1095 +#define SDRAM_COL_WIDTH_M 0x00001E00
1096 +#define SDRAM_COL_WIDTH_S 9
1097 +
1098 +#define SDRAM_ROW_WIDTH_M 0x000001E0
1099 +#define SDRAM_ROW_WIDTH_S 5
1100 +
1101 +#define SDRAM_BANKADDR_BITS_M 0x00000018
1102 +#define SDRAM_BANKADDR_BITS_S 3
1103 +
1104 +/*
1105 + * PCI Bus Interface Registers
1106 + */
1107 +#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008)
1108 +#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1109 +
1110 +#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c)
1111 +#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
1112 +#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* mem or config cycles */
1113 +#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
1114 +#define AR2315_PCIMISC_RST_MODE 0x00000030
1115 +#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
1116 +#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
1117 +#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
1118 +#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
1119 +#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
1120 +#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
1121 +#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
1122 +#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache
1123 + * disable */
1124 +
1125 +#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010)
1126 +
1127 +#define AR2315_PCI_UNCACHE_CFG (AR2315_PCI + 0x0014)
1128 +
1129 +#define AR2315_PCI_IN_EN (AR2315_PCI + 0x0100)
1130 +#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
1131 +#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
1132 +#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
1133 +#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
1134 +
1135 +#define AR2315_PCI_IN_DIS (AR2315_PCI + 0x0104)
1136 +#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
1137 +#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
1138 +#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
1139 +#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
1140 +
1141 +#define AR2315_PCI_IN_PTR (AR2315_PCI + 0x0200)
1142 +
1143 +#define AR2315_PCI_OUT_EN (AR2315_PCI + 0x0400)
1144 +#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
1145 +
1146 +#define AR2315_PCI_OUT_DIS (AR2315_PCI + 0x0404)
1147 +#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
1148 +
1149 +#define AR2315_PCI_OUT_PTR (AR2315_PCI + 0x0408)
1150 +
1151 +#define AR2315_PCI_ISR (AR2315_PCI + 0x0500) /* write one to clr */
1152 +#define AR2315_PCI_INT_TX 0x00000001 /* Desc In Completed */
1153 +#define AR2315_PCI_INT_TXOK 0x00000002 /* Desc In OK */
1154 +#define AR2315_PCI_INT_TXERR 0x00000004 /* Desc In ERR */
1155 +#define AR2315_PCI_INT_TXEOL 0x00000008 /* Desc In End-of-List */
1156 +#define AR2315_PCI_INT_RX 0x00000010 /* Desc Out Completed */
1157 +#define AR2315_PCI_INT_RXOK 0x00000020 /* Desc Out OK */
1158 +#define AR2315_PCI_INT_RXERR 0x00000040 /* Desc Out ERR */
1159 +#define AR2315_PCI_INT_RXEOL 0x00000080 /* Desc Out EOL */
1160 +#define AR2315_PCI_INT_TXOOD 0x00000200 /* Desc In Out-of-Desc */
1161 +#define AR2315_PCI_INT_DESCMASK 0x0000FFFF /* Desc Mask */
1162 +#define AR2315_PCI_INT_EXT 0x02000000 /* Extern PCI INTA */
1163 +#define AR2315_PCI_INT_ABORT 0x04000000 /* PCI bus abort event */
1164 +
1165 +#define AR2315_PCI_IMR (AR2315_PCI + 0x0504) /* mask _PCI_ISR bits */
1166 +
1167 +#define AR2315_PCI_IER (AR2315_PCI + 0x0508) /* global PCI int en */
1168 +#define AR2315_PCI_IER_DISABLE 0x00 /* disable pci interrupts */
1169 +#define AR2315_PCI_IER_ENABLE 0x01 /* enable pci interrupts */
1170 +
1171 +#define AR2315_PCI_HOST_IN_EN (AR2315_PCI + 0x0800)
1172 +#define AR2315_PCI_HOST_IN_DIS (AR2315_PCI + 0x0804)
1173 +#define AR2315_PCI_HOST_IN_PTR (AR2315_PCI + 0x0810)
1174 +#define AR2315_PCI_HOST_OUT_EN (AR2315_PCI + 0x0900)
1175 +#define AR2315_PCI_HOST_OUT_DIS (AR2315_PCI + 0x0904)
1176 +#define AR2315_PCI_HOST_OUT_PTR (AR2315_PCI + 0x0908)
1177 +
1178 +/*
1179 + * Local Bus Interface Registers
1180 + */
1181 +#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000)
1182 +#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
1183 +#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
1184 +#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
1185 +#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
1186 +#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
1187 +#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
1188 +#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
1189 +#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
1190 +#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
1191 +#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
1192 +#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
1193 +#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
1194 +#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
1195 +#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
1196 +#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
1197 +#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
1198 +#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
1199 +#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
1200 +#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
1201 +#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
1202 +#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
1203 +#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */
1204 +#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
1205 +#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
1206 +#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
1207 +
1208 +#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004)
1209 +#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */
1210 +
1211 +#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008)
1212 +#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1213 +
1214 +#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C)
1215 +#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
1216 +#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
1217 +#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
1218 +#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
1219 +#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
1220 +#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80
1221 +#define AR2315_LBM_TIMEOUT_SHFT 7
1222 +#define AR2315_LBM_PORTMUX 0x07000000
1223 +
1224 +#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010)
1225 +
1226 +#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100)
1227 +#define AR2315_LB_TXEN_0 0x01
1228 +#define AR2315_LB_TXEN_1 0x02
1229 +#define AR2315_LB_TXEN_2 0x04
1230 +#define AR2315_LB_TXEN_3 0x08
1231 +
1232 +#define AR2315_LB_TX_CHAIN_DIS (AR2315_LOCAL + 0x0104)
1233 +#define AR2315_LB_TX_DESC_PTR (AR2315_LOCAL + 0x0200)
1234 +
1235 +#define AR2315_LB_RX_CHAIN_EN (AR2315_LOCAL + 0x0400)
1236 +#define AR2315_LB_RXEN 0x01
1237 +
1238 +#define AR2315_LB_RX_CHAIN_DIS (AR2315_LOCAL + 0x0404)
1239 +#define AR2315_LB_RX_DESC_PTR (AR2315_LOCAL + 0x0408)
1240 +
1241 +#define AR2315_LB_INT_STATUS (AR2315_LOCAL + 0x0500)
1242 +#define AR2315_INT_TX_DESC 0x0001
1243 +#define AR2315_INT_TX_OK 0x0002
1244 +#define AR2315_INT_TX_ERR 0x0004
1245 +#define AR2315_INT_TX_EOF 0x0008
1246 +#define AR2315_INT_RX_DESC 0x0010
1247 +#define AR2315_INT_RX_OK 0x0020
1248 +#define AR2315_INT_RX_ERR 0x0040
1249 +#define AR2315_INT_RX_EOF 0x0080
1250 +#define AR2315_INT_TX_TRUNC 0x0100
1251 +#define AR2315_INT_TX_STARVE 0x0200
1252 +#define AR2315_INT_LB_TIMEOUT 0x0400
1253 +#define AR2315_INT_LB_ERR 0x0800
1254 +#define AR2315_INT_MBOX_WR 0x1000
1255 +#define AR2315_INT_MBOX_RD 0x2000
1256 +
1257 +/* Bit definitions for INT MASK are the same as INT_STATUS */
1258 +#define AR2315_LB_INT_MASK (AR2315_LOCAL + 0x0504)
1259 +
1260 +#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508)
1261 +#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600)
1262 +
1263 +/*
1264 + * IR Interface Registers
1265 + */
1266 +#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000)
1267 +
1268 +#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */
1269 +
1270 +#define AR2315_IR_CONTROL (AR2315_IR + 0x0800)
1271 +#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */
1272 +#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */
1273 +#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor */
1274 +#define AR2315_IRCTL_SAMPLECLK_SHFT 1
1275 +#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk div */
1276 +#define AR2315_IRCTL_OUTPUTCLK_SHFT 14
1277 +
1278 +#define AR2315_IR_STATUS (AR2315_IR + 0x0804)
1279 +#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */
1280 +#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */
1281 +
1282 +#define AR2315_IR_CONFIG (AR2315_IR + 0x0808)
1283 +#define AR2315_IRCFG_INVIN 0x00000001 /* invert in polarity */
1284 +#define AR2315_IRCFG_INVOUT 0x00000002 /* invert out polarity */
1285 +#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */
1286 +#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0
1287 +#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100
1288 +#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00
1289 +#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000
1290 +#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000
1291 +#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000
1292 +
1293 +/*
1294 + * We need some arbitrary non-zero value to be programmed to the BAR1 register
1295 + * of PCI host controller to enable DMA. The same value should be used as the
1296 + * offset to calculate the physical address of DMA buffer for PCI devices.
1297 + */
1298 +#define AR2315_PCI_HOST_SDRAM_BASEADDR 0x20000000
1299 +
1300 +/* ??? access BAR */
1301 +#define AR2315_PCI_HOST_MBAR0 0x10000000
1302 +/* RAM access BAR */
1303 +#define AR2315_PCI_HOST_MBAR1 AR2315_PCI_HOST_SDRAM_BASEADDR
1304 +/* ??? access BAR */
1305 +#define AR2315_PCI_HOST_MBAR2 0x30000000
1306 +
1307 +#endif /* __ASM_MACH_AR231X_AR2315_REGS_H */
1308 --- /dev/null
1309 +++ b/arch/mips/include/asm/mach-ar231x/ar5312_regs.h
1310 @@ -0,0 +1,249 @@
1311 +/*
1312 + * This file is subject to the terms and conditions of the GNU General Public
1313 + * License. See the file "COPYING" in the main directory of this archive
1314 + * for more details.
1315 + *
1316 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1317 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1318 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1319 + */
1320 +
1321 +#ifndef __ASM_MACH_AR231X_AR5312_REGS_H
1322 +#define __ASM_MACH_AR231X_AR5312_REGS_H
1323 +
1324 +#include <asm/addrspace.h>
1325 +
1326 +/*
1327 + * IRQs
1328 + */
1329 +#define AR5312_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
1330 +#define AR5312_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
1331 +#define AR5312_IRQ_ENET1_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
1332 +#define AR5312_IRQ_WLAN1_INTRS (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
1333 +#define AR5312_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
1334 +
1335 +/*
1336 + * Miscellaneous interrupts, which share IP6.
1337 + */
1338 +#define AR5312_MISC_IRQ_NONE (AR231X_MISC_IRQ_BASE+0)
1339 +#define AR5312_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+1)
1340 +#define AR5312_MISC_IRQ_AHB_PROC (AR231X_MISC_IRQ_BASE+2)
1341 +#define AR5312_MISC_IRQ_AHB_DMA (AR231X_MISC_IRQ_BASE+3)
1342 +#define AR5312_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+4)
1343 +#define AR5312_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+5)
1344 +#define AR5312_MISC_IRQ_UART0_DMA (AR231X_MISC_IRQ_BASE+6)
1345 +#define AR5312_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+7)
1346 +#define AR5312_MISC_IRQ_LOCAL (AR231X_MISC_IRQ_BASE+8)
1347 +#define AR5312_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+9)
1348 +#define AR5312_MISC_IRQ_COUNT 10
1349 +
1350 +/*
1351 + * Address Map
1352 + */
1353 +#define AR5312_WLAN0 0x18000000
1354 +#define AR5312_WLAN1 0x18500000
1355 +#define AR5312_ENET0 0x18100000
1356 +#define AR5312_ENET1 0x18200000
1357 +#define AR5312_SDRAMCTL 0x18300000
1358 +#define AR5312_FLASHCTL 0x18400000
1359 +#define AR5312_APBBASE 0x1c000000
1360 +#define AR5312_UART0 0x1c000000 /* UART MMR */
1361 +#define AR5312_FLASH 0x1e000000
1362 +
1363 +/*
1364 + * AR5312_NUM_ENET_MAC defines the number of ethernet MACs that
1365 + * should be considered available. The AR5312 supports 2 enet MACS,
1366 + * even though many reference boards only actually use 1 of them
1367 + * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch.
1368 + * The AR2312 supports 1 enet MAC.
1369 + */
1370 +#define AR5312_NUM_ENET_MAC 2
1371 +
1372 +/*
1373 + * Need these defines to determine true number of ethernet MACs
1374 + */
1375 +#define AR5312_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
1376 +#define AR5312_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
1377 +#define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
1378 +
1379 +/* MII registers offset inside Ethernet MMR region */
1380 +#define AR5312_ENET0_MII (AR5312_ENET0 + 0x14)
1381 +#define AR5312_ENET1_MII (AR5312_ENET1 + 0x14)
1382 +
1383 +/*
1384 + * AR5312_NUM_WMAC defines the number of Wireless MACs that\
1385 + * should be considered available.
1386 + */
1387 +#define AR5312_NUM_WMAC 2
1388 +
1389 +/* Reset/Timer Block Address Map */
1390 +#define AR5312_RESETTMR (AR5312_APBBASE + 0x3000)
1391 +#define AR5312_TIMER (AR5312_RESETTMR + 0x0000) /* countdown timer */
1392 +#define AR5312_WD_CTRL (AR5312_RESETTMR + 0x0008) /* watchdog cntrl */
1393 +#define AR5312_WD_TIMER (AR5312_RESETTMR + 0x000c) /* watchdog timer */
1394 +#define AR5312_ISR (AR5312_RESETTMR + 0x0010) /* Intr Status Reg */
1395 +#define AR5312_IMR (AR5312_RESETTMR + 0x0014) /* Intr Mask Reg */
1396 +#define AR5312_RESET (AR5312_RESETTMR + 0x0020)
1397 +#define AR5312_CLOCKCTL1 (AR5312_RESETTMR + 0x0064)
1398 +#define AR5312_SCRATCH (AR5312_RESETTMR + 0x006c)
1399 +#define AR5312_PROCADDR (AR5312_RESETTMR + 0x0070)
1400 +#define AR5312_PROC1 (AR5312_RESETTMR + 0x0074)
1401 +#define AR5312_DMAADDR (AR5312_RESETTMR + 0x0078)
1402 +#define AR5312_DMA1 (AR5312_RESETTMR + 0x007c)
1403 +#define AR5312_ENABLE (AR5312_RESETTMR + 0x0080) /* interface enb */
1404 +#define AR5312_REV (AR5312_RESETTMR + 0x0090) /* revision */
1405 +
1406 +/* AR5312_WD_CTRL register bit field definitions */
1407 +#define AR5312_WD_CTRL_IGNORE_EXPIRATION 0x0000
1408 +#define AR5312_WD_CTRL_NMI 0x0001
1409 +#define AR5312_WD_CTRL_RESET 0x0002
1410 +
1411 +/* AR5312_ISR register bit field definitions */
1412 +#define AR5312_ISR_NONE 0x0000
1413 +#define AR5312_ISR_TIMER 0x0001
1414 +#define AR5312_ISR_AHBPROC 0x0002
1415 +#define AR5312_ISR_AHBDMA 0x0004
1416 +#define AR5312_ISR_GPIO 0x0008
1417 +#define AR5312_ISR_UART0 0x0010
1418 +#define AR5312_ISR_UART0DMA 0x0020
1419 +#define AR5312_ISR_WD 0x0040
1420 +#define AR5312_ISR_LOCAL 0x0080
1421 +
1422 +/* AR5312_RESET register bit field definitions */
1423 +#define AR5312_RESET_SYSTEM 0x00000001 /* cold reset full system */
1424 +#define AR5312_RESET_PROC 0x00000002 /* cold reset MIPS core */
1425 +#define AR5312_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
1426 +#define AR5312_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
1427 +#define AR5312_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
1428 +#define AR5312_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
1429 +#define AR5312_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
1430 +#define AR5312_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */
1431 +#define AR5312_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
1432 +#define AR5312_RESET_APB 0x00000400 /* cold reset APB (ar5312) */
1433 +#define AR5312_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
1434 +#define AR5312_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
1435 +#define AR5312_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */
1436 +#define AR5312_RESET_NMI 0x00010000 /* send an NMI to the processor */
1437 +#define AR5312_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */
1438 +#define AR5312_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */
1439 +#define AR5312_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
1440 +#define AR5312_RESET_WDOG 0x00100000 /* last reset was a watchdog */
1441 +
1442 +#define AR5312_RESET_WMAC0_BITS \
1443 + (AR5312_RESET_WLAN0 |\
1444 + AR5312_RESET_WARM_WLAN0_MAC |\
1445 + AR5312_RESET_WARM_WLAN0_BB)
1446 +
1447 +#define AR5312_RESET_WMAC1_BITS \
1448 + (AR5312_RESET_WLAN1 |\
1449 + AR5312_RESET_WARM_WLAN1_MAC |\
1450 + AR5312_RESET_WARM_WLAN1_BB)
1451 +
1452 +/* AR5312_CLOCKCTL1 register bit field definitions */
1453 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1454 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1455 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1456 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1457 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1458 +
1459 +/* Valid for AR5312 and AR2312 */
1460 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1461 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1462 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1463 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1464 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1465 +
1466 +/* Valid for AR2313 */
1467 +#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
1468 +#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
1469 +#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
1470 +#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
1471 +#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
1472 +
1473 +/* AR5312_ENABLE register bit field definitions */
1474 +#define AR5312_ENABLE_WLAN0 0x0001
1475 +#define AR5312_ENABLE_ENET0 0x0002
1476 +#define AR5312_ENABLE_ENET1 0x0004
1477 +#define AR5312_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */
1478 +#define AR5312_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */
1479 +#define AR5312_ENABLE_WLAN1 \
1480 + (AR5312_ENABLE_UART_AND_WLAN1_PIO |\
1481 + AR5312_ENABLE_WLAN1_DMA)
1482 +
1483 +/* AR5312_REV register bit field definitions */
1484 +#define AR5312_REV_WMAC_MAJ 0xf000
1485 +#define AR5312_REV_WMAC_MAJ_S 12
1486 +#define AR5312_REV_WMAC_MIN 0x0f00
1487 +#define AR5312_REV_WMAC_MIN_S 8
1488 +#define AR5312_REV_MAJ 0x00f0
1489 +#define AR5312_REV_MAJ_S 4
1490 +#define AR5312_REV_MIN 0x000f
1491 +#define AR5312_REV_MIN_S 0
1492 +#define AR5312_REV_CHIP (AR5312_REV_MAJ|AR5312_REV_MIN)
1493 +
1494 +/* Major revision numbers, bits 7..4 of Revision ID register */
1495 +#define AR5312_REV_MAJ_AR5312 0x4
1496 +#define AR5312_REV_MAJ_AR2313 0x5
1497 +
1498 +/* Minor revision numbers, bits 3..0 of Revision ID register */
1499 +#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
1500 +#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
1501 +
1502 +/* AR5312_FLASHCTL register bit field definitions */
1503 +#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */
1504 +#define FLASHCTL_IDCY_S 0
1505 +#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
1506 +#define FLASHCTL_WST1_S 5
1507 +#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
1508 +#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
1509 +#define FLASHCTL_WST2_S 11
1510 +#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */
1511 +#define FLASHCTL_AC_S 16
1512 +#define FLASHCTL_AC_128K 0x00000000
1513 +#define FLASHCTL_AC_256K 0x00010000
1514 +#define FLASHCTL_AC_512K 0x00020000
1515 +#define FLASHCTL_AC_1M 0x00030000
1516 +#define FLASHCTL_AC_2M 0x00040000
1517 +#define FLASHCTL_AC_4M 0x00050000
1518 +#define FLASHCTL_AC_8M 0x00060000
1519 +#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
1520 +#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
1521 +#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */
1522 +#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */
1523 +#define FLASHCTL_WP 0x04000000 /* Write protect */
1524 +#define FLASHCTL_BM 0x08000000 /* Burst mode */
1525 +#define FLASHCTL_MW 0x30000000 /* Memory width */
1526 +#define FLASHCTL_MW8 0x00000000 /* Memory width x8 */
1527 +#define FLASHCTL_MW16 0x10000000 /* Memory width x16 */
1528 +#define FLASHCTL_MW32 0x20000000 /* Memory width x32 (not supported) */
1529 +#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */
1530 +#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */
1531 +#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */
1532 +
1533 +/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
1534 +#define AR5312_FLASHCTL0 (AR5312_FLASHCTL + 0x00)
1535 +#define AR5312_FLASHCTL1 (AR5312_FLASHCTL + 0x04)
1536 +#define AR5312_FLASHCTL2 (AR5312_FLASHCTL + 0x08)
1537 +
1538 +/* ARM SDRAM Controller -- just enough to determine memory size */
1539 +#define AR5312_MEM_CFG1 (AR5312_SDRAMCTL + 0x04)
1540 +#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */
1541 +#define MEM_CFG1_AC0_S 8
1542 +#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */
1543 +#define MEM_CFG1_AC1_S 12
1544 +
1545 +/* GPIO Address Map */
1546 +#define AR5312_GPIO (AR5312_APBBASE + 0x2000)
1547 +#define AR5312_GPIO_DO (AR5312_GPIO + 0x00) /* output register */
1548 +#define AR5312_GPIO_DI (AR5312_GPIO + 0x04) /* intput register */
1549 +#define AR5312_GPIO_CR (AR5312_GPIO + 0x08) /* control register */
1550 +
1551 +/* GPIO Control Register bit field definitions */
1552 +#define AR5312_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
1553 +#define AR5312_GPIO_CR_O(x) (0 << (x)) /* mask for output */
1554 +#define AR5312_GPIO_CR_I(x) (1 << (x)) /* mask for input */
1555 +#define AR5312_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt*/
1556 +#define AR5312_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */
1557 +#define AR5312_NUM_GPIO 8
1558 +
1559 +#endif /* __ASM_MACH_AR231X_AR5312_REGS_H */
1560 --- /dev/null
1561 +++ b/arch/mips/ar231x/ar5312.c
1562 @@ -0,0 +1,534 @@
1563 +/*
1564 + * This file is subject to the terms and conditions of the GNU General Public
1565 + * License. See the file "COPYING" in the main directory of this archive
1566 + * for more details.
1567 + *
1568 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1569 + * Copyright (C) 2006 FON Technology, SL.
1570 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1571 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1572 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1573 + */
1574 +
1575 +/*
1576 + * Platform devices for Atheros SoCs
1577 + */
1578 +
1579 +#include <generated/autoconf.h>
1580 +#include <linux/init.h>
1581 +#include <linux/module.h>
1582 +#include <linux/types.h>
1583 +#include <linux/string.h>
1584 +#include <linux/mtd/physmap.h>
1585 +#include <linux/platform_device.h>
1586 +#include <linux/kernel.h>
1587 +#include <linux/reboot.h>
1588 +#include <linux/leds.h>
1589 +#include <linux/gpio.h>
1590 +#include <asm/bootinfo.h>
1591 +#include <asm/reboot.h>
1592 +#include <asm/time.h>
1593 +#include <linux/irq.h>
1594 +#include <linux/io.h>
1595 +
1596 +#include <ar231x_platform.h>
1597 +#include <ar5312_regs.h>
1598 +#include <ar231x.h>
1599 +#include "devices.h"
1600 +#include "ar5312.h"
1601 +
1602 +static void ar5312_misc_irq_handler(unsigned irq, struct irq_desc *desc)
1603 +{
1604 + unsigned int ar231x_misc_intrs = ar231x_read_reg(AR5312_ISR) &
1605 + ar231x_read_reg(AR5312_IMR);
1606 +
1607 + if (ar231x_misc_intrs & AR5312_ISR_TIMER) {
1608 + do_IRQ(AR5312_MISC_IRQ_TIMER);
1609 + (void)ar231x_read_reg(AR5312_TIMER);
1610 + } else if (ar231x_misc_intrs & AR5312_ISR_AHBPROC)
1611 + do_IRQ(AR5312_MISC_IRQ_AHB_PROC);
1612 + else if ((ar231x_misc_intrs & AR5312_ISR_UART0))
1613 + do_IRQ(AR5312_MISC_IRQ_UART0);
1614 + else if (ar231x_misc_intrs & AR5312_ISR_WD)
1615 + do_IRQ(AR5312_MISC_IRQ_WATCHDOG);
1616 + else
1617 + do_IRQ(AR5312_MISC_IRQ_NONE);
1618 +}
1619 +
1620 +static asmlinkage void
1621 +ar5312_irq_dispatch(void)
1622 +{
1623 + int pending = read_c0_status() & read_c0_cause();
1624 +
1625 + if (pending & CAUSEF_IP2)
1626 + do_IRQ(AR5312_IRQ_WLAN0_INTRS);
1627 + else if (pending & CAUSEF_IP3)
1628 + do_IRQ(AR5312_IRQ_ENET0_INTRS);
1629 + else if (pending & CAUSEF_IP4)
1630 + do_IRQ(AR5312_IRQ_ENET1_INTRS);
1631 + else if (pending & CAUSEF_IP5)
1632 + do_IRQ(AR5312_IRQ_WLAN1_INTRS);
1633 + else if (pending & CAUSEF_IP6)
1634 + do_IRQ(AR5312_IRQ_MISC_INTRS);
1635 + else if (pending & CAUSEF_IP7)
1636 + do_IRQ(AR231X_IRQ_CPU_CLOCK);
1637 +}
1638 +
1639 +/* Enable the specified AR5312_MISC_IRQ interrupt */
1640 +static void
1641 +ar5312_misc_irq_unmask(struct irq_data *d)
1642 +{
1643 + unsigned int imr;
1644 +
1645 + imr = ar231x_read_reg(AR5312_IMR);
1646 + imr |= (1 << (d->irq - AR231X_MISC_IRQ_BASE - 1));
1647 + ar231x_write_reg(AR5312_IMR, imr);
1648 +}
1649 +
1650 +/* Disable the specified AR5312_MISC_IRQ interrupt */
1651 +static void
1652 +ar5312_misc_irq_mask(struct irq_data *d)
1653 +{
1654 + unsigned int imr;
1655 +
1656 + imr = ar231x_read_reg(AR5312_IMR);
1657 + imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE - 1));
1658 + ar231x_write_reg(AR5312_IMR, imr);
1659 + ar231x_read_reg(AR5312_IMR); /* flush write buffer */
1660 +}
1661 +
1662 +static struct irq_chip ar5312_misc_irq_chip = {
1663 + .name = "AR5312-MISC",
1664 + .irq_unmask = ar5312_misc_irq_unmask,
1665 + .irq_mask = ar5312_misc_irq_mask,
1666 +};
1667 +
1668 +static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id)
1669 +{
1670 + u32 proc1 = ar231x_read_reg(AR5312_PROC1);
1671 + u32 proc_addr = ar231x_read_reg(AR5312_PROCADDR); /* clears error */
1672 + u32 dma1 = ar231x_read_reg(AR5312_DMA1);
1673 + u32 dma_addr = ar231x_read_reg(AR5312_DMAADDR); /* clears error */
1674 +
1675 + pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
1676 + proc_addr, proc1, dma_addr, dma1);
1677 +
1678 + machine_restart("AHB error"); /* Catastrophic failure */
1679 + return IRQ_HANDLED;
1680 +}
1681 +
1682 +static struct irqaction ar5312_ahb_proc_interrupt = {
1683 + .handler = ar5312_ahb_proc_handler,
1684 + .name = "ar5312_ahb_proc_interrupt",
1685 +};
1686 +
1687 +void __init ar5312_irq_init(void)
1688 +{
1689 + int i;
1690 +
1691 + if (!is_5312())
1692 + return;
1693 +
1694 + ar231x_irq_dispatch = ar5312_irq_dispatch;
1695 + for (i = 0; i < AR5312_MISC_IRQ_COUNT; i++) {
1696 + int irq = AR231X_MISC_IRQ_BASE + i;
1697 +
1698 + irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip,
1699 + handle_level_irq);
1700 + }
1701 + setup_irq(AR5312_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt);
1702 + irq_set_chained_handler(AR5312_IRQ_MISC_INTRS, ar5312_misc_irq_handler);
1703 +}
1704 +
1705 +/*
1706 + * gpiolib implementations
1707 + */
1708 +static int
1709 +ar5312_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
1710 +{
1711 + return (ar231x_read_reg(AR5312_GPIO_DI) >> gpio) & 1;
1712 +}
1713 +
1714 +static void
1715 +ar5312_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
1716 +{
1717 + u32 reg = ar231x_read_reg(AR5312_GPIO_DO);
1718 +
1719 + reg = value ? reg | (1 << gpio) : reg & ~(1 << gpio);
1720 + ar231x_write_reg(AR5312_GPIO_DO, reg);
1721 +}
1722 +
1723 +static int
1724 +ar5312_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
1725 +{
1726 + ar231x_mask_reg(AR5312_GPIO_CR, 0, 1 << gpio);
1727 + return 0;
1728 +}
1729 +
1730 +static int
1731 +ar5312_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
1732 +{
1733 + ar231x_mask_reg(AR5312_GPIO_CR, 1 << gpio, 0);
1734 + ar5312_gpio_set_value(chip, gpio, value);
1735 + return 0;
1736 +}
1737 +
1738 +static struct gpio_chip ar5312_gpio_chip = {
1739 + .label = "ar5312-gpio",
1740 + .direction_input = ar5312_gpio_direction_input,
1741 + .direction_output = ar5312_gpio_direction_output,
1742 + .set = ar5312_gpio_set_value,
1743 + .get = ar5312_gpio_get_value,
1744 + .base = 0,
1745 + .ngpio = AR5312_NUM_GPIO, /* 8 */
1746 +};
1747 +
1748 +/* end of gpiolib */
1749 +
1750 +static void ar5312_device_reset_set(u32 mask)
1751 +{
1752 + u32 val;
1753 +
1754 + val = ar231x_read_reg(AR5312_RESET);
1755 + ar231x_write_reg(AR5312_RESET, val | mask);
1756 +}
1757 +
1758 +static void ar5312_device_reset_clear(u32 mask)
1759 +{
1760 + u32 val;
1761 +
1762 + val = ar231x_read_reg(AR5312_RESET);
1763 + ar231x_write_reg(AR5312_RESET, val & ~mask);
1764 +}
1765 +
1766 +static struct physmap_flash_data ar5312_flash_data = {
1767 + .width = 2,
1768 +};
1769 +
1770 +static struct resource ar5312_flash_resource = {
1771 + .start = AR5312_FLASH,
1772 + .end = AR5312_FLASH + 0x800000 - 1,
1773 + .flags = IORESOURCE_MEM,
1774 +};
1775 +
1776 +static struct ar231x_eth ar5312_eth0_data = {
1777 + .reset_set = ar5312_device_reset_set,
1778 + .reset_clear = ar5312_device_reset_clear,
1779 + .reset_mac = AR5312_RESET_ENET0,
1780 + .reset_phy = AR5312_RESET_EPHY0,
1781 + .config = &ar231x_board,
1782 +};
1783 +
1784 +static struct ar231x_eth ar5312_eth1_data = {
1785 + .reset_set = ar5312_device_reset_set,
1786 + .reset_clear = ar5312_device_reset_clear,
1787 + .reset_mac = AR5312_RESET_ENET1,
1788 + .reset_phy = AR5312_RESET_EPHY1,
1789 + .config = &ar231x_board,
1790 +};
1791 +
1792 +static struct platform_device ar5312_physmap_flash = {
1793 + .name = "physmap-flash",
1794 + .id = 0,
1795 + .dev.platform_data = &ar5312_flash_data,
1796 + .resource = &ar5312_flash_resource,
1797 + .num_resources = 1,
1798 +};
1799 +
1800 +#ifdef CONFIG_LEDS_GPIO
1801 +static struct gpio_led ar5312_leds[] = {
1802 + { .name = "wlan", .gpio = 0, .active_low = 1, },
1803 +};
1804 +
1805 +static const struct gpio_led_platform_data ar5312_led_data = {
1806 + .num_leds = ARRAY_SIZE(ar5312_leds),
1807 + .leds = (void *)ar5312_leds,
1808 +};
1809 +
1810 +static struct platform_device ar5312_gpio_leds = {
1811 + .name = "leds-gpio",
1812 + .id = -1,
1813 + .dev.platform_data = (void *)&ar5312_led_data,
1814 +};
1815 +#endif
1816 +
1817 +/*
1818 + * NB: This mapping size is larger than the actual flash size,
1819 + * but this shouldn't be a problem here, because the flash
1820 + * will simply be mapped multiple times.
1821 + */
1822 +static char __init *ar5312_flash_limit(void)
1823 +{
1824 + u32 ctl;
1825 + /*
1826 + * Configure flash bank 0.
1827 + * Assume 8M window size. Flash will be aliased if it's smaller
1828 + */
1829 + ctl = FLASHCTL_E |
1830 + FLASHCTL_AC_8M |
1831 + FLASHCTL_RBLE |
1832 + (0x01 << FLASHCTL_IDCY_S) |
1833 + (0x07 << FLASHCTL_WST1_S) |
1834 + (0x07 << FLASHCTL_WST2_S) |
1835 + (ar231x_read_reg(AR5312_FLASHCTL0) & FLASHCTL_MW);
1836 +
1837 + ar231x_write_reg(AR5312_FLASHCTL0, ctl);
1838 +
1839 + /* Disable other flash banks */
1840 + ar231x_write_reg(AR5312_FLASHCTL1,
1841 + ar231x_read_reg(AR5312_FLASHCTL1) &
1842 + ~(FLASHCTL_E | FLASHCTL_AC));
1843 +
1844 + ar231x_write_reg(AR5312_FLASHCTL2,
1845 + ar231x_read_reg(AR5312_FLASHCTL2) &
1846 + ~(FLASHCTL_E | FLASHCTL_AC));
1847 +
1848 + return (char *)KSEG1ADDR(AR5312_FLASH + 0x800000);
1849 +}
1850 +
1851 +int __init ar5312_init_devices(void)
1852 +{
1853 + struct ar231x_boarddata *config;
1854 + u32 fctl = 0;
1855 + u8 *c;
1856 +
1857 + if (!is_5312())
1858 + return 0;
1859 +
1860 + /* Locate board/radio config data */
1861 + ar231x_find_config(ar5312_flash_limit());
1862 + config = ar231x_board.config;
1863 +
1864 + /* AR2313 has CPU minor rev. 10 */
1865 + if ((current_cpu_data.processor_id & 0xff) == 0x0a)
1866 + ar231x_devtype = DEV_TYPE_AR2313;
1867 +
1868 + /* AR2312 shares the same Silicon ID as AR5312 */
1869 + else if (config->flags & BD_ISCASPER)
1870 + ar231x_devtype = DEV_TYPE_AR2312;
1871 +
1872 + /* Everything else is probably AR5312 or compatible */
1873 + else
1874 + ar231x_devtype = DEV_TYPE_AR5312;
1875 +
1876 + /* fixup flash width */
1877 + fctl = ar231x_read_reg(AR5312_FLASHCTL) & FLASHCTL_MW;
1878 + switch (fctl) {
1879 + case FLASHCTL_MW16:
1880 + ar5312_flash_data.width = 2;
1881 + break;
1882 + case FLASHCTL_MW8:
1883 + default:
1884 + ar5312_flash_data.width = 1;
1885 + break;
1886 + }
1887 +
1888 + platform_device_register(&ar5312_physmap_flash);
1889 +
1890 +#ifdef CONFIG_LEDS_GPIO
1891 + ar5312_leds[0].gpio = config->sys_led_gpio;
1892 + platform_device_register(&ar5312_gpio_leds);
1893 +#endif
1894 +
1895 + /* Fix up MAC addresses if necessary */
1896 + if (is_broadcast_ether_addr(config->enet0_mac))
1897 + ether_addr_copy(config->enet0_mac, config->enet1_mac);
1898 +
1899 + /* If ENET0 and ENET1 have the same mac address,
1900 + * increment the one from ENET1 */
1901 + if (ether_addr_equal(config->enet0_mac, config->enet1_mac)) {
1902 + c = config->enet1_mac + 5;
1903 + while ((c >= config->enet1_mac) && !(++(*c)))
1904 + c--;
1905 + }
1906 +
1907 + switch (ar231x_devtype) {
1908 + case DEV_TYPE_AR5312:
1909 + ar5312_eth0_data.macaddr = config->enet0_mac;
1910 + ar231x_add_ethernet(0, AR5312_ENET0, "eth0_mii",
1911 + AR5312_ENET0_MII, AR5312_IRQ_ENET0_INTRS,
1912 + &ar5312_eth0_data);
1913 +
1914 + ar5312_eth1_data.macaddr = config->enet1_mac;
1915 + ar231x_add_ethernet(1, AR5312_ENET1, "eth1_mii",
1916 + AR5312_ENET1_MII, AR5312_IRQ_ENET1_INTRS,
1917 + &ar5312_eth1_data);
1918 +
1919 + if (!ar231x_board.radio)
1920 + return 0;
1921 +
1922 + if (!(config->flags & BD_WLAN0))
1923 + break;
1924 +
1925 + ar231x_add_wmac(0, AR5312_WLAN0, AR5312_IRQ_WLAN0_INTRS);
1926 + break;
1927 + /*
1928 + * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
1929 + * of ENET1. Atheros calls it 'twisted' for a reason :)
1930 + */
1931 + case DEV_TYPE_AR2312:
1932 + case DEV_TYPE_AR2313:
1933 + ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
1934 + ar5312_eth1_data.macaddr = config->enet0_mac;
1935 + ar231x_add_ethernet(1, AR5312_ENET1, "eth0_mii",
1936 + AR5312_ENET0_MII, AR5312_IRQ_ENET1_INTRS,
1937 + &ar5312_eth1_data);
1938 +
1939 + if (!ar231x_board.radio)
1940 + return 0;
1941 + break;
1942 + default:
1943 + break;
1944 + }
1945 +
1946 + if (config->flags & BD_WLAN1)
1947 + ar231x_add_wmac(1, AR5312_WLAN1, AR5312_IRQ_WLAN1_INTRS);
1948 +
1949 + return 0;
1950 +}
1951 +
1952 +static void ar5312_restart(char *command)
1953 +{
1954 + /* reset the system */
1955 + local_irq_disable();
1956 + while (1)
1957 + ar231x_write_reg(AR5312_RESET, AR5312_RESET_SYSTEM);
1958 +}
1959 +
1960 +/*
1961 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
1962 + * to determine the predevisor value.
1963 + */
1964 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
1965 +
1966 +static int __init
1967 +ar5312_cpu_frequency(void)
1968 +{
1969 + unsigned int scratch;
1970 + unsigned int predivide_mask, predivide_shift;
1971 + unsigned int multiplier_mask, multiplier_shift;
1972 + unsigned int clock_ctl1, predivide_select, predivisor, multiplier;
1973 + unsigned int doubler_mask;
1974 + u16 devid;
1975 +
1976 + /* Trust the bootrom's idea of cpu frequency. */
1977 + scratch = ar231x_read_reg(AR5312_SCRATCH);
1978 + if (scratch)
1979 + return scratch;
1980 +
1981 + devid = ar231x_read_reg(AR5312_REV);
1982 + devid &= AR5312_REV_MAJ;
1983 + devid >>= AR5312_REV_MAJ_S;
1984 + if (devid == AR5312_REV_MAJ_AR2313) {
1985 + predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
1986 + predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
1987 + multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
1988 + multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
1989 + doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
1990 + } else { /* AR5312 and AR2312 */
1991 + predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
1992 + predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
1993 + multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
1994 + multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
1995 + doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
1996 + }
1997 +
1998 + /*
1999 + * Clocking is derived from a fixed 40MHz input clock.
2000 + *
2001 + * cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
2002 + * sys_freq = cpu_freq / 4 (used for APB clock, serial,
2003 + * flash, Timer, Watchdog Timer)
2004 + *
2005 + * cnt_freq = cpu_freq / 2 (use for CPU count/compare)
2006 + *
2007 + * So, for example, with a PLL multiplier of 5, we have
2008 + *
2009 + * cpu_freq = 200MHz
2010 + * sys_freq = 50MHz
2011 + * cnt_freq = 100MHz
2012 + *
2013 + * We compute the CPU frequency, based on PLL settings.
2014 + */
2015 +
2016 + clock_ctl1 = ar231x_read_reg(AR5312_CLOCKCTL1);
2017 + predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
2018 + predivisor = clockctl1_predivide_table[predivide_select];
2019 + multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
2020 +
2021 + if (clock_ctl1 & doubler_mask)
2022 + multiplier = multiplier << 1;
2023 +
2024 + return (40000000 / predivisor) * multiplier;
2025 +}
2026 +
2027 +static inline int
2028 +ar5312_sys_frequency(void)
2029 +{
2030 + return ar5312_cpu_frequency() / 4;
2031 +}
2032 +
2033 +void __init
2034 +ar5312_time_init(void)
2035 +{
2036 + if (!is_5312())
2037 + return;
2038 +
2039 + mips_hpt_frequency = ar5312_cpu_frequency() / 2;
2040 +}
2041 +
2042 +static int __init
2043 +ar5312_gpio_init(void)
2044 +{
2045 + int ret = gpiochip_add(&ar5312_gpio_chip);
2046 +
2047 + if (ret) {
2048 + pr_err("%s: failed to add gpiochip\n", ar5312_gpio_chip.label);
2049 + return ret;
2050 + }
2051 + pr_info("%s: registered %d GPIOs\n", ar5312_gpio_chip.label,
2052 + ar5312_gpio_chip.ngpio);
2053 + return ret;
2054 +}
2055 +
2056 +void __init
2057 +ar5312_prom_init(void)
2058 +{
2059 + u32 memsize, memcfg, bank0AC, bank1AC;
2060 + u32 devid;
2061 +
2062 + if (!is_5312())
2063 + return;
2064 +
2065 + /* Detect memory size */
2066 + memcfg = ar231x_read_reg(AR5312_MEM_CFG1);
2067 + bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
2068 + bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
2069 + memsize = (bank0AC ? (1 << (bank0AC+1)) : 0) +
2070 + (bank1AC ? (1 << (bank1AC+1)) : 0);
2071 + memsize <<= 20;
2072 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2073 +
2074 + devid = ar231x_read_reg(AR5312_REV);
2075 + devid >>= AR5312_REV_WMAC_MIN_S;
2076 + devid &= AR5312_REV_CHIP;
2077 + ar231x_board.devid = (u16)devid;
2078 + ar5312_gpio_init();
2079 +}
2080 +
2081 +void __init
2082 +ar5312_plat_setup(void)
2083 +{
2084 + if (!is_5312())
2085 + return;
2086 +
2087 + /* Clear any lingering AHB errors */
2088 + ar231x_read_reg(AR5312_PROCADDR);
2089 + ar231x_read_reg(AR5312_DMAADDR);
2090 + ar231x_write_reg(AR5312_WD_CTRL, AR5312_WD_CTRL_IGNORE_EXPIRATION);
2091 +
2092 + _machine_restart = ar5312_restart;
2093 + ar231x_serial_setup(AR5312_UART0, AR5312_MISC_IRQ_UART0,
2094 + ar5312_sys_frequency());
2095 +}
2096 +
2097 --- /dev/null
2098 +++ b/arch/mips/ar231x/ar2315.c
2099 @@ -0,0 +1,556 @@
2100 +/*
2101 + * This file is subject to the terms and conditions of the GNU General Public
2102 + * License. See the file "COPYING" in the main directory of this archive
2103 + * for more details.
2104 + *
2105 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
2106 + * Copyright (C) 2006 FON Technology, SL.
2107 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
2108 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
2109 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
2110 + */
2111 +
2112 +/*
2113 + * Platform devices for Atheros SoCs
2114 + */
2115 +
2116 +#include <generated/autoconf.h>
2117 +#include <linux/init.h>
2118 +#include <linux/module.h>
2119 +#include <linux/types.h>
2120 +#include <linux/string.h>
2121 +#include <linux/platform_device.h>
2122 +#include <linux/kernel.h>
2123 +#include <linux/reboot.h>
2124 +#include <linux/delay.h>
2125 +#include <linux/leds.h>
2126 +#include <linux/gpio.h>
2127 +#include <asm/bootinfo.h>
2128 +#include <asm/reboot.h>
2129 +#include <asm/time.h>
2130 +#include <linux/irq.h>
2131 +#include <linux/io.h>
2132 +
2133 +#include <ar231x_platform.h>
2134 +#include <ar2315_regs.h>
2135 +#include <ar231x.h>
2136 +#include "devices.h"
2137 +#include "ar2315.h"
2138 +
2139 +static u32 gpiointmask, gpiointval;
2140 +
2141 +static void ar2315_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
2142 +{
2143 + u32 pend;
2144 + int bit = -1;
2145 +
2146 + /* only do one gpio interrupt at a time */
2147 + pend = (ar231x_read_reg(AR2315_GPIO_DI) ^ gpiointval) & gpiointmask;
2148 +
2149 + if (pend) {
2150 + bit = fls(pend) - 1;
2151 + pend &= ~(1 << bit);
2152 + gpiointval ^= (1 << bit);
2153 + }
2154 +
2155 + if (!pend)
2156 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO);
2157 +
2158 + /* Enable interrupt with edge detection */
2159 + if ((ar231x_read_reg(AR2315_GPIO_DIR) & AR2315_GPIO_DIR_M(bit)) !=
2160 + AR2315_GPIO_DIR_I(bit))
2161 + return;
2162 +
2163 + if (bit >= 0)
2164 + do_IRQ(AR231X_GPIO_IRQ_BASE + bit);
2165 +}
2166 +
2167 +static void ar2315_misc_irq_handler(unsigned irq, struct irq_desc *desc)
2168 +{
2169 + unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) &
2170 + ar231x_read_reg(AR2315_IMR);
2171 +
2172 + if (misc_intr & AR2315_ISR_SPI)
2173 + do_IRQ(AR2315_MISC_IRQ_SPI);
2174 + else if (misc_intr & AR2315_ISR_TIMER)
2175 + do_IRQ(AR2315_MISC_IRQ_TIMER);
2176 + else if (misc_intr & AR2315_ISR_AHB)
2177 + do_IRQ(AR2315_MISC_IRQ_AHB);
2178 + else if (misc_intr & AR2315_ISR_GPIO)
2179 + do_IRQ(AR2315_MISC_IRQ_GPIO);
2180 + else if (misc_intr & AR2315_ISR_UART0)
2181 + do_IRQ(AR2315_MISC_IRQ_UART0);
2182 + else if (misc_intr & AR2315_ISR_WD) {
2183 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_WD);
2184 + do_IRQ(AR2315_MISC_IRQ_WATCHDOG);
2185 + } else
2186 + do_IRQ(AR2315_MISC_IRQ_NONE);
2187 +}
2188 +
2189 +/*
2190 + * Called when an interrupt is received, this function
2191 + * determines exactly which interrupt it was, and it
2192 + * invokes the appropriate handler.
2193 + *
2194 + * Implicitly, we also define interrupt priority by
2195 + * choosing which to dispatch first.
2196 + */
2197 +static asmlinkage void
2198 +ar2315_irq_dispatch(void)
2199 +{
2200 + int pending = read_c0_status() & read_c0_cause();
2201 +
2202 + if (pending & CAUSEF_IP3)
2203 + do_IRQ(AR2315_IRQ_WLAN0_INTRS);
2204 + else if (pending & CAUSEF_IP4)
2205 + do_IRQ(AR2315_IRQ_ENET0_INTRS);
2206 + else if (pending & CAUSEF_IP2)
2207 + do_IRQ(AR2315_IRQ_MISC_INTRS);
2208 + else if (pending & CAUSEF_IP7)
2209 + do_IRQ(AR231X_IRQ_CPU_CLOCK);
2210 +}
2211 +
2212 +static void ar2315_set_gpiointmask(int gpio, int level)
2213 +{
2214 + u32 reg;
2215 +
2216 + reg = ar231x_read_reg(AR2315_GPIO_INT);
2217 + reg &= ~(AR2315_GPIO_INT_M | AR2315_GPIO_INT_LVL_M);
2218 + reg |= gpio | AR2315_GPIO_INT_LVL(level);
2219 + ar231x_write_reg(AR2315_GPIO_INT, reg);
2220 +}
2221 +
2222 +static void ar2315_gpio_irq_unmask(struct irq_data *d)
2223 +{
2224 + unsigned int gpio = d->irq - AR231X_GPIO_IRQ_BASE;
2225 +
2226 + /* Enable interrupt with edge detection */
2227 + if ((ar231x_read_reg(AR2315_GPIO_DIR) & AR2315_GPIO_DIR_M(gpio)) !=
2228 + AR2315_GPIO_DIR_I(gpio))
2229 + return;
2230 +
2231 + gpiointmask |= (1 << gpio);
2232 + ar2315_set_gpiointmask(gpio, 3);
2233 +}
2234 +
2235 +static void ar2315_gpio_irq_mask(struct irq_data *d)
2236 +{
2237 + unsigned int gpio = d->irq - AR231X_GPIO_IRQ_BASE;
2238 +
2239 + /* Disable interrupt */
2240 + gpiointmask &= ~(1 << gpio);
2241 + ar2315_set_gpiointmask(gpio, 0);
2242 +}
2243 +
2244 +static struct irq_chip ar2315_gpio_irq_chip = {
2245 + .name = "AR2315-GPIO",
2246 + .irq_unmask = ar2315_gpio_irq_unmask,
2247 + .irq_mask = ar2315_gpio_irq_mask,
2248 +};
2249 +
2250 +static void
2251 +ar2315_misc_irq_unmask(struct irq_data *d)
2252 +{
2253 + unsigned int imr;
2254 +
2255 + imr = ar231x_read_reg(AR2315_IMR);
2256 + imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE - 1);
2257 + ar231x_write_reg(AR2315_IMR, imr);
2258 +}
2259 +
2260 +static void
2261 +ar2315_misc_irq_mask(struct irq_data *d)
2262 +{
2263 + unsigned int imr;
2264 +
2265 + imr = ar231x_read_reg(AR2315_IMR);
2266 + imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE - 1));
2267 + ar231x_write_reg(AR2315_IMR, imr);
2268 +}
2269 +
2270 +static struct irq_chip ar2315_misc_irq_chip = {
2271 + .name = "AR2315-MISC",
2272 + .irq_unmask = ar2315_misc_irq_unmask,
2273 + .irq_mask = ar2315_misc_irq_mask,
2274 +};
2275 +
2276 +static irqreturn_t ar2315_ahb_proc_handler(int cpl, void *dev_id)
2277 +{
2278 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2279 + ar231x_read_reg(AR2315_AHB_ERR1);
2280 +
2281 + pr_emerg("AHB fatal error\n");
2282 + machine_restart("AHB error"); /* Catastrophic failure */
2283 +
2284 + return IRQ_HANDLED;
2285 +}
2286 +
2287 +static struct irqaction ar2315_ahb_proc_interrupt = {
2288 + .handler = ar2315_ahb_proc_handler,
2289 + .name = "ar2315_ahb_proc_interrupt",
2290 +};
2291 +
2292 +void
2293 +ar2315_irq_init(void)
2294 +{
2295 + int i;
2296 +
2297 + if (!is_2315())
2298 + return;
2299 +
2300 + ar231x_irq_dispatch = ar2315_irq_dispatch;
2301 + gpiointval = ar231x_read_reg(AR2315_GPIO_DI);
2302 + for (i = 0; i < AR2315_MISC_IRQ_COUNT; i++) {
2303 + int irq = AR231X_MISC_IRQ_BASE + i;
2304 +
2305 + irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip,
2306 + handle_level_irq);
2307 + }
2308 + for (i = 0; i < AR2315_NUM_GPIO; i++) {
2309 + int irq = AR231X_GPIO_IRQ_BASE + i;
2310 +
2311 + irq_set_chip_and_handler(irq, &ar2315_gpio_irq_chip,
2312 + handle_level_irq);
2313 + }
2314 + irq_set_chained_handler(AR2315_MISC_IRQ_GPIO, ar2315_gpio_irq_handler);
2315 + setup_irq(AR2315_MISC_IRQ_AHB, &ar2315_ahb_proc_interrupt);
2316 + irq_set_chained_handler(AR2315_IRQ_MISC_INTRS, ar2315_misc_irq_handler);
2317 +}
2318 +
2319 +/*
2320 + * gpiolib implementation
2321 + */
2322 +static int
2323 +ar2315_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
2324 +{
2325 + return (ar231x_read_reg(AR2315_GPIO_DI) >> gpio) & 1;
2326 +}
2327 +
2328 +static void
2329 +ar2315_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
2330 +{
2331 + u32 reg = ar231x_read_reg(AR2315_GPIO_DO);
2332 +
2333 + reg = value ? reg | (1 << gpio) : reg & ~(1 << gpio);
2334 + ar231x_write_reg(AR2315_GPIO_DO, reg);
2335 +}
2336 +
2337 +static int
2338 +ar2315_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
2339 +{
2340 + ar231x_mask_reg(AR2315_GPIO_DIR, 1 << gpio, 0);
2341 + return 0;
2342 +}
2343 +
2344 +static int
2345 +ar2315_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
2346 +{
2347 + ar231x_mask_reg(AR2315_GPIO_DIR, 0, 1 << gpio);
2348 + ar2315_gpio_set_value(chip, gpio, value);
2349 + return 0;
2350 +}
2351 +
2352 +static struct gpio_chip ar2315_gpio_chip = {
2353 + .label = "ar2315-gpio",
2354 + .direction_input = ar2315_gpio_direction_input,
2355 + .direction_output = ar2315_gpio_direction_output,
2356 + .set = ar2315_gpio_set_value,
2357 + .get = ar2315_gpio_get_value,
2358 + .base = 0,
2359 + .ngpio = AR2315_NUM_GPIO, /* 22 */
2360 +};
2361 +
2362 +/* end of gpiolib */
2363 +
2364 +static void ar2315_device_reset_set(u32 mask)
2365 +{
2366 + u32 val;
2367 +
2368 + val = ar231x_read_reg(AR2315_RESET);
2369 + ar231x_write_reg(AR2315_RESET, val | mask);
2370 +}
2371 +
2372 +static void ar2315_device_reset_clear(u32 mask)
2373 +{
2374 + u32 val;
2375 +
2376 + val = ar231x_read_reg(AR2315_RESET);
2377 + ar231x_write_reg(AR2315_RESET, val & ~mask);
2378 +}
2379 +
2380 +static struct ar231x_eth ar2315_eth_data = {
2381 + .reset_set = ar2315_device_reset_set,
2382 + .reset_clear = ar2315_device_reset_clear,
2383 + .reset_mac = AR2315_RESET_ENET0,
2384 + .reset_phy = AR2315_RESET_EPHY0,
2385 + .config = &ar231x_board,
2386 +};
2387 +
2388 +static struct resource ar2315_spiflash_res[] = {
2389 + {
2390 + .name = "spiflash_read",
2391 + .flags = IORESOURCE_MEM,
2392 + .start = AR2315_SPI_READ,
2393 + .end = AR2315_SPI_READ + 0x1000000 - 1,
2394 + },
2395 + {
2396 + .name = "spiflash_mmr",
2397 + .flags = IORESOURCE_MEM,
2398 + .start = AR2315_SPI_MMR,
2399 + .end = AR2315_SPI_MMR + 12 - 1,
2400 + },
2401 +};
2402 +
2403 +static struct platform_device ar2315_spiflash = {
2404 + .id = 0,
2405 + .name = "ar2315-spiflash",
2406 + .resource = ar2315_spiflash_res,
2407 + .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
2408 +};
2409 +
2410 +static struct resource ar2315_wdt_res[] = {
2411 + {
2412 + .flags = IORESOURCE_MEM,
2413 + .start = AR2315_WD,
2414 + .end = AR2315_WD + 8 - 1,
2415 + },
2416 + {
2417 + .flags = IORESOURCE_IRQ,
2418 + .start = AR2315_MISC_IRQ_WATCHDOG,
2419 + .end = AR2315_MISC_IRQ_WATCHDOG,
2420 + }
2421 +};
2422 +
2423 +static struct platform_device ar2315_wdt = {
2424 + .id = 0,
2425 + .name = "ar2315-wdt",
2426 + .resource = ar2315_wdt_res,
2427 + .num_resources = ARRAY_SIZE(ar2315_wdt_res)
2428 +};
2429 +
2430 +/*
2431 + * NB: We use mapping size that is larger than the actual flash size,
2432 + * but this shouldn't be a problem here, because the flash will simply
2433 + * be mapped multiple times.
2434 + */
2435 +static u8 __init *ar2315_flash_limit(void)
2436 +{
2437 + return (u8 *)KSEG1ADDR(ar2315_spiflash_res[0].end + 1);
2438 +}
2439 +
2440 +#ifdef CONFIG_LEDS_GPIO
2441 +static struct gpio_led ar2315_leds[6];
2442 +static struct gpio_led_platform_data ar2315_led_data = {
2443 + .leds = (void *)ar2315_leds,
2444 +};
2445 +
2446 +static struct platform_device ar2315_gpio_leds = {
2447 + .name = "leds-gpio",
2448 + .id = -1,
2449 + .dev = {
2450 + .platform_data = (void *)&ar2315_led_data,
2451 + }
2452 +};
2453 +
2454 +static void __init
2455 +ar2315_init_gpio_leds(void)
2456 +{
2457 + static char led_names[6][6];
2458 + int i, led = 0;
2459 +
2460 + ar2315_led_data.num_leds = 0;
2461 + for (i = 1; i < 8; i++) {
2462 + if ((i == AR2315_RESET_GPIO) ||
2463 + (i == ar231x_board.config->reset_config_gpio))
2464 + continue;
2465 +
2466 + if (i == ar231x_board.config->sys_led_gpio)
2467 + strcpy(led_names[led], "wlan");
2468 + else
2469 + sprintf(led_names[led], "gpio%d", i);
2470 +
2471 + ar2315_leds[led].name = led_names[led];
2472 + ar2315_leds[led].gpio = i;
2473 + ar2315_leds[led].active_low = 0;
2474 + led++;
2475 + }
2476 + ar2315_led_data.num_leds = led;
2477 + platform_device_register(&ar2315_gpio_leds);
2478 +}
2479 +#else
2480 +static inline void ar2315_init_gpio_leds(void)
2481 +{
2482 +}
2483 +#endif
2484 +
2485 +int __init
2486 +ar2315_init_devices(void)
2487 +{
2488 + if (!is_2315())
2489 + return 0;
2490 +
2491 + /* Find board configuration */
2492 + ar231x_find_config(ar2315_flash_limit());
2493 + ar2315_eth_data.macaddr = ar231x_board.config->enet0_mac;
2494 +
2495 + ar2315_init_gpio_leds();
2496 + platform_device_register(&ar2315_wdt);
2497 + platform_device_register(&ar2315_spiflash);
2498 + ar231x_add_ethernet(0, AR2315_ENET0, "eth0_mii", AR2315_ENET0_MII,
2499 + AR2315_IRQ_ENET0_INTRS, &ar2315_eth_data);
2500 + ar231x_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS);
2501 +
2502 + return 0;
2503 +}
2504 +
2505 +static void
2506 +ar2315_restart(char *command)
2507 +{
2508 + void (*mips_reset_vec)(void) = (void *)0xbfc00000;
2509 +
2510 + local_irq_disable();
2511 +
2512 + /* try reset the system via reset control */
2513 + ar231x_write_reg(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
2514 +
2515 + /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
2516 + * a workaround. Give it some time to attempt a gpio based hardware
2517 + * reset (atheros reference design workaround) */
2518 + gpio_request_one(AR2315_RESET_GPIO, GPIOF_OUT_INIT_LOW, "Reset");
2519 + mdelay(100);
2520 +
2521 + /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
2522 + * workaround. Attempt to jump to the mips reset location -
2523 + * the boot loader itself might be able to recover the system */
2524 + mips_reset_vec();
2525 +}
2526 +
2527 +/*
2528 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
2529 + * to determine the predevisor value.
2530 + */
2531 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
2532 +static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
2533 +
2534 +static unsigned int __init
2535 +ar2315_sys_clk(unsigned int clock_ctl)
2536 +{
2537 + unsigned int pllc_ctrl, cpu_div;
2538 + unsigned int pllc_out, refdiv, fdiv, divby2;
2539 + unsigned int clk_div;
2540 +
2541 + pllc_ctrl = ar231x_read_reg(AR2315_PLLC_CTL);
2542 + refdiv = (pllc_ctrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
2543 + refdiv = clockctl1_predivide_table[refdiv];
2544 + fdiv = (pllc_ctrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
2545 + divby2 = (pllc_ctrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
2546 + divby2 += 1;
2547 + pllc_out = (40000000/refdiv)*(2*divby2)*fdiv;
2548 +
2549 + /* clkm input selected */
2550 + switch (clock_ctl & CPUCLK_CLK_SEL_M) {
2551 + case 0:
2552 + case 1:
2553 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKM_DIV_M) >>
2554 + PLLC_CLKM_DIV_S];
2555 + break;
2556 + case 2:
2557 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKC_DIV_M) >>
2558 + PLLC_CLKC_DIV_S];
2559 + break;
2560 + default:
2561 + pllc_out = 40000000;
2562 + clk_div = 1;
2563 + break;
2564 + }
2565 +
2566 + cpu_div = (clock_ctl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
2567 + cpu_div = cpu_div * 2 ?: 1;
2568 +
2569 + return pllc_out / (clk_div * cpu_div);
2570 +}
2571 +
2572 +static inline unsigned int
2573 +ar2315_cpu_frequency(void)
2574 +{
2575 + return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK));
2576 +}
2577 +
2578 +static inline unsigned int
2579 +ar2315_apb_frequency(void)
2580 +{
2581 + return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK));
2582 +}
2583 +
2584 +void __init
2585 +ar2315_time_init(void)
2586 +{
2587 + if (!is_2315())
2588 + return;
2589 +
2590 + mips_hpt_frequency = ar2315_cpu_frequency() / 2;
2591 +}
2592 +
2593 +static int __init
2594 +ar2315_gpio_init(void)
2595 +{
2596 + int ret = gpiochip_add(&ar2315_gpio_chip);
2597 +
2598 + if (ret) {
2599 + pr_err("%s: failed to add gpiochip\n", ar2315_gpio_chip.label);
2600 + return ret;
2601 + }
2602 + pr_info("%s: registered %d GPIOs\n", ar2315_gpio_chip.label,
2603 + ar2315_gpio_chip.ngpio);
2604 + return ret;
2605 +}
2606 +
2607 +void __init
2608 +ar2315_prom_init(void)
2609 +{
2610 + u32 memsize, memcfg, devid;
2611 +
2612 + if (!is_2315())
2613 + return;
2614 +
2615 + memcfg = ar231x_read_reg(AR2315_MEM_CFG);
2616 + memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
2617 + memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
2618 + memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
2619 + memsize <<= 3;
2620 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2621 +
2622 + /* Detect the hardware based on the device ID */
2623 + devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP;
2624 + switch (devid) {
2625 + case 0x90:
2626 + case 0x91:
2627 + ar231x_devtype = DEV_TYPE_AR2317;
2628 + break;
2629 + default:
2630 + ar231x_devtype = DEV_TYPE_AR2315;
2631 + break;
2632 + }
2633 + ar2315_gpio_init();
2634 + ar231x_board.devid = devid;
2635 +}
2636 +
2637 +void __init
2638 +ar2315_plat_setup(void)
2639 +{
2640 + u32 config;
2641 +
2642 + if (!is_2315())
2643 + return;
2644 +
2645 + /* Clear any lingering AHB errors */
2646 + config = read_c0_config();
2647 + write_c0_config(config & ~0x3);
2648 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2649 + ar231x_read_reg(AR2315_AHB_ERR1);
2650 + ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION);
2651 +
2652 + _machine_restart = ar2315_restart;
2653 + ar231x_serial_setup(AR2315_UART0, AR2315_MISC_IRQ_UART0,
2654 + ar2315_apb_frequency());
2655 +}
2656 --- /dev/null
2657 +++ b/arch/mips/ar231x/ar2315.h
2658 @@ -0,0 +1,37 @@
2659 +#ifndef __AR2315_H
2660 +#define __AR2315_H
2661 +
2662 +#ifdef CONFIG_ATHEROS_AR2315
2663 +
2664 +void ar2315_irq_init(void);
2665 +int ar2315_init_devices(void);
2666 +void ar2315_prom_init(void);
2667 +void ar2315_plat_setup(void);
2668 +void ar2315_time_init(void);
2669 +
2670 +#else
2671 +
2672 +static inline void ar2315_irq_init(void)
2673 +{
2674 +}
2675 +
2676 +static inline int ar2315_init_devices(void)
2677 +{
2678 + return 0;
2679 +}
2680 +
2681 +static inline void ar2315_prom_init(void)
2682 +{
2683 +}
2684 +
2685 +static inline void ar2315_plat_setup(void)
2686 +{
2687 +}
2688 +
2689 +static inline void ar2315_time_init(void)
2690 +{
2691 +}
2692 +
2693 +#endif
2694 +
2695 +#endif
2696 --- /dev/null
2697 +++ b/arch/mips/ar231x/ar5312.h
2698 @@ -0,0 +1,37 @@
2699 +#ifndef __AR5312_H
2700 +#define __AR5312_H
2701 +
2702 +#ifdef CONFIG_ATHEROS_AR5312
2703 +
2704 +void ar5312_irq_init(void);
2705 +int ar5312_init_devices(void);
2706 +void ar5312_prom_init(void);
2707 +void ar5312_plat_setup(void);
2708 +void ar5312_time_init(void);
2709 +
2710 +#else
2711 +
2712 +static inline void ar5312_irq_init(void)
2713 +{
2714 +}
2715 +
2716 +static inline int ar5312_init_devices(void)
2717 +{
2718 + return 0;
2719 +}
2720 +
2721 +static inline void ar5312_prom_init(void)
2722 +{
2723 +}
2724 +
2725 +static inline void ar5312_plat_setup(void)
2726 +{
2727 +}
2728 +
2729 +static inline void ar5312_time_init(void)
2730 +{
2731 +}
2732 +
2733 +#endif
2734 +
2735 +#endif
2736 --- /dev/null
2737 +++ b/arch/mips/include/asm/mach-ar231x/ar231x.h
2738 @@ -0,0 +1,43 @@
2739 +#ifndef __ASM_MACH_AR231X_H
2740 +#define __ASM_MACH_AR231X_H
2741 +
2742 +#include <linux/types.h>
2743 +#include <linux/io.h>
2744 +
2745 +#define AR231X_MISC_IRQ_BASE 0x20
2746 +#define AR231X_GPIO_IRQ_BASE 0x30
2747 +
2748 +/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
2749 +#define AR231X_IRQ_NONE (MIPS_CPU_IRQ_BASE+0)
2750 +#define AR231X_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE+7) /* C0_CAUSE: 0x8000 */
2751 +
2752 +/* GPIO Interrupts, share ARXXXX_MISC_IRQ_GPIO */
2753 +#define AR231X_GPIO_IRQ_NONE (AR231X_GPIO_IRQ_BASE+0)
2754 +#define AR231X_GPIO_IRQ(n) (AR231X_GPIO_IRQ_BASE+n)
2755 +
2756 +static inline u32
2757 +ar231x_read_reg(u32 reg)
2758 +{
2759 + return __raw_readl((void __iomem *)KSEG1ADDR(reg));
2760 +}
2761 +
2762 +static inline void
2763 +ar231x_write_reg(u32 reg, u32 val)
2764 +{
2765 + __raw_writel(val, (void __iomem *)KSEG1ADDR(reg));
2766 +}
2767 +
2768 +static inline u32
2769 +ar231x_mask_reg(u32 reg, u32 mask, u32 val)
2770 +{
2771 + u32 ret;
2772 +
2773 + ret = ar231x_read_reg(reg);
2774 + ret &= ~mask;
2775 + ret |= val;
2776 + ar231x_write_reg(reg, ret);
2777 +
2778 + return ret;
2779 +}
2780 +
2781 +#endif /* __ASM_MACH_AR231X_H */
2782 --- /dev/null
2783 +++ b/arch/mips/ar231x/devices.h
2784 @@ -0,0 +1,38 @@
2785 +#ifndef __AR231X_DEVICES_H
2786 +#define __AR231X_DEVICES_H
2787 +
2788 +enum {
2789 + /* handled by ar5312.c */
2790 + DEV_TYPE_AR2312,
2791 + DEV_TYPE_AR2313,
2792 + DEV_TYPE_AR5312,
2793 +
2794 + /* handled by ar2315.c */
2795 + DEV_TYPE_AR2315,
2796 + DEV_TYPE_AR2316,
2797 + DEV_TYPE_AR2317,
2798 +
2799 + DEV_TYPE_UNKNOWN
2800 +};
2801 +
2802 +extern int ar231x_devtype;
2803 +extern struct ar231x_board_config ar231x_board;
2804 +extern asmlinkage void (*ar231x_irq_dispatch)(void);
2805 +
2806 +int ar231x_find_config(u8 *flash_limit);
2807 +void ar231x_serial_setup(u32 mapbase, int irq, unsigned int uartclk);
2808 +int ar231x_add_wmac(int nr, u32 base, int irq);
2809 +int ar231x_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
2810 + int irq, void *pdata);
2811 +
2812 +static inline bool is_2315(void)
2813 +{
2814 + return (current_cpu_data.cputype == CPU_4KEC);
2815 +}
2816 +
2817 +static inline bool is_5312(void)
2818 +{
2819 + return !is_2315();
2820 +}
2821 +
2822 +#endif
2823 --- /dev/null
2824 +++ b/arch/mips/ar231x/devices.c
2825 @@ -0,0 +1,180 @@
2826 +#include <linux/kernel.h>
2827 +#include <linux/init.h>
2828 +#include <linux/serial.h>
2829 +#include <linux/serial_core.h>
2830 +#include <linux/serial_8250.h>
2831 +#include <linux/platform_device.h>
2832 +#include <asm/bootinfo.h>
2833 +
2834 +#include <ar231x_platform.h>
2835 +#include <ar231x.h>
2836 +#include "devices.h"
2837 +#include "ar5312.h"
2838 +#include "ar2315.h"
2839 +
2840 +struct ar231x_board_config ar231x_board;
2841 +int ar231x_devtype = DEV_TYPE_UNKNOWN;
2842 +
2843 +static struct resource ar231x_eth0_res[] = {
2844 + {
2845 + .name = "eth0_membase",
2846 + .flags = IORESOURCE_MEM,
2847 + },
2848 + {
2849 + .name = "eth0_mii",
2850 + .flags = IORESOURCE_MEM,
2851 + },
2852 + {
2853 + .name = "eth0_irq",
2854 + .flags = IORESOURCE_IRQ,
2855 + }
2856 +};
2857 +
2858 +static struct resource ar231x_eth1_res[] = {
2859 + {
2860 + .name = "eth1_membase",
2861 + .flags = IORESOURCE_MEM,
2862 + },
2863 + {
2864 + .name = "eth1_mii",
2865 + .flags = IORESOURCE_MEM,
2866 + },
2867 + {
2868 + .name = "eth1_irq",
2869 + .flags = IORESOURCE_IRQ,
2870 + }
2871 +};
2872 +
2873 +static struct platform_device ar231x_eth[] = {
2874 + {
2875 + .id = 0,
2876 + .name = "ar231x-eth",
2877 + .resource = ar231x_eth0_res,
2878 + .num_resources = ARRAY_SIZE(ar231x_eth0_res)
2879 + },
2880 + {
2881 + .id = 1,
2882 + .name = "ar231x-eth",
2883 + .resource = ar231x_eth1_res,
2884 + .num_resources = ARRAY_SIZE(ar231x_eth1_res)
2885 + }
2886 +};
2887 +
2888 +static struct resource ar231x_wmac0_res[] = {
2889 + {
2890 + .name = "wmac0_membase",
2891 + .flags = IORESOURCE_MEM,
2892 + },
2893 + {
2894 + .name = "wmac0_irq",
2895 + .flags = IORESOURCE_IRQ,
2896 + }
2897 +};
2898 +
2899 +static struct resource ar231x_wmac1_res[] = {
2900 + {
2901 + .name = "wmac1_membase",
2902 + .flags = IORESOURCE_MEM,
2903 + },
2904 + {
2905 + .name = "wmac1_irq",
2906 + .flags = IORESOURCE_IRQ,
2907 + }
2908 +};
2909 +
2910 +static struct platform_device ar231x_wmac[] = {
2911 + {
2912 + .id = 0,
2913 + .name = "ar231x-wmac",
2914 + .resource = ar231x_wmac0_res,
2915 + .num_resources = ARRAY_SIZE(ar231x_wmac0_res),
2916 + .dev.platform_data = &ar231x_board,
2917 + },
2918 + {
2919 + .id = 1,
2920 + .name = "ar231x-wmac",
2921 + .resource = ar231x_wmac1_res,
2922 + .num_resources = ARRAY_SIZE(ar231x_wmac1_res),
2923 + .dev.platform_data = &ar231x_board,
2924 + },
2925 +};
2926 +
2927 +static const char * const devtype_strings[] = {
2928 + [DEV_TYPE_AR5312] = "Atheros AR5312",
2929 + [DEV_TYPE_AR2312] = "Atheros AR2312",
2930 + [DEV_TYPE_AR2313] = "Atheros AR2313",
2931 + [DEV_TYPE_AR2315] = "Atheros AR2315",
2932 + [DEV_TYPE_AR2316] = "Atheros AR2316",
2933 + [DEV_TYPE_AR2317] = "Atheros AR2317",
2934 + [DEV_TYPE_UNKNOWN] = "Atheros (unknown)",
2935 +};
2936 +
2937 +const char *get_system_type(void)
2938 +{
2939 + if ((ar231x_devtype >= ARRAY_SIZE(devtype_strings)) ||
2940 + !devtype_strings[ar231x_devtype])
2941 + return devtype_strings[DEV_TYPE_UNKNOWN];
2942 + return devtype_strings[ar231x_devtype];
2943 +}
2944 +
2945 +int __init
2946 +ar231x_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
2947 + int irq, void *pdata)
2948 +{
2949 + struct resource *res;
2950 +
2951 + ar231x_eth[nr].dev.platform_data = pdata;
2952 + res = &ar231x_eth[nr].resource[0];
2953 + res->start = base;
2954 + res->end = base + 0x2000 - 1;
2955 + res++;
2956 + res->name = mii_name;
2957 + res->start = mii_base;
2958 + res->end = mii_base + 8 - 1;
2959 + res++;
2960 + res->start = irq;
2961 + res->end = irq;
2962 + return platform_device_register(&ar231x_eth[nr]);
2963 +}
2964 +
2965 +void __init
2966 +ar231x_serial_setup(u32 mapbase, int irq, unsigned int uartclk)
2967 +{
2968 + struct uart_port s;
2969 +
2970 + memset(&s, 0, sizeof(s));
2971 +
2972 + s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP;
2973 + s.iotype = UPIO_MEM32;
2974 + s.irq = irq;
2975 + s.regshift = 2;
2976 + s.mapbase = mapbase;
2977 + s.uartclk = uartclk;
2978 +
2979 + early_serial_setup(&s);
2980 +}
2981 +
2982 +int __init
2983 +ar231x_add_wmac(int nr, u32 base, int irq)
2984 +{
2985 + struct resource *res;
2986 +
2987 + ar231x_wmac[nr].dev.platform_data = &ar231x_board;
2988 + res = &ar231x_wmac[nr].resource[0];
2989 + res->start = base;
2990 + res->end = base + 0x10000 - 1;
2991 + res++;
2992 + res->start = irq;
2993 + res->end = irq;
2994 + return platform_device_register(&ar231x_wmac[nr]);
2995 +}
2996 +
2997 +static int __init ar231x_register_devices(void)
2998 +{
2999 + ar5312_init_devices();
3000 + ar2315_init_devices();
3001 +
3002 + return 0;
3003 +}
3004 +
3005 +device_initcall(ar231x_register_devices);