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[openwrt/openwrt.git] / target / linux / atheros / patches-3.14 / 100-board.patch
1 --- a/arch/mips/Kconfig
2 +++ b/arch/mips/Kconfig
3 @@ -144,6 +144,19 @@ config BCM63XX
4 help
5 Support for BCM63XX based boards
6
7 +config ATHEROS_AR231X
8 + bool "Atheros 231x/531x SoC support"
9 + select CEVT_R4K
10 + select CSRC_R4K
11 + select DMA_NONCOHERENT
12 + select IRQ_CPU
13 + select SYS_HAS_CPU_MIPS32_R1
14 + select SYS_SUPPORTS_BIG_ENDIAN
15 + select SYS_SUPPORTS_32BIT_KERNEL
16 + select ARCH_REQUIRE_GPIOLIB
17 + help
18 + Support for AR231x and AR531x based boards
19 +
20 config MIPS_COBALT
21 bool "Cobalt Server"
22 select CEVT_R4K
23 @@ -795,6 +808,7 @@ config NLM_XLP_BOARD
24
25 endchoice
26
27 +source "arch/mips/ar231x/Kconfig"
28 source "arch/mips/alchemy/Kconfig"
29 source "arch/mips/ath79/Kconfig"
30 source "arch/mips/bcm47xx/Kconfig"
31 --- a/arch/mips/Kbuild.platforms
32 +++ b/arch/mips/Kbuild.platforms
33 @@ -6,6 +6,7 @@ platforms += ath79
34 platforms += bcm47xx
35 platforms += bcm63xx
36 platforms += cavium-octeon
37 +platforms += ar231x
38 platforms += cobalt
39 platforms += dec
40 platforms += emma
41 --- /dev/null
42 +++ b/arch/mips/ar231x/Platform
43 @@ -0,0 +1,6 @@
44 +#
45 +# Atheros AR531X/AR231X WiSoC
46 +#
47 +platform-$(CONFIG_ATHEROS_AR231X) += ar231x/
48 +cflags-$(CONFIG_ATHEROS_AR231X) += -I$(srctree)/arch/mips/include/asm/mach-ar231x
49 +load-$(CONFIG_ATHEROS_AR231X) += 0xffffffff80041000
50 --- /dev/null
51 +++ b/arch/mips/ar231x/Kconfig
52 @@ -0,0 +1,9 @@
53 +config ATHEROS_AR5312
54 + bool "Atheros 5312/2312+ support"
55 + depends on ATHEROS_AR231X
56 + default y
57 +
58 +config ATHEROS_AR2315
59 + bool "Atheros 2315+ support"
60 + depends on ATHEROS_AR231X
61 + default y
62 --- /dev/null
63 +++ b/arch/mips/ar231x/Makefile
64 @@ -0,0 +1,13 @@
65 +#
66 +# This file is subject to the terms and conditions of the GNU General Public
67 +# License. See the file "COPYING" in the main directory of this archive
68 +# for more details.
69 +#
70 +# Copyright (C) 2006 FON Technology, SL.
71 +# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
72 +# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
73 +#
74 +
75 +obj-y += board.o prom.o devices.o
76 +obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o
77 +obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o
78 --- /dev/null
79 +++ b/arch/mips/ar231x/board.c
80 @@ -0,0 +1,229 @@
81 +/*
82 + * This file is subject to the terms and conditions of the GNU General Public
83 + * License. See the file "COPYING" in the main directory of this archive
84 + * for more details.
85 + *
86 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
87 + * Copyright (C) 2006 FON Technology, SL.
88 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
89 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
90 + */
91 +
92 +#include <generated/autoconf.h>
93 +#include <linux/init.h>
94 +#include <linux/module.h>
95 +#include <linux/types.h>
96 +#include <linux/string.h>
97 +#include <linux/platform_device.h>
98 +#include <linux/kernel.h>
99 +#include <linux/random.h>
100 +#include <linux/etherdevice.h>
101 +#include <linux/irq.h>
102 +#include <linux/io.h>
103 +#include <asm/irq_cpu.h>
104 +#include <asm/reboot.h>
105 +#include <asm/bootinfo.h>
106 +#include <asm/time.h>
107 +
108 +#include <ar231x_platform.h>
109 +#include "devices.h"
110 +#include "ar5312.h"
111 +#include "ar2315.h"
112 +
113 +void (*ar231x_irq_dispatch)(void);
114 +
115 +static inline bool check_radio_magic(u8 *addr)
116 +{
117 + addr += 0x7a; /* offset for flash magic */
118 + return (addr[0] == 0x5a) && (addr[1] == 0xa5);
119 +}
120 +
121 +static inline bool check_notempty(u8 *addr)
122 +{
123 + return *(u32 *)addr != 0xffffffff;
124 +}
125 +
126 +static inline bool check_board_data(u8 *flash_limit, u8 *addr, bool broken)
127 +{
128 + /* config magic found */
129 + if (*((u32 *)addr) == AR231X_BD_MAGIC)
130 + return true;
131 +
132 + if (!broken)
133 + return false;
134 +
135 + if (check_radio_magic(addr + 0xf8))
136 + ar231x_board.radio = addr + 0xf8;
137 + if ((addr < flash_limit + 0x10000) &&
138 + check_radio_magic(addr + 0x10000))
139 + ar231x_board.radio = addr + 0x10000;
140 +
141 + if (ar231x_board.radio) {
142 + /* broken board data detected, use radio data to find the
143 + * offset, user will fix this */
144 + return true;
145 + }
146 +
147 + return false;
148 +}
149 +
150 +static u8 * __init find_board_config(u8 *flash_limit, bool broken)
151 +{
152 + u8 *addr;
153 + u8 *begin = flash_limit - 0x1000;
154 + u8 *end = flash_limit - 0x30000;
155 +
156 + for (addr = begin; addr >= end; addr -= 0x1000)
157 + if (check_board_data(flash_limit, addr, broken))
158 + return addr;
159 +
160 + return NULL;
161 +}
162 +
163 +static u8 * __init find_radio_config(u8 *flash_limit, u8 *bcfg)
164 +{
165 + u8 *rcfg, *begin, *end;
166 +
167 + /*
168 + * Now find the start of Radio Configuration data, using heuristics:
169 + * Search forward from Board Configuration data by 0x1000 bytes
170 + * at a time until we find non-0xffffffff.
171 + */
172 + begin = bcfg + 0x1000;
173 + end = flash_limit;
174 + for (rcfg = begin; rcfg < end; rcfg += 0x1000)
175 + if (check_notempty(rcfg) && check_radio_magic(rcfg))
176 + return rcfg;
177 +
178 + /* AR2316 relocates radio config to new location */
179 + begin = bcfg + 0xf8;
180 + end = flash_limit - 0x1000 + 0xf8;
181 + for (rcfg = begin; rcfg < end; rcfg += 0x1000)
182 + if (check_notempty(rcfg) && check_radio_magic(rcfg))
183 + return rcfg;
184 +
185 + pr_warn("WARNING: Could not find Radio Configuration data\n");
186 +
187 + return NULL;
188 +}
189 +
190 +int __init ar231x_find_config(u8 *flash_limit)
191 +{
192 + struct ar231x_boarddata *config;
193 + unsigned int rcfg_size;
194 + int broken_boarddata = 0;
195 + u8 *bcfg, *rcfg;
196 + u8 *board_data;
197 + u8 *radio_data;
198 + u8 *mac_addr;
199 + u32 offset;
200 +
201 + ar231x_board.config = NULL;
202 + ar231x_board.radio = NULL;
203 + /* Copy the board and radio data to RAM, because accessing the mapped
204 + * memory of the flash directly after booting is not safe */
205 +
206 + /* Try to find valid board and radio data */
207 + bcfg = find_board_config(flash_limit, false);
208 +
209 + /* If that fails, try to at least find valid radio data */
210 + if (!bcfg) {
211 + bcfg = find_board_config(flash_limit, true);
212 + broken_boarddata = 1;
213 + }
214 +
215 + if (!bcfg) {
216 + pr_warn("WARNING: No board configuration data found!\n");
217 + return -ENODEV;
218 + }
219 +
220 + board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
221 + ar231x_board.config = (struct ar231x_boarddata *)board_data;
222 + memcpy(board_data, bcfg, 0x100);
223 + if (broken_boarddata) {
224 + pr_warn("WARNING: broken board data detected\n");
225 + config = ar231x_board.config;
226 + if (is_zero_ether_addr(config->enet0_mac)) {
227 + pr_info("Fixing up empty mac addresses\n");
228 + config->reset_config_gpio = 0xffff;
229 + config->sys_led_gpio = 0xffff;
230 + random_ether_addr(config->wlan0_mac);
231 + config->wlan0_mac[0] &= ~0x06;
232 + random_ether_addr(config->enet0_mac);
233 + random_ether_addr(config->enet1_mac);
234 + }
235 + }
236 +
237 + /* Radio config starts 0x100 bytes after board config, regardless
238 + * of what the physical layout on the flash chip looks like */
239 +
240 + if (ar231x_board.radio)
241 + rcfg = (u8 *)ar231x_board.radio;
242 + else
243 + rcfg = find_radio_config(flash_limit, bcfg);
244 +
245 + if (!rcfg)
246 + return -ENODEV;
247 +
248 + radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
249 + ar231x_board.radio = radio_data;
250 + offset = radio_data - board_data;
251 + pr_info("Radio config found at offset 0x%x (0x%x)\n", rcfg - bcfg,
252 + offset);
253 + rcfg_size = BOARD_CONFIG_BUFSZ - offset;
254 + memcpy(radio_data, rcfg, rcfg_size);
255 +
256 + mac_addr = &radio_data[0x1d * 2];
257 + if (is_broadcast_ether_addr(mac_addr)) {
258 + pr_info("Radio MAC is blank; using board-data\n");
259 + ether_addr_copy(mac_addr, ar231x_board.config->wlan0_mac);
260 + }
261 +
262 + return 0;
263 +}
264 +
265 +static void ar231x_halt(void)
266 +{
267 + local_irq_disable();
268 + while (1)
269 + ;
270 +}
271 +
272 +void __init plat_mem_setup(void)
273 +{
274 + _machine_halt = ar231x_halt;
275 + pm_power_off = ar231x_halt;
276 +
277 + ar5312_plat_setup();
278 + ar2315_plat_setup();
279 +
280 + /* Disable data watchpoints */
281 + write_c0_watchlo0(0);
282 +}
283 +
284 +asmlinkage void plat_irq_dispatch(void)
285 +{
286 + ar231x_irq_dispatch();
287 +}
288 +
289 +void __init plat_time_init(void)
290 +{
291 + ar5312_time_init();
292 + ar2315_time_init();
293 +}
294 +
295 +unsigned int __cpuinit get_c0_compare_int(void)
296 +{
297 + return CP0_LEGACY_COMPARE_IRQ;
298 +}
299 +
300 +void __init arch_init_irq(void)
301 +{
302 + clear_c0_status(ST0_IM);
303 + mips_cpu_irq_init();
304 +
305 + /* Initialize interrupt controllers */
306 + ar5312_irq_init();
307 + ar2315_irq_init();
308 +}
309 +
310 --- /dev/null
311 +++ b/arch/mips/ar231x/prom.c
312 @@ -0,0 +1,37 @@
313 +/*
314 + * This file is subject to the terms and conditions of the GNU General Public
315 + * License. See the file "COPYING" in the main directory of this archive
316 + * for more details.
317 + *
318 + * Copyright MontaVista Software Inc
319 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
320 + * Copyright (C) 2006 FON Technology, SL.
321 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
322 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
323 + */
324 +
325 +/*
326 + * Prom setup file for ar231x
327 + */
328 +
329 +#include <linux/init.h>
330 +#include <generated/autoconf.h>
331 +#include <linux/kernel.h>
332 +#include <linux/string.h>
333 +#include <linux/mm.h>
334 +#include <linux/bootmem.h>
335 +
336 +#include <asm/bootinfo.h>
337 +#include <asm/addrspace.h>
338 +#include "ar5312.h"
339 +#include "ar2315.h"
340 +
341 +void __init prom_init(void)
342 +{
343 + ar5312_prom_init();
344 + ar2315_prom_init();
345 +}
346 +
347 +void __init prom_free_prom_memory(void)
348 +{
349 +}
350 --- /dev/null
351 +++ b/arch/mips/include/asm/mach-ar231x/ar231x_platform.h
352 @@ -0,0 +1,85 @@
353 +#ifndef __ASM_MACH_AR231X_PLATFORM_H
354 +#define __ASM_MACH_AR231X_PLATFORM_H
355 +
356 +#include <linux/etherdevice.h>
357 +
358 +/*
359 + * This is board-specific data that is stored in a "fixed" location in flash.
360 + * It is shared across operating systems, so it should not be changed lightly.
361 + * The main reason we need it is in order to extract the ethernet MAC
362 + * address(es).
363 + */
364 +struct ar231x_boarddata {
365 + u32 magic; /* board data is valid */
366 +#define AR231X_BD_MAGIC 0x35333131 /* "5311", for all 531x/231x platforms */
367 + u16 cksum; /* checksum (starting with BD_REV 2) */
368 + u16 rev; /* revision of this struct */
369 +#define BD_REV 4
370 + char board_name[64]; /* Name of board */
371 + u16 major; /* Board major number */
372 + u16 minor; /* Board minor number */
373 + u32 flags; /* Board configuration */
374 +#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
375 +#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
376 +#define BD_UART1 0x00000004 /* UART1 is stuffed */
377 +#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
378 +#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
379 +#define BD_SYSLED 0x00000020 /* System LED stuffed */
380 +#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
381 +#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
382 +#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
383 +#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
384 +#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ mem_cap for testing */
385 +#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
386 +#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
387 +#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
388 +#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
389 +#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
390 +#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
391 +#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
392 + u16 reset_config_gpio; /* Reset factory GPIO pin */
393 + u16 sys_led_gpio; /* System LED GPIO pin */
394 +
395 + u32 cpu_freq; /* CPU core frequency in Hz */
396 + u32 sys_freq; /* System frequency in Hz */
397 + u32 cnt_freq; /* Calculated C0_COUNT frequency */
398 +
399 + u8 wlan0_mac[ETH_ALEN];
400 + u8 enet0_mac[ETH_ALEN];
401 + u8 enet1_mac[ETH_ALEN];
402 +
403 + u16 pci_id; /* Pseudo PCIID for common code */
404 + u16 mem_cap; /* cap bank1 in MB */
405 +
406 + /* version 3 */
407 + u8 wlan1_mac[ETH_ALEN]; /* (ar5212) */
408 +};
409 +
410 +#define BOARD_CONFIG_BUFSZ 0x1000
411 +
412 +/*
413 + * Platform device information for the Wireless MAC
414 + */
415 +struct ar231x_board_config {
416 + u16 devid;
417 +
418 + /* board config data */
419 + struct ar231x_boarddata *config;
420 +
421 + /* radio calibration data */
422 + const char *radio;
423 +};
424 +
425 +/*
426 + * Platform device information for the Ethernet MAC
427 + */
428 +struct ar231x_eth {
429 + void (*reset_set)(u32);
430 + void (*reset_clear)(u32);
431 + u32 reset_mac;
432 + u32 reset_phy;
433 + struct ar231x_board_config *config;
434 + char *macaddr;
435 +};
436 +
437 +#endif /* __ASM_MACH_AR231X_PLATFORM_H */
438 --- /dev/null
439 +++ b/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h
440 @@ -0,0 +1,84 @@
441 +/*
442 + * Atheros AR231x/AR531x SoC specific CPU feature overrides
443 + *
444 + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
445 + *
446 + * This file was derived from: include/asm-mips/cpu-features.h
447 + * Copyright (C) 2003, 2004 Ralf Baechle
448 + * Copyright (C) 2004 Maciej W. Rozycki
449 + *
450 + * This program is free software; you can redistribute it and/or modify it
451 + * under the terms of the GNU General Public License version 2 as published
452 + * by the Free Software Foundation.
453 + *
454 + */
455 +#ifndef __ASM_MACH_AR231X_CPU_FEATURE_OVERRIDES_H
456 +#define __ASM_MACH_AR231X_CPU_FEATURE_OVERRIDES_H
457 +
458 +/*
459 + * The Atheros AR531x/AR231x SoCs have MIPS 4Kc/4KEc core.
460 + */
461 +#define cpu_has_tlb 1
462 +#define cpu_has_4kex 1
463 +#define cpu_has_3k_cache 0
464 +#define cpu_has_4k_cache 1
465 +#define cpu_has_tx39_cache 0
466 +#define cpu_has_sb1_cache 0
467 +#define cpu_has_fpu 0
468 +#define cpu_has_32fpr 0
469 +#define cpu_has_counter 1
470 +/* #define cpu_has_watch ? */
471 +/* #define cpu_has_divec ? */
472 +/* #define cpu_has_vce ? */
473 +/* #define cpu_has_cache_cdex_p ? */
474 +/* #define cpu_has_cache_cdex_s ? */
475 +/* #define cpu_has_prefetch ? */
476 +/* #define cpu_has_mcheck ? */
477 +#define cpu_has_ejtag 1
478 +
479 +#if !defined(CONFIG_ATHEROS_AR5312)
480 +# define cpu_has_llsc 1
481 +#else
482 +/*
483 + * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
484 + * ll/sc instructions.
485 + */
486 +# define cpu_has_llsc 0
487 +#endif
488 +
489 +#define cpu_has_mips16 0
490 +#define cpu_has_mdmx 0
491 +#define cpu_has_mips3d 0
492 +#define cpu_has_smartmips 0
493 +
494 +/* #define cpu_has_vtag_icache ? */
495 +/* #define cpu_has_dc_aliases ? */
496 +/* #define cpu_has_ic_fills_f_dc ? */
497 +/* #define cpu_has_pindexed_dcache ? */
498 +
499 +/* #define cpu_icache_snoops_remote_store ? */
500 +
501 +#define cpu_has_mips32r1 1
502 +
503 +#if !defined(CONFIG_ATHEROS_AR5312)
504 +# define cpu_has_mips32r2 1
505 +#endif
506 +
507 +#define cpu_has_mips64r1 0
508 +#define cpu_has_mips64r2 0
509 +
510 +#define cpu_has_dsp 0
511 +#define cpu_has_mipsmt 0
512 +
513 +/* #define cpu_has_nofpuex ? */
514 +#define cpu_has_64bits 0
515 +#define cpu_has_64bit_zero_reg 0
516 +#define cpu_has_64bit_gp_regs 0
517 +#define cpu_has_64bit_addresses 0
518 +
519 +/* #define cpu_has_inclusive_pcaches ? */
520 +
521 +/* #define cpu_dcache_line_size() ? */
522 +/* #define cpu_icache_line_size() ? */
523 +
524 +#endif /* __ASM_MACH_AR231X_CPU_FEATURE_OVERRIDES_H */
525 --- /dev/null
526 +++ b/arch/mips/include/asm/mach-ar231x/dma-coherence.h
527 @@ -0,0 +1,77 @@
528 +/*
529 + * This file is subject to the terms and conditions of the GNU General Public
530 + * License. See the file "COPYING" in the main directory of this archive
531 + * for more details.
532 + *
533 + * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
534 + * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
535 + *
536 + */
537 +#ifndef __ASM_MACH_AR231X_DMA_COHERENCE_H
538 +#define __ASM_MACH_AR231X_DMA_COHERENCE_H
539 +
540 +#define PCI_DMA_OFFSET 0x20000000
541 +
542 +#include <linux/device.h>
543 +
544 +static inline dma_addr_t ar231x_dev_offset(struct device *dev)
545 +{
546 +#ifdef CONFIG_PCI
547 + extern struct bus_type pci_bus_type;
548 +
549 + if (dev && dev->bus == &pci_bus_type)
550 + return PCI_DMA_OFFSET;
551 +#endif
552 + return 0;
553 +}
554 +
555 +static inline dma_addr_t
556 +plat_map_dma_mem(struct device *dev, void *addr, size_t size)
557 +{
558 + return virt_to_phys(addr) + ar231x_dev_offset(dev);
559 +}
560 +
561 +static inline dma_addr_t
562 +plat_map_dma_mem_page(struct device *dev, struct page *page)
563 +{
564 + return page_to_phys(page) + ar231x_dev_offset(dev);
565 +}
566 +
567 +static inline unsigned long
568 +plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
569 +{
570 + return dma_addr - ar231x_dev_offset(dev);
571 +}
572 +
573 +static inline void
574 +plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, size_t size,
575 + enum dma_data_direction direction)
576 +{
577 +}
578 +
579 +static inline int plat_dma_supported(struct device *dev, u64 mask)
580 +{
581 + return 1;
582 +}
583 +
584 +static inline void plat_extra_sync_for_device(struct device *dev)
585 +{
586 +}
587 +
588 +static inline int plat_dma_mapping_error(struct device *dev,
589 + dma_addr_t dma_addr)
590 +{
591 + return 0;
592 +}
593 +
594 +static inline int plat_device_is_coherent(struct device *dev)
595 +{
596 +#ifdef CONFIG_DMA_COHERENT
597 + return 1;
598 +#endif
599 +#ifdef CONFIG_DMA_NONCOHERENT
600 + return 0;
601 +#endif
602 +}
603 +
604 +#endif /* __ASM_MACH_AR231X_DMA_COHERENCE_H */
605 --- /dev/null
606 +++ b/arch/mips/include/asm/mach-ar231x/gpio.h
607 @@ -0,0 +1,30 @@
608 +#ifndef __ASM_MACH_AR231X_GPIO_H
609 +#define __ASM_MACH_AR231X_GPIO_H
610 +
611 +#include <ar231x.h>
612 +
613 +#define gpio_get_value __gpio_get_value
614 +#define gpio_set_value __gpio_set_value
615 +#define gpio_cansleep __gpio_cansleep
616 +
617 +/*
618 + * Wrappers for the generic GPIO layer
619 + */
620 +
621 +/* not sure if these are used? */
622 +
623 +/* Returns IRQ to attach for gpio. Unchecked function */
624 +static inline int gpio_to_irq(unsigned gpio)
625 +{
626 + return AR231X_GPIO_IRQ(gpio);
627 +}
628 +
629 +/* Returns gpio for IRQ attached. Unchecked function */
630 +static inline int irq_to_gpio(unsigned irq)
631 +{
632 + return irq - AR231X_GPIO_IRQ(0);
633 +}
634 +
635 +#include <asm-generic/gpio.h> /* cansleep wrappers */
636 +
637 +#endif /* __ASM_MACH_AR231X_GPIO_H */
638 --- /dev/null
639 +++ b/arch/mips/include/asm/mach-ar231x/reset.h
640 @@ -0,0 +1,6 @@
641 +#ifndef __ASM_MACH_AR231X_RESET_H
642 +#define __ASM_MACH_AR231X_RESET_H
643 +
644 +void ar231x_disable_reset_button(void);
645 +
646 +#endif /* __ASM_MACH_AR231X_RESET_H */
647 --- /dev/null
648 +++ b/arch/mips/include/asm/mach-ar231x/war.h
649 @@ -0,0 +1,25 @@
650 +/*
651 + * This file is subject to the terms and conditions of the GNU General Public
652 + * License. See the file "COPYING" in the main directory of this archive
653 + * for more details.
654 + *
655 + * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
656 + */
657 +#ifndef __ASM_MACH_AR231X_WAR_H
658 +#define __ASM_MACH_AR231X_WAR_H
659 +
660 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
661 +#define R4600_V1_HIT_CACHEOP_WAR 0
662 +#define R4600_V2_HIT_CACHEOP_WAR 0
663 +#define R5432_CP0_INTERRUPT_WAR 0
664 +#define BCM1250_M3_WAR 0
665 +#define SIBYTE_1956_WAR 0
666 +#define MIPS4K_ICACHE_REFILL_WAR 0
667 +#define MIPS_CACHE_SYNC_WAR 0
668 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
669 +#define RM9000_CDEX_SMP_WAR 0
670 +#define ICACHE_REFILLS_WORKAROUND_WAR 0
671 +#define R10000_LLSC_WAR 0
672 +#define MIPS34K_MISSED_ITLB_WAR 0
673 +
674 +#endif /* __ASM_MACH_AR231X_WAR_H */
675 --- /dev/null
676 +++ b/arch/mips/include/asm/mach-ar231x/ar2315_regs.h
677 @@ -0,0 +1,614 @@
678 +/*
679 + * Register definitions for AR2315+
680 + *
681 + * This file is subject to the terms and conditions of the GNU General Public
682 + * License. See the file "COPYING" in the main directory of this archive
683 + * for more details.
684 + *
685 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
686 + * Copyright (C) 2006 FON Technology, SL.
687 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
688 + * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
689 + */
690 +
691 +#ifndef __ASM_MACH_AR231X_AR2315_REGS_H
692 +#define __ASM_MACH_AR231X_AR2315_REGS_H
693 +
694 +/*
695 + * IRQs
696 + */
697 +#define AR2315_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
698 +#define AR2315_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
699 +#define AR2315_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
700 +#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
701 +#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
702 +
703 +/*
704 + * Miscellaneous interrupts, which share IP2.
705 + */
706 +#define AR2315_MISC_IRQ_NONE (AR231X_MISC_IRQ_BASE+0)
707 +#define AR2315_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+1)
708 +#define AR2315_MISC_IRQ_I2C_RSVD (AR231X_MISC_IRQ_BASE+2)
709 +#define AR2315_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+3)
710 +#define AR2315_MISC_IRQ_AHB (AR231X_MISC_IRQ_BASE+4)
711 +#define AR2315_MISC_IRQ_APB (AR231X_MISC_IRQ_BASE+5)
712 +#define AR2315_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+6)
713 +#define AR2315_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+7)
714 +#define AR2315_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+8)
715 +#define AR2315_MISC_IRQ_IR_RSVD (AR231X_MISC_IRQ_BASE+9)
716 +#define AR2315_MISC_IRQ_COUNT 10
717 +
718 +/*
719 + * Address map
720 + */
721 +#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */
722 +#define AR2315_WLAN0 0x10000000 /* Wireless MMR */
723 +#define AR2315_PCI 0x10100000 /* PCI MMR */
724 +#define AR2315_SDRAMCTL 0x10300000 /* SDRAM MMR */
725 +#define AR2315_LOCAL 0x10400000 /* LOCAL BUS MMR */
726 +#define AR2315_ENET0 0x10500000 /* ETHERNET MMR */
727 +#define AR2315_DSLBASE 0x11000000 /* RESET CONTROL MMR */
728 +#define AR2315_UART0 0x11100000 /* UART MMR */
729 +#define AR2315_SPI_MMR 0x11300000 /* SPI FLASH MMR */
730 +#define AR2315_PCIEXT 0x80000000 /* pci external */
731 +
732 +/* MII registers offset inside Ethernet MMR region */
733 +#define AR2315_ENET0_MII (AR2315_ENET0 + 0x14)
734 +
735 +/*
736 + * Cold reset register
737 + */
738 +#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000)
739 +
740 +#define AR2315_RESET_COLD_AHB 0x00000001
741 +#define AR2315_RESET_COLD_APB 0x00000002
742 +#define AR2315_RESET_COLD_CPU 0x00000004
743 +#define AR2315_RESET_COLD_CPUWARM 0x00000008
744 +#define AR2315_RESET_SYSTEM \
745 + (RESET_COLD_CPU |\
746 + RESET_COLD_APB |\
747 + RESET_COLD_AHB) /* full system */
748 +#define AR2317_RESET_SYSTEM 0x00000010
749 +
750 +/*
751 + * Reset register
752 + */
753 +#define AR2315_RESET (AR2315_DSLBASE + 0x0004)
754 +
755 +/* warm reset WLAN0 MAC */
756 +#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001
757 +/* warm reset WLAN0 BaseBand */
758 +#define AR2315_RESET_WARM_WLAN0_BB 0x00000002
759 +/* warm reset MPEG-TS */
760 +#define AR2315_RESET_MPEGTS_RSVD 0x00000004
761 +/* warm reset PCI ahb/dma */
762 +#define AR2315_RESET_PCIDMA 0x00000008
763 +/* warm reset memory controller */
764 +#define AR2315_RESET_MEMCTL 0x00000010
765 +/* warm reset local bus */
766 +#define AR2315_RESET_LOCAL 0x00000020
767 +/* warm reset I2C bus */
768 +#define AR2315_RESET_I2C_RSVD 0x00000040
769 +/* warm reset SPI interface */
770 +#define AR2315_RESET_SPI 0x00000080
771 +/* warm reset UART0 */
772 +#define AR2315_RESET_UART0 0x00000100
773 +/* warm reset IR interface */
774 +#define AR2315_RESET_IR_RSVD 0x00000200
775 +/* cold reset ENET0 phy */
776 +#define AR2315_RESET_EPHY0 0x00000400
777 +/* cold reset ENET0 mac */
778 +#define AR2315_RESET_ENET0 0x00000800
779 +
780 +/*
781 + * AHB master arbitration control
782 + */
783 +#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008)
784 +
785 +/* CPU, default */
786 +#define AR2315_ARB_CPU 0x00000001
787 +/* WLAN */
788 +#define AR2315_ARB_WLAN 0x00000002
789 +/* MPEG-TS */
790 +#define AR2315_ARB_MPEGTS_RSVD 0x00000004
791 +/* LOCAL */
792 +#define AR2315_ARB_LOCAL 0x00000008
793 +/* PCI */
794 +#define AR2315_ARB_PCI 0x00000010
795 +/* Ethernet */
796 +#define AR2315_ARB_ETHERNET 0x00000020
797 +/* retry policy, debug only */
798 +#define AR2315_ARB_RETRY 0x00000100
799 +
800 +/*
801 + * Config Register
802 + */
803 +#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c)
804 +
805 +/* EC - AHB bridge endianess */
806 +#define AR2315_CONFIG_AHB 0x00000001
807 +/* WLAN byteswap */
808 +#define AR2315_CONFIG_WLAN 0x00000002
809 +/* MPEG-TS byteswap */
810 +#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004
811 +/* PCI byteswap */
812 +#define AR2315_CONFIG_PCI 0x00000008
813 +/* Memory controller endianess */
814 +#define AR2315_CONFIG_MEMCTL 0x00000010
815 +/* Local bus byteswap */
816 +#define AR2315_CONFIG_LOCAL 0x00000020
817 +/* Ethernet byteswap */
818 +#define AR2315_CONFIG_ETHERNET 0x00000040
819 +
820 +/* CPU write buffer merge */
821 +#define AR2315_CONFIG_MERGE 0x00000200
822 +/* CPU big endian */
823 +#define AR2315_CONFIG_CPU 0x00000400
824 +#define AR2315_CONFIG_PCIAHB 0x00000800
825 +#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
826 +/* SPI byteswap */
827 +#define AR2315_CONFIG_SPI 0x00008000
828 +#define AR2315_CONFIG_CPU_DRAM 0x00010000
829 +#define AR2315_CONFIG_CPU_PCI 0x00020000
830 +#define AR2315_CONFIG_CPU_MMR 0x00040000
831 +#define AR2315_CONFIG_BIG 0x00000400
832 +
833 +/*
834 + * NMI control
835 + */
836 +#define AR2315_NMI_CTL (AR2315_DSLBASE + 0x0010)
837 +
838 +#define AR2315_NMI_EN 1
839 +
840 +/*
841 + * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR231X 1.0).
842 + */
843 +#define AR2315_SREV (AR2315_DSLBASE + 0x0014)
844 +
845 +#define AR2315_REV_MAJ 0x00f0
846 +#define AR2315_REV_MAJ_S 4
847 +#define AR2315_REV_MIN 0x000f
848 +#define AR2315_REV_MIN_S 0
849 +#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN)
850 +
851 +/*
852 + * Interface Enable
853 + */
854 +#define AR2315_IF_CTL (AR2315_DSLBASE + 0x0018)
855 +
856 +#define AR2315_IF_MASK 0x00000007
857 +#define AR2315_IF_DISABLED 0
858 +#define AR2315_IF_PCI 1
859 +#define AR2315_IF_TS_LOCAL 2
860 +/* only for emulation with separate pins */
861 +#define AR2315_IF_ALL 3
862 +#define AR2315_IF_LOCAL_HOST 0x00000008
863 +#define AR2315_IF_PCI_HOST 0x00000010
864 +#define AR2315_IF_PCI_INTR 0x00000020
865 +#define AR2315_IF_PCI_CLK_MASK 0x00030000
866 +#define AR2315_IF_PCI_CLK_INPUT 0
867 +#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
868 +#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
869 +#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
870 +#define AR2315_IF_PCI_CLK_SHIFT 16
871 +
872 +/*
873 + * APB Interrupt control
874 + */
875 +
876 +#define AR2315_ISR (AR2315_DSLBASE + 0x0020)
877 +#define AR2315_IMR (AR2315_DSLBASE + 0x0024)
878 +#define AR2315_GISR (AR2315_DSLBASE + 0x0028)
879 +
880 +#define AR2315_ISR_UART0 0x0001 /* high speed UART */
881 +#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */
882 +#define AR2315_ISR_SPI 0x0004 /* SPI bus */
883 +#define AR2315_ISR_AHB 0x0008 /* AHB error */
884 +#define AR2315_ISR_APB 0x0010 /* APB error */
885 +#define AR2315_ISR_TIMER 0x0020 /* timer */
886 +#define AR2315_ISR_GPIO 0x0040 /* GPIO */
887 +#define AR2315_ISR_WD 0x0080 /* watchdog */
888 +#define AR2315_ISR_IR_RSVD 0x0100 /* IR */
889 +
890 +#define AR2315_GISR_MISC 0x0001
891 +#define AR2315_GISR_WLAN0 0x0002
892 +#define AR2315_GISR_MPEGTS_RSVD 0x0004
893 +#define AR2315_GISR_LOCALPCI 0x0008
894 +#define AR2315_GISR_WMACPOLL 0x0010
895 +#define AR2315_GISR_TIMER 0x0020
896 +#define AR2315_GISR_ETHERNET 0x0040
897 +
898 +/*
899 + * Interrupt routing from IO to the processor IP bits
900 + * Define our inter mask and level
901 + */
902 +#define AR2315_INTR_MISCIO SR_IBIT3
903 +#define AR2315_INTR_WLAN0 SR_IBIT4
904 +#define AR2315_INTR_ENET0 SR_IBIT5
905 +#define AR2315_INTR_LOCALPCI SR_IBIT6
906 +#define AR2315_INTR_WMACPOLL SR_IBIT7
907 +#define AR2315_INTR_COMPARE SR_IBIT8
908 +
909 +/*
910 + * Timers
911 + */
912 +#define AR2315_TIMER (AR2315_DSLBASE + 0x0030)
913 +#define AR2315_RELOAD (AR2315_DSLBASE + 0x0034)
914 +#define AR2315_WD (AR2315_DSLBASE + 0x0038)
915 +#define AR2315_WDC (AR2315_DSLBASE + 0x003c)
916 +
917 +#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000
918 +#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */
919 +#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */
920 +
921 +/*
922 + * CPU Performance Counters
923 + */
924 +#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048)
925 +#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c)
926 +
927 +#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */
928 +#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */
929 +#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */
930 +#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */
931 +#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */
932 +#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */
933 +#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */
934 +
935 +#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */
936 +#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */
937 +#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */
938 +#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */
939 +#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */
940 +#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */
941 +#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */
942 +
943 +/*
944 + * AHB Error Reporting.
945 + */
946 +#define AR2315_AHB_ERR0 (AR2315_DSLBASE + 0x0050) /* error */
947 +#define AR2315_AHB_ERR1 (AR2315_DSLBASE + 0x0054) /* haddr */
948 +#define AR2315_AHB_ERR2 (AR2315_DSLBASE + 0x0058) /* hwdata */
949 +#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */
950 +#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */
951 +
952 +#define AHB_ERROR_DET 1 /* AHB Error has been detected, */
953 + /* write 1 to clear all bits in ERR0 */
954 +#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
955 +#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
956 +
957 +#define AR2315_PROCERR_HMAST 0x0000000f
958 +#define AR2315_PROCERR_HMAST_DFLT 0
959 +#define AR2315_PROCERR_HMAST_WMAC 1
960 +#define AR2315_PROCERR_HMAST_ENET 2
961 +#define AR2315_PROCERR_HMAST_PCIENDPT 3
962 +#define AR2315_PROCERR_HMAST_LOCAL 4
963 +#define AR2315_PROCERR_HMAST_CPU 5
964 +#define AR2315_PROCERR_HMAST_PCITGT 6
965 +
966 +#define AR2315_PROCERR_HMAST_S 0
967 +#define AR2315_PROCERR_HWRITE 0x00000010
968 +#define AR2315_PROCERR_HSIZE 0x00000060
969 +#define AR2315_PROCERR_HSIZE_S 5
970 +#define AR2315_PROCERR_HTRANS 0x00000180
971 +#define AR2315_PROCERR_HTRANS_S 7
972 +#define AR2315_PROCERR_HBURST 0x00000e00
973 +#define AR2315_PROCERR_HBURST_S 9
974 +
975 +/*
976 + * Clock Control
977 + */
978 +#define AR2315_PLLC_CTL (AR2315_DSLBASE + 0x0064)
979 +#define AR2315_PLLV_CTL (AR2315_DSLBASE + 0x0068)
980 +#define AR2315_CPUCLK (AR2315_DSLBASE + 0x006c)
981 +#define AR2315_AMBACLK (AR2315_DSLBASE + 0x0070)
982 +#define AR2315_SYNCCLK (AR2315_DSLBASE + 0x0074)
983 +#define AR2315_DSL_SLEEP_CTL (AR2315_DSLBASE + 0x0080)
984 +#define AR2315_DSL_SLEEP_DUR (AR2315_DSLBASE + 0x0084)
985 +
986 +/* PLLc Control fields */
987 +#define PLLC_REF_DIV_M 0x00000003
988 +#define PLLC_REF_DIV_S 0
989 +#define PLLC_FDBACK_DIV_M 0x0000007C
990 +#define PLLC_FDBACK_DIV_S 2
991 +#define PLLC_ADD_FDBACK_DIV_M 0x00000080
992 +#define PLLC_ADD_FDBACK_DIV_S 7
993 +#define PLLC_CLKC_DIV_M 0x0001c000
994 +#define PLLC_CLKC_DIV_S 14
995 +#define PLLC_CLKM_DIV_M 0x00700000
996 +#define PLLC_CLKM_DIV_S 20
997 +
998 +/* CPU CLK Control fields */
999 +#define CPUCLK_CLK_SEL_M 0x00000003
1000 +#define CPUCLK_CLK_SEL_S 0
1001 +#define CPUCLK_CLK_DIV_M 0x0000000c
1002 +#define CPUCLK_CLK_DIV_S 2
1003 +
1004 +/* AMBA CLK Control fields */
1005 +#define AMBACLK_CLK_SEL_M 0x00000003
1006 +#define AMBACLK_CLK_SEL_S 0
1007 +#define AMBACLK_CLK_DIV_M 0x0000000c
1008 +#define AMBACLK_CLK_DIV_S 2
1009 +
1010 +/*
1011 + * GPIO
1012 + */
1013 +#define AR2315_GPIO_DI (AR2315_DSLBASE + 0x0088)
1014 +#define AR2315_GPIO_DO (AR2315_DSLBASE + 0x0090)
1015 +#define AR2315_GPIO_DIR (AR2315_DSLBASE + 0x0098)
1016 +#define AR2315_GPIO_INT (AR2315_DSLBASE + 0x00a0)
1017 +
1018 +#define AR2315_GPIO_DIR_M(x) (1 << (x)) /* mask for i/o */
1019 +#define AR2315_GPIO_DIR_O(x) (1 << (x)) /* output */
1020 +#define AR2315_GPIO_DIR_I(x) (0) /* input */
1021 +
1022 +#define AR2315_GPIO_INT_S(x) (x) /* interrupt enable */
1023 +#define AR2315_GPIO_INT_M (0x3F) /* mask for int */
1024 +#define AR2315_GPIO_INT_LVL(x) ((x) << 6) /* interrupt level */
1025 +#define AR2315_GPIO_INT_LVL_M ((0x3) << 6) /* mask for int level */
1026 +
1027 +#define AR2315_GPIO_INT_MAX_Y 1 /* Maximum value of Y for
1028 + * AR2315_GPIO_INT_* macros */
1029 +#define AR2315_GPIO_INT_LVL_OFF 0 /* Triggerring off */
1030 +#define AR2315_GPIO_INT_LVL_LOW 1 /* Low Level Triggered */
1031 +#define AR2315_GPIO_INT_LVL_HIGH 2 /* High Level Triggered */
1032 +#define AR2315_GPIO_INT_LVL_EDGE 3 /* Edge Triggered */
1033 +
1034 +#define AR2315_RESET_GPIO 5
1035 +#define AR2315_NUM_GPIO 22
1036 +
1037 +/*
1038 + * PCI Clock Control
1039 + */
1040 +#define AR2315_PCICLK (AR2315_DSLBASE + 0x00a4)
1041 +
1042 +#define AR2315_PCICLK_INPUT_M 0x3
1043 +#define AR2315_PCICLK_INPUT_S 0
1044 +
1045 +#define AR2315_PCICLK_PLLC_CLKM 0
1046 +#define AR2315_PCICLK_PLLC_CLKM1 1
1047 +#define AR2315_PCICLK_PLLC_CLKC 2
1048 +#define AR2315_PCICLK_REF_CLK 3
1049 +
1050 +#define AR2315_PCICLK_DIV_M 0xc
1051 +#define AR2315_PCICLK_DIV_S 2
1052 +
1053 +#define AR2315_PCICLK_IN_FREQ 0
1054 +#define AR2315_PCICLK_IN_FREQ_DIV_6 1
1055 +#define AR2315_PCICLK_IN_FREQ_DIV_8 2
1056 +#define AR2315_PCICLK_IN_FREQ_DIV_10 3
1057 +
1058 +/*
1059 + * Observation Control Register
1060 + */
1061 +#define AR2315_OCR (AR2315_DSLBASE + 0x00b0)
1062 +#define OCR_GPIO0_IRIN 0x0040
1063 +#define OCR_GPIO1_IROUT 0x0080
1064 +#define OCR_GPIO3_RXCLR 0x0200
1065 +
1066 +/*
1067 + * General Clock Control
1068 + */
1069 +
1070 +#define AR2315_MISCCLK (AR2315_DSLBASE + 0x00b4)
1071 +#define MISCCLK_PLLBYPASS_EN 0x00000001
1072 +#define MISCCLK_PROCREFCLK 0x00000002
1073 +
1074 +/*
1075 + * SDRAM Controller
1076 + * - No read or write buffers are included.
1077 + */
1078 +#define AR2315_MEM_CFG (AR2315_SDRAMCTL + 0x00)
1079 +#define AR2315_MEM_CTRL (AR2315_SDRAMCTL + 0x0c)
1080 +#define AR2315_MEM_REF (AR2315_SDRAMCTL + 0x10)
1081 +
1082 +#define SDRAM_DATA_WIDTH_M 0x00006000
1083 +#define SDRAM_DATA_WIDTH_S 13
1084 +
1085 +#define SDRAM_COL_WIDTH_M 0x00001E00
1086 +#define SDRAM_COL_WIDTH_S 9
1087 +
1088 +#define SDRAM_ROW_WIDTH_M 0x000001E0
1089 +#define SDRAM_ROW_WIDTH_S 5
1090 +
1091 +#define SDRAM_BANKADDR_BITS_M 0x00000018
1092 +#define SDRAM_BANKADDR_BITS_S 3
1093 +
1094 +/*
1095 + * PCI Bus Interface Registers
1096 + */
1097 +#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008)
1098 +#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1099 +
1100 +#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c)
1101 +#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
1102 +#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* mem or config cycles */
1103 +#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
1104 +#define AR2315_PCIMISC_RST_MODE 0x00000030
1105 +#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
1106 +#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
1107 +#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
1108 +#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
1109 +#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
1110 +#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
1111 +#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
1112 +#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache
1113 + * disable */
1114 +
1115 +#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010)
1116 +
1117 +#define AR2315_PCI_UNCACHE_CFG (AR2315_PCI + 0x0014)
1118 +
1119 +#define AR2315_PCI_IN_EN (AR2315_PCI + 0x0100)
1120 +#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
1121 +#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
1122 +#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
1123 +#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
1124 +
1125 +#define AR2315_PCI_IN_DIS (AR2315_PCI + 0x0104)
1126 +#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
1127 +#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
1128 +#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
1129 +#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
1130 +
1131 +#define AR2315_PCI_IN_PTR (AR2315_PCI + 0x0200)
1132 +
1133 +#define AR2315_PCI_OUT_EN (AR2315_PCI + 0x0400)
1134 +#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
1135 +
1136 +#define AR2315_PCI_OUT_DIS (AR2315_PCI + 0x0404)
1137 +#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
1138 +
1139 +#define AR2315_PCI_OUT_PTR (AR2315_PCI + 0x0408)
1140 +
1141 +#define AR2315_PCI_INT_STATUS (AR2315_PCI + 0x0500) /* write one to clr */
1142 +#define AR2315_PCI_TXINT 0x00000001 /* Desc In Completed */
1143 +#define AR2315_PCI_TXOK 0x00000002 /* Desc In OK */
1144 +#define AR2315_PCI_TXERR 0x00000004 /* Desc In ERR */
1145 +#define AR2315_PCI_TXEOL 0x00000008 /* Desc In End-of-List */
1146 +#define AR2315_PCI_RXINT 0x00000010 /* Desc Out Completed */
1147 +#define AR2315_PCI_RXOK 0x00000020 /* Desc Out OK */
1148 +#define AR2315_PCI_RXERR 0x00000040 /* Desc Out ERR */
1149 +#define AR2315_PCI_RXEOL 0x00000080 /* Desc Out EOL */
1150 +#define AR2315_PCI_TXOOD 0x00000200 /* Desc In Out-of-Desc */
1151 +#define AR2315_PCI_MASK 0x0000FFFF /* Desc Mask */
1152 +#define AR2315_PCI_EXT_INT 0x02000000
1153 +#define AR2315_PCI_ABORT_INT 0x04000000
1154 +
1155 +#define AR2315_PCI_INT_MASK (AR2315_PCI + 0x0504) /* same as INT_STATUS */
1156 +
1157 +#define AR2315_PCI_INTEN_REG (AR2315_PCI + 0x0508)
1158 +#define AR2315_PCI_INT_DISABLE 0x00 /* disable pci interrupts */
1159 +#define AR2315_PCI_INT_ENABLE 0x01 /* enable pci interrupts */
1160 +
1161 +#define AR2315_PCI_HOST_IN_EN (AR2315_PCI + 0x0800)
1162 +#define AR2315_PCI_HOST_IN_DIS (AR2315_PCI + 0x0804)
1163 +#define AR2315_PCI_HOST_IN_PTR (AR2315_PCI + 0x0810)
1164 +#define AR2315_PCI_HOST_OUT_EN (AR2315_PCI + 0x0900)
1165 +#define AR2315_PCI_HOST_OUT_DIS (AR2315_PCI + 0x0904)
1166 +#define AR2315_PCI_HOST_OUT_PTR (AR2315_PCI + 0x0908)
1167 +
1168 +/*
1169 + * Local Bus Interface Registers
1170 + */
1171 +#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000)
1172 +#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
1173 +#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
1174 +#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
1175 +#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
1176 +#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
1177 +#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
1178 +#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
1179 +#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
1180 +#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
1181 +#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
1182 +#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
1183 +#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
1184 +#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
1185 +#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
1186 +#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
1187 +#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
1188 +#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
1189 +#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
1190 +#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
1191 +#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
1192 +#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
1193 +#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */
1194 +#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
1195 +#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
1196 +#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
1197 +
1198 +#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004)
1199 +#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */
1200 +
1201 +#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008)
1202 +#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1203 +
1204 +#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C)
1205 +#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
1206 +#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
1207 +#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
1208 +#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
1209 +#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
1210 +#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80
1211 +#define AR2315_LBM_TIMEOUT_SHFT 7
1212 +#define AR2315_LBM_PORTMUX 0x07000000
1213 +
1214 +#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010)
1215 +
1216 +#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100)
1217 +#define AR2315_LB_TXEN_0 0x01
1218 +#define AR2315_LB_TXEN_1 0x02
1219 +#define AR2315_LB_TXEN_2 0x04
1220 +#define AR2315_LB_TXEN_3 0x08
1221 +
1222 +#define AR2315_LB_TX_CHAIN_DIS (AR2315_LOCAL + 0x0104)
1223 +#define AR2315_LB_TX_DESC_PTR (AR2315_LOCAL + 0x0200)
1224 +
1225 +#define AR2315_LB_RX_CHAIN_EN (AR2315_LOCAL + 0x0400)
1226 +#define AR2315_LB_RXEN 0x01
1227 +
1228 +#define AR2315_LB_RX_CHAIN_DIS (AR2315_LOCAL + 0x0404)
1229 +#define AR2315_LB_RX_DESC_PTR (AR2315_LOCAL + 0x0408)
1230 +
1231 +#define AR2315_LB_INT_STATUS (AR2315_LOCAL + 0x0500)
1232 +#define AR2315_INT_TX_DESC 0x0001
1233 +#define AR2315_INT_TX_OK 0x0002
1234 +#define AR2315_INT_TX_ERR 0x0004
1235 +#define AR2315_INT_TX_EOF 0x0008
1236 +#define AR2315_INT_RX_DESC 0x0010
1237 +#define AR2315_INT_RX_OK 0x0020
1238 +#define AR2315_INT_RX_ERR 0x0040
1239 +#define AR2315_INT_RX_EOF 0x0080
1240 +#define AR2315_INT_TX_TRUNC 0x0100
1241 +#define AR2315_INT_TX_STARVE 0x0200
1242 +#define AR2315_INT_LB_TIMEOUT 0x0400
1243 +#define AR2315_INT_LB_ERR 0x0800
1244 +#define AR2315_INT_MBOX_WR 0x1000
1245 +#define AR2315_INT_MBOX_RD 0x2000
1246 +
1247 +/* Bit definitions for INT MASK are the same as INT_STATUS */
1248 +#define AR2315_LB_INT_MASK (AR2315_LOCAL + 0x0504)
1249 +
1250 +#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508)
1251 +#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600)
1252 +
1253 +/*
1254 + * IR Interface Registers
1255 + */
1256 +#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000)
1257 +
1258 +#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */
1259 +
1260 +#define AR2315_IR_CONTROL (AR2315_IR + 0x0800)
1261 +#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */
1262 +#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */
1263 +#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor */
1264 +#define AR2315_IRCTL_SAMPLECLK_SHFT 1
1265 +#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk div */
1266 +#define AR2315_IRCTL_OUTPUTCLK_SHFT 14
1267 +
1268 +#define AR2315_IR_STATUS (AR2315_IR + 0x0804)
1269 +#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */
1270 +#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */
1271 +
1272 +#define AR2315_IR_CONFIG (AR2315_IR + 0x0808)
1273 +#define AR2315_IRCFG_INVIN 0x00000001 /* invert in polarity */
1274 +#define AR2315_IRCFG_INVOUT 0x00000002 /* invert out polarity */
1275 +#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */
1276 +#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0
1277 +#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100
1278 +#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00
1279 +#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000
1280 +#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000
1281 +#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000
1282 +
1283 +#define HOST_PCI_DEV_ID 3
1284 +#define HOST_PCI_MBAR0 0x10000000
1285 +#define HOST_PCI_MBAR1 0x20000000
1286 +#define HOST_PCI_MBAR2 0x30000000
1287 +
1288 +#define HOST_PCI_SDRAM_BASEADDR HOST_PCI_MBAR1
1289 +#define PCI_DEVICE_MEM_SPACE 0x800000
1290 +
1291 +#endif /* __ASM_MACH_AR231X_AR2315_REGS_H */
1292 --- /dev/null
1293 +++ b/arch/mips/include/asm/mach-ar231x/ar5312_regs.h
1294 @@ -0,0 +1,249 @@
1295 +/*
1296 + * This file is subject to the terms and conditions of the GNU General Public
1297 + * License. See the file "COPYING" in the main directory of this archive
1298 + * for more details.
1299 + *
1300 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1301 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1302 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1303 + */
1304 +
1305 +#ifndef __ASM_MACH_AR231X_AR5312_REGS_H
1306 +#define __ASM_MACH_AR231X_AR5312_REGS_H
1307 +
1308 +#include <asm/addrspace.h>
1309 +
1310 +/*
1311 + * IRQs
1312 + */
1313 +#define AR5312_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
1314 +#define AR5312_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
1315 +#define AR5312_IRQ_ENET1_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
1316 +#define AR5312_IRQ_WLAN1_INTRS (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
1317 +#define AR5312_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
1318 +
1319 +/*
1320 + * Miscellaneous interrupts, which share IP6.
1321 + */
1322 +#define AR5312_MISC_IRQ_NONE (AR231X_MISC_IRQ_BASE+0)
1323 +#define AR5312_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+1)
1324 +#define AR5312_MISC_IRQ_AHB_PROC (AR231X_MISC_IRQ_BASE+2)
1325 +#define AR5312_MISC_IRQ_AHB_DMA (AR231X_MISC_IRQ_BASE+3)
1326 +#define AR5312_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+4)
1327 +#define AR5312_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+5)
1328 +#define AR5312_MISC_IRQ_UART0_DMA (AR231X_MISC_IRQ_BASE+6)
1329 +#define AR5312_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+7)
1330 +#define AR5312_MISC_IRQ_LOCAL (AR231X_MISC_IRQ_BASE+8)
1331 +#define AR5312_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+9)
1332 +#define AR5312_MISC_IRQ_COUNT 10
1333 +
1334 +/*
1335 + * Address Map
1336 + */
1337 +#define AR5312_WLAN0 0x18000000
1338 +#define AR5312_WLAN1 0x18500000
1339 +#define AR5312_ENET0 0x18100000
1340 +#define AR5312_ENET1 0x18200000
1341 +#define AR5312_SDRAMCTL 0x18300000
1342 +#define AR5312_FLASHCTL 0x18400000
1343 +#define AR5312_APBBASE 0x1c000000
1344 +#define AR5312_UART0 0x1c000000 /* UART MMR */
1345 +#define AR5312_FLASH 0x1e000000
1346 +
1347 +/*
1348 + * AR5312_NUM_ENET_MAC defines the number of ethernet MACs that
1349 + * should be considered available. The AR5312 supports 2 enet MACS,
1350 + * even though many reference boards only actually use 1 of them
1351 + * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch.
1352 + * The AR2312 supports 1 enet MAC.
1353 + */
1354 +#define AR5312_NUM_ENET_MAC 2
1355 +
1356 +/*
1357 + * Need these defines to determine true number of ethernet MACs
1358 + */
1359 +#define AR5312_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
1360 +#define AR5312_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
1361 +#define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
1362 +
1363 +/* MII registers offset inside Ethernet MMR region */
1364 +#define AR5312_ENET0_MII (AR5312_ENET0 + 0x14)
1365 +#define AR5312_ENET1_MII (AR5312_ENET1 + 0x14)
1366 +
1367 +/*
1368 + * AR5312_NUM_WMAC defines the number of Wireless MACs that\
1369 + * should be considered available.
1370 + */
1371 +#define AR5312_NUM_WMAC 2
1372 +
1373 +/* Reset/Timer Block Address Map */
1374 +#define AR5312_RESETTMR (AR5312_APBBASE + 0x3000)
1375 +#define AR5312_TIMER (AR5312_RESETTMR + 0x0000) /* countdown timer */
1376 +#define AR5312_WD_CTRL (AR5312_RESETTMR + 0x0008) /* watchdog cntrl */
1377 +#define AR5312_WD_TIMER (AR5312_RESETTMR + 0x000c) /* watchdog timer */
1378 +#define AR5312_ISR (AR5312_RESETTMR + 0x0010) /* Intr Status Reg */
1379 +#define AR5312_IMR (AR5312_RESETTMR + 0x0014) /* Intr Mask Reg */
1380 +#define AR5312_RESET (AR5312_RESETTMR + 0x0020)
1381 +#define AR5312_CLOCKCTL1 (AR5312_RESETTMR + 0x0064)
1382 +#define AR5312_SCRATCH (AR5312_RESETTMR + 0x006c)
1383 +#define AR5312_PROCADDR (AR5312_RESETTMR + 0x0070)
1384 +#define AR5312_PROC1 (AR5312_RESETTMR + 0x0074)
1385 +#define AR5312_DMAADDR (AR5312_RESETTMR + 0x0078)
1386 +#define AR5312_DMA1 (AR5312_RESETTMR + 0x007c)
1387 +#define AR5312_ENABLE (AR5312_RESETTMR + 0x0080) /* interface enb */
1388 +#define AR5312_REV (AR5312_RESETTMR + 0x0090) /* revision */
1389 +
1390 +/* AR5312_WD_CTRL register bit field definitions */
1391 +#define AR5312_WD_CTRL_IGNORE_EXPIRATION 0x0000
1392 +#define AR5312_WD_CTRL_NMI 0x0001
1393 +#define AR5312_WD_CTRL_RESET 0x0002
1394 +
1395 +/* AR5312_ISR register bit field definitions */
1396 +#define AR5312_ISR_NONE 0x0000
1397 +#define AR5312_ISR_TIMER 0x0001
1398 +#define AR5312_ISR_AHBPROC 0x0002
1399 +#define AR5312_ISR_AHBDMA 0x0004
1400 +#define AR5312_ISR_GPIO 0x0008
1401 +#define AR5312_ISR_UART0 0x0010
1402 +#define AR5312_ISR_UART0DMA 0x0020
1403 +#define AR5312_ISR_WD 0x0040
1404 +#define AR5312_ISR_LOCAL 0x0080
1405 +
1406 +/* AR5312_RESET register bit field definitions */
1407 +#define AR5312_RESET_SYSTEM 0x00000001 /* cold reset full system */
1408 +#define AR5312_RESET_PROC 0x00000002 /* cold reset MIPS core */
1409 +#define AR5312_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
1410 +#define AR5312_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
1411 +#define AR5312_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
1412 +#define AR5312_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
1413 +#define AR5312_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
1414 +#define AR5312_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */
1415 +#define AR5312_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
1416 +#define AR5312_RESET_APB 0x00000400 /* cold reset APB (ar5312) */
1417 +#define AR5312_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
1418 +#define AR5312_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
1419 +#define AR5312_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */
1420 +#define AR5312_RESET_NMI 0x00010000 /* send an NMI to the processor */
1421 +#define AR5312_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */
1422 +#define AR5312_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */
1423 +#define AR5312_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
1424 +#define AR5312_RESET_WDOG 0x00100000 /* last reset was a watchdog */
1425 +
1426 +#define AR5312_RESET_WMAC0_BITS \
1427 + (AR5312_RESET_WLAN0 |\
1428 + AR5312_RESET_WARM_WLAN0_MAC |\
1429 + AR5312_RESET_WARM_WLAN0_BB)
1430 +
1431 +#define AR5312_RESET_WMAC1_BITS \
1432 + (AR5312_RESET_WLAN1 |\
1433 + AR5312_RESET_WARM_WLAN1_MAC |\
1434 + AR5312_RESET_WARM_WLAN1_BB)
1435 +
1436 +/* AR5312_CLOCKCTL1 register bit field definitions */
1437 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1438 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1439 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1440 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1441 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1442 +
1443 +/* Valid for AR5312 and AR2312 */
1444 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1445 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1446 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1447 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1448 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1449 +
1450 +/* Valid for AR2313 */
1451 +#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
1452 +#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
1453 +#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
1454 +#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
1455 +#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
1456 +
1457 +/* AR5312_ENABLE register bit field definitions */
1458 +#define AR5312_ENABLE_WLAN0 0x0001
1459 +#define AR5312_ENABLE_ENET0 0x0002
1460 +#define AR5312_ENABLE_ENET1 0x0004
1461 +#define AR5312_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */
1462 +#define AR5312_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */
1463 +#define AR5312_ENABLE_WLAN1 \
1464 + (AR5312_ENABLE_UART_AND_WLAN1_PIO |\
1465 + AR5312_ENABLE_WLAN1_DMA)
1466 +
1467 +/* AR5312_REV register bit field definitions */
1468 +#define AR5312_REV_WMAC_MAJ 0xf000
1469 +#define AR5312_REV_WMAC_MAJ_S 12
1470 +#define AR5312_REV_WMAC_MIN 0x0f00
1471 +#define AR5312_REV_WMAC_MIN_S 8
1472 +#define AR5312_REV_MAJ 0x00f0
1473 +#define AR5312_REV_MAJ_S 4
1474 +#define AR5312_REV_MIN 0x000f
1475 +#define AR5312_REV_MIN_S 0
1476 +#define AR5312_REV_CHIP (AR5312_REV_MAJ|AR5312_REV_MIN)
1477 +
1478 +/* Major revision numbers, bits 7..4 of Revision ID register */
1479 +#define AR5312_REV_MAJ_AR5312 0x4
1480 +#define AR5312_REV_MAJ_AR2313 0x5
1481 +
1482 +/* Minor revision numbers, bits 3..0 of Revision ID register */
1483 +#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
1484 +#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
1485 +
1486 +/* AR5312_FLASHCTL register bit field definitions */
1487 +#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */
1488 +#define FLASHCTL_IDCY_S 0
1489 +#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
1490 +#define FLASHCTL_WST1_S 5
1491 +#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
1492 +#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
1493 +#define FLASHCTL_WST2_S 11
1494 +#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */
1495 +#define FLASHCTL_AC_S 16
1496 +#define FLASHCTL_AC_128K 0x00000000
1497 +#define FLASHCTL_AC_256K 0x00010000
1498 +#define FLASHCTL_AC_512K 0x00020000
1499 +#define FLASHCTL_AC_1M 0x00030000
1500 +#define FLASHCTL_AC_2M 0x00040000
1501 +#define FLASHCTL_AC_4M 0x00050000
1502 +#define FLASHCTL_AC_8M 0x00060000
1503 +#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
1504 +#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
1505 +#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */
1506 +#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */
1507 +#define FLASHCTL_WP 0x04000000 /* Write protect */
1508 +#define FLASHCTL_BM 0x08000000 /* Burst mode */
1509 +#define FLASHCTL_MW 0x30000000 /* Memory width */
1510 +#define FLASHCTL_MW8 0x00000000 /* Memory width x8 */
1511 +#define FLASHCTL_MW16 0x10000000 /* Memory width x16 */
1512 +#define FLASHCTL_MW32 0x20000000 /* Memory width x32 (not supported) */
1513 +#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */
1514 +#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */
1515 +#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */
1516 +
1517 +/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
1518 +#define AR5312_FLASHCTL0 (AR5312_FLASHCTL + 0x00)
1519 +#define AR5312_FLASHCTL1 (AR5312_FLASHCTL + 0x04)
1520 +#define AR5312_FLASHCTL2 (AR5312_FLASHCTL + 0x08)
1521 +
1522 +/* ARM SDRAM Controller -- just enough to determine memory size */
1523 +#define AR5312_MEM_CFG1 (AR5312_SDRAMCTL + 0x04)
1524 +#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */
1525 +#define MEM_CFG1_AC0_S 8
1526 +#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */
1527 +#define MEM_CFG1_AC1_S 12
1528 +
1529 +/* GPIO Address Map */
1530 +#define AR5312_GPIO (AR5312_APBBASE + 0x2000)
1531 +#define AR5312_GPIO_DO (AR5312_GPIO + 0x00) /* output register */
1532 +#define AR5312_GPIO_DI (AR5312_GPIO + 0x04) /* intput register */
1533 +#define AR5312_GPIO_CR (AR5312_GPIO + 0x08) /* control register */
1534 +
1535 +/* GPIO Control Register bit field definitions */
1536 +#define AR5312_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
1537 +#define AR5312_GPIO_CR_O(x) (0 << (x)) /* mask for output */
1538 +#define AR5312_GPIO_CR_I(x) (1 << (x)) /* mask for input */
1539 +#define AR5312_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt*/
1540 +#define AR5312_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */
1541 +#define AR5312_NUM_GPIO 8
1542 +
1543 +#endif /* __ASM_MACH_AR231X_AR5312_REGS_H */
1544 --- /dev/null
1545 +++ b/arch/mips/ar231x/ar5312.c
1546 @@ -0,0 +1,534 @@
1547 +/*
1548 + * This file is subject to the terms and conditions of the GNU General Public
1549 + * License. See the file "COPYING" in the main directory of this archive
1550 + * for more details.
1551 + *
1552 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1553 + * Copyright (C) 2006 FON Technology, SL.
1554 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1555 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1556 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1557 + */
1558 +
1559 +/*
1560 + * Platform devices for Atheros SoCs
1561 + */
1562 +
1563 +#include <generated/autoconf.h>
1564 +#include <linux/init.h>
1565 +#include <linux/module.h>
1566 +#include <linux/types.h>
1567 +#include <linux/string.h>
1568 +#include <linux/mtd/physmap.h>
1569 +#include <linux/platform_device.h>
1570 +#include <linux/kernel.h>
1571 +#include <linux/reboot.h>
1572 +#include <linux/leds.h>
1573 +#include <linux/gpio.h>
1574 +#include <asm/bootinfo.h>
1575 +#include <asm/reboot.h>
1576 +#include <asm/time.h>
1577 +#include <linux/irq.h>
1578 +#include <linux/io.h>
1579 +
1580 +#include <ar231x_platform.h>
1581 +#include <ar5312_regs.h>
1582 +#include <ar231x.h>
1583 +#include "devices.h"
1584 +#include "ar5312.h"
1585 +
1586 +static void ar5312_misc_irq_handler(unsigned irq, struct irq_desc *desc)
1587 +{
1588 + unsigned int ar231x_misc_intrs = ar231x_read_reg(AR5312_ISR) &
1589 + ar231x_read_reg(AR5312_IMR);
1590 +
1591 + if (ar231x_misc_intrs & AR5312_ISR_TIMER) {
1592 + do_IRQ(AR5312_MISC_IRQ_TIMER);
1593 + (void)ar231x_read_reg(AR5312_TIMER);
1594 + } else if (ar231x_misc_intrs & AR5312_ISR_AHBPROC)
1595 + do_IRQ(AR5312_MISC_IRQ_AHB_PROC);
1596 + else if ((ar231x_misc_intrs & AR5312_ISR_UART0))
1597 + do_IRQ(AR5312_MISC_IRQ_UART0);
1598 + else if (ar231x_misc_intrs & AR5312_ISR_WD)
1599 + do_IRQ(AR5312_MISC_IRQ_WATCHDOG);
1600 + else
1601 + do_IRQ(AR5312_MISC_IRQ_NONE);
1602 +}
1603 +
1604 +static asmlinkage void
1605 +ar5312_irq_dispatch(void)
1606 +{
1607 + int pending = read_c0_status() & read_c0_cause();
1608 +
1609 + if (pending & CAUSEF_IP2)
1610 + do_IRQ(AR5312_IRQ_WLAN0_INTRS);
1611 + else if (pending & CAUSEF_IP3)
1612 + do_IRQ(AR5312_IRQ_ENET0_INTRS);
1613 + else if (pending & CAUSEF_IP4)
1614 + do_IRQ(AR5312_IRQ_ENET1_INTRS);
1615 + else if (pending & CAUSEF_IP5)
1616 + do_IRQ(AR5312_IRQ_WLAN1_INTRS);
1617 + else if (pending & CAUSEF_IP6)
1618 + do_IRQ(AR5312_IRQ_MISC_INTRS);
1619 + else if (pending & CAUSEF_IP7)
1620 + do_IRQ(AR231X_IRQ_CPU_CLOCK);
1621 +}
1622 +
1623 +/* Enable the specified AR5312_MISC_IRQ interrupt */
1624 +static void
1625 +ar5312_misc_irq_unmask(struct irq_data *d)
1626 +{
1627 + unsigned int imr;
1628 +
1629 + imr = ar231x_read_reg(AR5312_IMR);
1630 + imr |= (1 << (d->irq - AR231X_MISC_IRQ_BASE - 1));
1631 + ar231x_write_reg(AR5312_IMR, imr);
1632 +}
1633 +
1634 +/* Disable the specified AR5312_MISC_IRQ interrupt */
1635 +static void
1636 +ar5312_misc_irq_mask(struct irq_data *d)
1637 +{
1638 + unsigned int imr;
1639 +
1640 + imr = ar231x_read_reg(AR5312_IMR);
1641 + imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE - 1));
1642 + ar231x_write_reg(AR5312_IMR, imr);
1643 + ar231x_read_reg(AR5312_IMR); /* flush write buffer */
1644 +}
1645 +
1646 +static struct irq_chip ar5312_misc_irq_chip = {
1647 + .name = "AR5312-MISC",
1648 + .irq_unmask = ar5312_misc_irq_unmask,
1649 + .irq_mask = ar5312_misc_irq_mask,
1650 +};
1651 +
1652 +static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id)
1653 +{
1654 + u32 proc1 = ar231x_read_reg(AR5312_PROC1);
1655 + u32 proc_addr = ar231x_read_reg(AR5312_PROCADDR); /* clears error */
1656 + u32 dma1 = ar231x_read_reg(AR5312_DMA1);
1657 + u32 dma_addr = ar231x_read_reg(AR5312_DMAADDR); /* clears error */
1658 +
1659 + pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
1660 + proc_addr, proc1, dma_addr, dma1);
1661 +
1662 + machine_restart("AHB error"); /* Catastrophic failure */
1663 + return IRQ_HANDLED;
1664 +}
1665 +
1666 +static struct irqaction ar5312_ahb_proc_interrupt = {
1667 + .handler = ar5312_ahb_proc_handler,
1668 + .name = "ar5312_ahb_proc_interrupt",
1669 +};
1670 +
1671 +void __init ar5312_irq_init(void)
1672 +{
1673 + int i;
1674 +
1675 + if (!is_5312())
1676 + return;
1677 +
1678 + ar231x_irq_dispatch = ar5312_irq_dispatch;
1679 + for (i = 0; i < AR5312_MISC_IRQ_COUNT; i++) {
1680 + int irq = AR231X_MISC_IRQ_BASE + i;
1681 +
1682 + irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip,
1683 + handle_level_irq);
1684 + }
1685 + setup_irq(AR5312_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt);
1686 + irq_set_chained_handler(AR5312_IRQ_MISC_INTRS, ar5312_misc_irq_handler);
1687 +}
1688 +
1689 +/*
1690 + * gpiolib implementations
1691 + */
1692 +static int
1693 +ar5312_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
1694 +{
1695 + return (ar231x_read_reg(AR5312_GPIO_DI) >> gpio) & 1;
1696 +}
1697 +
1698 +static void
1699 +ar5312_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
1700 +{
1701 + u32 reg = ar231x_read_reg(AR5312_GPIO_DO);
1702 +
1703 + reg = value ? reg | (1 << gpio) : reg & ~(1 << gpio);
1704 + ar231x_write_reg(AR5312_GPIO_DO, reg);
1705 +}
1706 +
1707 +static int
1708 +ar5312_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
1709 +{
1710 + ar231x_mask_reg(AR5312_GPIO_CR, 0, 1 << gpio);
1711 + return 0;
1712 +}
1713 +
1714 +static int
1715 +ar5312_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
1716 +{
1717 + ar231x_mask_reg(AR5312_GPIO_CR, 1 << gpio, 0);
1718 + ar5312_gpio_set_value(chip, gpio, value);
1719 + return 0;
1720 +}
1721 +
1722 +static struct gpio_chip ar5312_gpio_chip = {
1723 + .label = "ar5312-gpio",
1724 + .direction_input = ar5312_gpio_direction_input,
1725 + .direction_output = ar5312_gpio_direction_output,
1726 + .set = ar5312_gpio_set_value,
1727 + .get = ar5312_gpio_get_value,
1728 + .base = 0,
1729 + .ngpio = AR5312_NUM_GPIO, /* 8 */
1730 +};
1731 +
1732 +/* end of gpiolib */
1733 +
1734 +static void ar5312_device_reset_set(u32 mask)
1735 +{
1736 + u32 val;
1737 +
1738 + val = ar231x_read_reg(AR5312_RESET);
1739 + ar231x_write_reg(AR5312_RESET, val | mask);
1740 +}
1741 +
1742 +static void ar5312_device_reset_clear(u32 mask)
1743 +{
1744 + u32 val;
1745 +
1746 + val = ar231x_read_reg(AR5312_RESET);
1747 + ar231x_write_reg(AR5312_RESET, val & ~mask);
1748 +}
1749 +
1750 +static struct physmap_flash_data ar5312_flash_data = {
1751 + .width = 2,
1752 +};
1753 +
1754 +static struct resource ar5312_flash_resource = {
1755 + .start = AR5312_FLASH,
1756 + .end = AR5312_FLASH + 0x800000 - 1,
1757 + .flags = IORESOURCE_MEM,
1758 +};
1759 +
1760 +static struct ar231x_eth ar5312_eth0_data = {
1761 + .reset_set = ar5312_device_reset_set,
1762 + .reset_clear = ar5312_device_reset_clear,
1763 + .reset_mac = AR5312_RESET_ENET0,
1764 + .reset_phy = AR5312_RESET_EPHY0,
1765 + .config = &ar231x_board,
1766 +};
1767 +
1768 +static struct ar231x_eth ar5312_eth1_data = {
1769 + .reset_set = ar5312_device_reset_set,
1770 + .reset_clear = ar5312_device_reset_clear,
1771 + .reset_mac = AR5312_RESET_ENET1,
1772 + .reset_phy = AR5312_RESET_EPHY1,
1773 + .config = &ar231x_board,
1774 +};
1775 +
1776 +static struct platform_device ar5312_physmap_flash = {
1777 + .name = "physmap-flash",
1778 + .id = 0,
1779 + .dev.platform_data = &ar5312_flash_data,
1780 + .resource = &ar5312_flash_resource,
1781 + .num_resources = 1,
1782 +};
1783 +
1784 +#ifdef CONFIG_LEDS_GPIO
1785 +static struct gpio_led ar5312_leds[] = {
1786 + { .name = "wlan", .gpio = 0, .active_low = 1, },
1787 +};
1788 +
1789 +static const struct gpio_led_platform_data ar5312_led_data = {
1790 + .num_leds = ARRAY_SIZE(ar5312_leds),
1791 + .leds = (void *)ar5312_leds,
1792 +};
1793 +
1794 +static struct platform_device ar5312_gpio_leds = {
1795 + .name = "leds-gpio",
1796 + .id = -1,
1797 + .dev.platform_data = (void *)&ar5312_led_data,
1798 +};
1799 +#endif
1800 +
1801 +/*
1802 + * NB: This mapping size is larger than the actual flash size,
1803 + * but this shouldn't be a problem here, because the flash
1804 + * will simply be mapped multiple times.
1805 + */
1806 +static char __init *ar5312_flash_limit(void)
1807 +{
1808 + u32 ctl;
1809 + /*
1810 + * Configure flash bank 0.
1811 + * Assume 8M window size. Flash will be aliased if it's smaller
1812 + */
1813 + ctl = FLASHCTL_E |
1814 + FLASHCTL_AC_8M |
1815 + FLASHCTL_RBLE |
1816 + (0x01 << FLASHCTL_IDCY_S) |
1817 + (0x07 << FLASHCTL_WST1_S) |
1818 + (0x07 << FLASHCTL_WST2_S) |
1819 + (ar231x_read_reg(AR5312_FLASHCTL0) & FLASHCTL_MW);
1820 +
1821 + ar231x_write_reg(AR5312_FLASHCTL0, ctl);
1822 +
1823 + /* Disable other flash banks */
1824 + ar231x_write_reg(AR5312_FLASHCTL1,
1825 + ar231x_read_reg(AR5312_FLASHCTL1) &
1826 + ~(FLASHCTL_E | FLASHCTL_AC));
1827 +
1828 + ar231x_write_reg(AR5312_FLASHCTL2,
1829 + ar231x_read_reg(AR5312_FLASHCTL2) &
1830 + ~(FLASHCTL_E | FLASHCTL_AC));
1831 +
1832 + return (char *)KSEG1ADDR(AR5312_FLASH + 0x800000);
1833 +}
1834 +
1835 +int __init ar5312_init_devices(void)
1836 +{
1837 + struct ar231x_boarddata *config;
1838 + u32 fctl = 0;
1839 + u8 *c;
1840 +
1841 + if (!is_5312())
1842 + return 0;
1843 +
1844 + /* Locate board/radio config data */
1845 + ar231x_find_config(ar5312_flash_limit());
1846 + config = ar231x_board.config;
1847 +
1848 + /* AR2313 has CPU minor rev. 10 */
1849 + if ((current_cpu_data.processor_id & 0xff) == 0x0a)
1850 + ar231x_devtype = DEV_TYPE_AR2313;
1851 +
1852 + /* AR2312 shares the same Silicon ID as AR5312 */
1853 + else if (config->flags & BD_ISCASPER)
1854 + ar231x_devtype = DEV_TYPE_AR2312;
1855 +
1856 + /* Everything else is probably AR5312 or compatible */
1857 + else
1858 + ar231x_devtype = DEV_TYPE_AR5312;
1859 +
1860 + /* fixup flash width */
1861 + fctl = ar231x_read_reg(AR5312_FLASHCTL) & FLASHCTL_MW;
1862 + switch (fctl) {
1863 + case FLASHCTL_MW16:
1864 + ar5312_flash_data.width = 2;
1865 + break;
1866 + case FLASHCTL_MW8:
1867 + default:
1868 + ar5312_flash_data.width = 1;
1869 + break;
1870 + }
1871 +
1872 + platform_device_register(&ar5312_physmap_flash);
1873 +
1874 +#ifdef CONFIG_LEDS_GPIO
1875 + ar5312_leds[0].gpio = config->sys_led_gpio;
1876 + platform_device_register(&ar5312_gpio_leds);
1877 +#endif
1878 +
1879 + /* Fix up MAC addresses if necessary */
1880 + if (is_broadcast_ether_addr(config->enet0_mac))
1881 + ether_addr_copy(config->enet0_mac, config->enet1_mac);
1882 +
1883 + /* If ENET0 and ENET1 have the same mac address,
1884 + * increment the one from ENET1 */
1885 + if (ether_addr_equal(config->enet0_mac, config->enet1_mac)) {
1886 + c = config->enet1_mac + 5;
1887 + while ((c >= config->enet1_mac) && !(++(*c)))
1888 + c--;
1889 + }
1890 +
1891 + switch (ar231x_devtype) {
1892 + case DEV_TYPE_AR5312:
1893 + ar5312_eth0_data.macaddr = config->enet0_mac;
1894 + ar231x_add_ethernet(0, AR5312_ENET0, "eth0_mii",
1895 + AR5312_ENET0_MII, AR5312_IRQ_ENET0_INTRS,
1896 + &ar5312_eth0_data);
1897 +
1898 + ar5312_eth1_data.macaddr = config->enet1_mac;
1899 + ar231x_add_ethernet(1, AR5312_ENET1, "eth1_mii",
1900 + AR5312_ENET1_MII, AR5312_IRQ_ENET1_INTRS,
1901 + &ar5312_eth1_data);
1902 +
1903 + if (!ar231x_board.radio)
1904 + return 0;
1905 +
1906 + if (!(config->flags & BD_WLAN0))
1907 + break;
1908 +
1909 + ar231x_add_wmac(0, AR5312_WLAN0, AR5312_IRQ_WLAN0_INTRS);
1910 + break;
1911 + /*
1912 + * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
1913 + * of ENET1. Atheros calls it 'twisted' for a reason :)
1914 + */
1915 + case DEV_TYPE_AR2312:
1916 + case DEV_TYPE_AR2313:
1917 + ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
1918 + ar5312_eth1_data.macaddr = config->enet0_mac;
1919 + ar231x_add_ethernet(1, AR5312_ENET1, "eth0_mii",
1920 + AR5312_ENET0_MII, AR5312_IRQ_ENET1_INTRS,
1921 + &ar5312_eth1_data);
1922 +
1923 + if (!ar231x_board.radio)
1924 + return 0;
1925 + break;
1926 + default:
1927 + break;
1928 + }
1929 +
1930 + if (config->flags & BD_WLAN1)
1931 + ar231x_add_wmac(1, AR5312_WLAN1, AR5312_IRQ_WLAN1_INTRS);
1932 +
1933 + return 0;
1934 +}
1935 +
1936 +static void ar5312_restart(char *command)
1937 +{
1938 + /* reset the system */
1939 + local_irq_disable();
1940 + while (1)
1941 + ar231x_write_reg(AR5312_RESET, AR5312_RESET_SYSTEM);
1942 +}
1943 +
1944 +/*
1945 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
1946 + * to determine the predevisor value.
1947 + */
1948 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
1949 +
1950 +static int __init
1951 +ar5312_cpu_frequency(void)
1952 +{
1953 + unsigned int scratch;
1954 + unsigned int predivide_mask, predivide_shift;
1955 + unsigned int multiplier_mask, multiplier_shift;
1956 + unsigned int clock_ctl1, predivide_select, predivisor, multiplier;
1957 + unsigned int doubler_mask;
1958 + u16 devid;
1959 +
1960 + /* Trust the bootrom's idea of cpu frequency. */
1961 + scratch = ar231x_read_reg(AR5312_SCRATCH);
1962 + if (scratch)
1963 + return scratch;
1964 +
1965 + devid = ar231x_read_reg(AR5312_REV);
1966 + devid &= AR5312_REV_MAJ;
1967 + devid >>= AR5312_REV_MAJ_S;
1968 + if (devid == AR5312_REV_MAJ_AR2313) {
1969 + predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
1970 + predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
1971 + multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
1972 + multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
1973 + doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
1974 + } else { /* AR5312 and AR2312 */
1975 + predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
1976 + predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
1977 + multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
1978 + multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
1979 + doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
1980 + }
1981 +
1982 + /*
1983 + * Clocking is derived from a fixed 40MHz input clock.
1984 + *
1985 + * cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
1986 + * sys_freq = cpu_freq / 4 (used for APB clock, serial,
1987 + * flash, Timer, Watchdog Timer)
1988 + *
1989 + * cnt_freq = cpu_freq / 2 (use for CPU count/compare)
1990 + *
1991 + * So, for example, with a PLL multiplier of 5, we have
1992 + *
1993 + * cpu_freq = 200MHz
1994 + * sys_freq = 50MHz
1995 + * cnt_freq = 100MHz
1996 + *
1997 + * We compute the CPU frequency, based on PLL settings.
1998 + */
1999 +
2000 + clock_ctl1 = ar231x_read_reg(AR5312_CLOCKCTL1);
2001 + predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
2002 + predivisor = clockctl1_predivide_table[predivide_select];
2003 + multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
2004 +
2005 + if (clock_ctl1 & doubler_mask)
2006 + multiplier = multiplier << 1;
2007 +
2008 + return (40000000 / predivisor) * multiplier;
2009 +}
2010 +
2011 +static inline int
2012 +ar5312_sys_frequency(void)
2013 +{
2014 + return ar5312_cpu_frequency() / 4;
2015 +}
2016 +
2017 +void __init
2018 +ar5312_time_init(void)
2019 +{
2020 + if (!is_5312())
2021 + return;
2022 +
2023 + mips_hpt_frequency = ar5312_cpu_frequency() / 2;
2024 +}
2025 +
2026 +static int __init
2027 +ar5312_gpio_init(void)
2028 +{
2029 + int ret = gpiochip_add(&ar5312_gpio_chip);
2030 +
2031 + if (ret) {
2032 + pr_err("%s: failed to add gpiochip\n", ar5312_gpio_chip.label);
2033 + return ret;
2034 + }
2035 + pr_info("%s: registered %d GPIOs\n", ar5312_gpio_chip.label,
2036 + ar5312_gpio_chip.ngpio);
2037 + return ret;
2038 +}
2039 +
2040 +void __init
2041 +ar5312_prom_init(void)
2042 +{
2043 + u32 memsize, memcfg, bank0AC, bank1AC;
2044 + u32 devid;
2045 +
2046 + if (!is_5312())
2047 + return;
2048 +
2049 + /* Detect memory size */
2050 + memcfg = ar231x_read_reg(AR5312_MEM_CFG1);
2051 + bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
2052 + bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
2053 + memsize = (bank0AC ? (1 << (bank0AC+1)) : 0) +
2054 + (bank1AC ? (1 << (bank1AC+1)) : 0);
2055 + memsize <<= 20;
2056 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2057 +
2058 + devid = ar231x_read_reg(AR5312_REV);
2059 + devid >>= AR5312_REV_WMAC_MIN_S;
2060 + devid &= AR5312_REV_CHIP;
2061 + ar231x_board.devid = (u16)devid;
2062 + ar5312_gpio_init();
2063 +}
2064 +
2065 +void __init
2066 +ar5312_plat_setup(void)
2067 +{
2068 + if (!is_5312())
2069 + return;
2070 +
2071 + /* Clear any lingering AHB errors */
2072 + ar231x_read_reg(AR5312_PROCADDR);
2073 + ar231x_read_reg(AR5312_DMAADDR);
2074 + ar231x_write_reg(AR5312_WD_CTRL, AR5312_WD_CTRL_IGNORE_EXPIRATION);
2075 +
2076 + _machine_restart = ar5312_restart;
2077 + ar231x_serial_setup(AR5312_UART0, AR5312_MISC_IRQ_UART0,
2078 + ar5312_sys_frequency());
2079 +}
2080 +
2081 --- /dev/null
2082 +++ b/arch/mips/ar231x/ar2315.c
2083 @@ -0,0 +1,556 @@
2084 +/*
2085 + * This file is subject to the terms and conditions of the GNU General Public
2086 + * License. See the file "COPYING" in the main directory of this archive
2087 + * for more details.
2088 + *
2089 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
2090 + * Copyright (C) 2006 FON Technology, SL.
2091 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
2092 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
2093 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
2094 + */
2095 +
2096 +/*
2097 + * Platform devices for Atheros SoCs
2098 + */
2099 +
2100 +#include <generated/autoconf.h>
2101 +#include <linux/init.h>
2102 +#include <linux/module.h>
2103 +#include <linux/types.h>
2104 +#include <linux/string.h>
2105 +#include <linux/platform_device.h>
2106 +#include <linux/kernel.h>
2107 +#include <linux/reboot.h>
2108 +#include <linux/delay.h>
2109 +#include <linux/leds.h>
2110 +#include <linux/gpio.h>
2111 +#include <asm/bootinfo.h>
2112 +#include <asm/reboot.h>
2113 +#include <asm/time.h>
2114 +#include <linux/irq.h>
2115 +#include <linux/io.h>
2116 +
2117 +#include <ar231x_platform.h>
2118 +#include <ar2315_regs.h>
2119 +#include <ar231x.h>
2120 +#include "devices.h"
2121 +#include "ar2315.h"
2122 +
2123 +static u32 gpiointmask, gpiointval;
2124 +
2125 +static void ar2315_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
2126 +{
2127 + u32 pend;
2128 + int bit = -1;
2129 +
2130 + /* only do one gpio interrupt at a time */
2131 + pend = (ar231x_read_reg(AR2315_GPIO_DI) ^ gpiointval) & gpiointmask;
2132 +
2133 + if (pend) {
2134 + bit = fls(pend) - 1;
2135 + pend &= ~(1 << bit);
2136 + gpiointval ^= (1 << bit);
2137 + }
2138 +
2139 + if (!pend)
2140 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO);
2141 +
2142 + /* Enable interrupt with edge detection */
2143 + if ((ar231x_read_reg(AR2315_GPIO_DIR) & AR2315_GPIO_DIR_M(bit)) !=
2144 + AR2315_GPIO_DIR_I(bit))
2145 + return;
2146 +
2147 + if (bit >= 0)
2148 + do_IRQ(AR231X_GPIO_IRQ_BASE + bit);
2149 +}
2150 +
2151 +static void ar2315_misc_irq_handler(unsigned irq, struct irq_desc *desc)
2152 +{
2153 + unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) &
2154 + ar231x_read_reg(AR2315_IMR);
2155 +
2156 + if (misc_intr & AR2315_ISR_SPI)
2157 + do_IRQ(AR2315_MISC_IRQ_SPI);
2158 + else if (misc_intr & AR2315_ISR_TIMER)
2159 + do_IRQ(AR2315_MISC_IRQ_TIMER);
2160 + else if (misc_intr & AR2315_ISR_AHB)
2161 + do_IRQ(AR2315_MISC_IRQ_AHB);
2162 + else if (misc_intr & AR2315_ISR_GPIO)
2163 + do_IRQ(AR2315_MISC_IRQ_GPIO);
2164 + else if (misc_intr & AR2315_ISR_UART0)
2165 + do_IRQ(AR2315_MISC_IRQ_UART0);
2166 + else if (misc_intr & AR2315_ISR_WD) {
2167 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_WD);
2168 + do_IRQ(AR2315_MISC_IRQ_WATCHDOG);
2169 + } else
2170 + do_IRQ(AR2315_MISC_IRQ_NONE);
2171 +}
2172 +
2173 +/*
2174 + * Called when an interrupt is received, this function
2175 + * determines exactly which interrupt it was, and it
2176 + * invokes the appropriate handler.
2177 + *
2178 + * Implicitly, we also define interrupt priority by
2179 + * choosing which to dispatch first.
2180 + */
2181 +static asmlinkage void
2182 +ar2315_irq_dispatch(void)
2183 +{
2184 + int pending = read_c0_status() & read_c0_cause();
2185 +
2186 + if (pending & CAUSEF_IP3)
2187 + do_IRQ(AR2315_IRQ_WLAN0_INTRS);
2188 + else if (pending & CAUSEF_IP4)
2189 + do_IRQ(AR2315_IRQ_ENET0_INTRS);
2190 + else if (pending & CAUSEF_IP2)
2191 + do_IRQ(AR2315_IRQ_MISC_INTRS);
2192 + else if (pending & CAUSEF_IP7)
2193 + do_IRQ(AR231X_IRQ_CPU_CLOCK);
2194 +}
2195 +
2196 +static void ar2315_set_gpiointmask(int gpio, int level)
2197 +{
2198 + u32 reg;
2199 +
2200 + reg = ar231x_read_reg(AR2315_GPIO_INT);
2201 + reg &= ~(AR2315_GPIO_INT_M | AR2315_GPIO_INT_LVL_M);
2202 + reg |= gpio | AR2315_GPIO_INT_LVL(level);
2203 + ar231x_write_reg(AR2315_GPIO_INT, reg);
2204 +}
2205 +
2206 +static void ar2315_gpio_irq_unmask(struct irq_data *d)
2207 +{
2208 + unsigned int gpio = d->irq - AR231X_GPIO_IRQ_BASE;
2209 +
2210 + /* Enable interrupt with edge detection */
2211 + if ((ar231x_read_reg(AR2315_GPIO_DIR) & AR2315_GPIO_DIR_M(gpio)) !=
2212 + AR2315_GPIO_DIR_I(gpio))
2213 + return;
2214 +
2215 + gpiointmask |= (1 << gpio);
2216 + ar2315_set_gpiointmask(gpio, 3);
2217 +}
2218 +
2219 +static void ar2315_gpio_irq_mask(struct irq_data *d)
2220 +{
2221 + unsigned int gpio = d->irq - AR231X_GPIO_IRQ_BASE;
2222 +
2223 + /* Disable interrupt */
2224 + gpiointmask &= ~(1 << gpio);
2225 + ar2315_set_gpiointmask(gpio, 0);
2226 +}
2227 +
2228 +static struct irq_chip ar2315_gpio_irq_chip = {
2229 + .name = "AR2315-GPIO",
2230 + .irq_unmask = ar2315_gpio_irq_unmask,
2231 + .irq_mask = ar2315_gpio_irq_mask,
2232 +};
2233 +
2234 +static void
2235 +ar2315_misc_irq_unmask(struct irq_data *d)
2236 +{
2237 + unsigned int imr;
2238 +
2239 + imr = ar231x_read_reg(AR2315_IMR);
2240 + imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE - 1);
2241 + ar231x_write_reg(AR2315_IMR, imr);
2242 +}
2243 +
2244 +static void
2245 +ar2315_misc_irq_mask(struct irq_data *d)
2246 +{
2247 + unsigned int imr;
2248 +
2249 + imr = ar231x_read_reg(AR2315_IMR);
2250 + imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE - 1));
2251 + ar231x_write_reg(AR2315_IMR, imr);
2252 +}
2253 +
2254 +static struct irq_chip ar2315_misc_irq_chip = {
2255 + .name = "AR2315-MISC",
2256 + .irq_unmask = ar2315_misc_irq_unmask,
2257 + .irq_mask = ar2315_misc_irq_mask,
2258 +};
2259 +
2260 +static irqreturn_t ar2315_ahb_proc_handler(int cpl, void *dev_id)
2261 +{
2262 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2263 + ar231x_read_reg(AR2315_AHB_ERR1);
2264 +
2265 + pr_emerg("AHB fatal error\n");
2266 + machine_restart("AHB error"); /* Catastrophic failure */
2267 +
2268 + return IRQ_HANDLED;
2269 +}
2270 +
2271 +static struct irqaction ar2315_ahb_proc_interrupt = {
2272 + .handler = ar2315_ahb_proc_handler,
2273 + .name = "ar2315_ahb_proc_interrupt",
2274 +};
2275 +
2276 +void
2277 +ar2315_irq_init(void)
2278 +{
2279 + int i;
2280 +
2281 + if (!is_2315())
2282 + return;
2283 +
2284 + ar231x_irq_dispatch = ar2315_irq_dispatch;
2285 + gpiointval = ar231x_read_reg(AR2315_GPIO_DI);
2286 + for (i = 0; i < AR2315_MISC_IRQ_COUNT; i++) {
2287 + int irq = AR231X_MISC_IRQ_BASE + i;
2288 +
2289 + irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip,
2290 + handle_level_irq);
2291 + }
2292 + for (i = 0; i < AR2315_NUM_GPIO; i++) {
2293 + int irq = AR231X_GPIO_IRQ_BASE + i;
2294 +
2295 + irq_set_chip_and_handler(irq, &ar2315_gpio_irq_chip,
2296 + handle_level_irq);
2297 + }
2298 + irq_set_chained_handler(AR2315_MISC_IRQ_GPIO, ar2315_gpio_irq_handler);
2299 + setup_irq(AR2315_MISC_IRQ_AHB, &ar2315_ahb_proc_interrupt);
2300 + irq_set_chained_handler(AR2315_IRQ_MISC_INTRS, ar2315_misc_irq_handler);
2301 +}
2302 +
2303 +/*
2304 + * gpiolib implementation
2305 + */
2306 +static int
2307 +ar2315_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
2308 +{
2309 + return (ar231x_read_reg(AR2315_GPIO_DI) >> gpio) & 1;
2310 +}
2311 +
2312 +static void
2313 +ar2315_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
2314 +{
2315 + u32 reg = ar231x_read_reg(AR2315_GPIO_DO);
2316 +
2317 + reg = value ? reg | (1 << gpio) : reg & ~(1 << gpio);
2318 + ar231x_write_reg(AR2315_GPIO_DO, reg);
2319 +}
2320 +
2321 +static int
2322 +ar2315_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
2323 +{
2324 + ar231x_mask_reg(AR2315_GPIO_DIR, 1 << gpio, 0);
2325 + return 0;
2326 +}
2327 +
2328 +static int
2329 +ar2315_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
2330 +{
2331 + ar231x_mask_reg(AR2315_GPIO_DIR, 0, 1 << gpio);
2332 + ar2315_gpio_set_value(chip, gpio, value);
2333 + return 0;
2334 +}
2335 +
2336 +static struct gpio_chip ar2315_gpio_chip = {
2337 + .label = "ar2315-gpio",
2338 + .direction_input = ar2315_gpio_direction_input,
2339 + .direction_output = ar2315_gpio_direction_output,
2340 + .set = ar2315_gpio_set_value,
2341 + .get = ar2315_gpio_get_value,
2342 + .base = 0,
2343 + .ngpio = AR2315_NUM_GPIO, /* 22 */
2344 +};
2345 +
2346 +/* end of gpiolib */
2347 +
2348 +static void ar2315_device_reset_set(u32 mask)
2349 +{
2350 + u32 val;
2351 +
2352 + val = ar231x_read_reg(AR2315_RESET);
2353 + ar231x_write_reg(AR2315_RESET, val | mask);
2354 +}
2355 +
2356 +static void ar2315_device_reset_clear(u32 mask)
2357 +{
2358 + u32 val;
2359 +
2360 + val = ar231x_read_reg(AR2315_RESET);
2361 + ar231x_write_reg(AR2315_RESET, val & ~mask);
2362 +}
2363 +
2364 +static struct ar231x_eth ar2315_eth_data = {
2365 + .reset_set = ar2315_device_reset_set,
2366 + .reset_clear = ar2315_device_reset_clear,
2367 + .reset_mac = AR2315_RESET_ENET0,
2368 + .reset_phy = AR2315_RESET_EPHY0,
2369 + .config = &ar231x_board,
2370 +};
2371 +
2372 +static struct resource ar2315_spiflash_res[] = {
2373 + {
2374 + .name = "spiflash_read",
2375 + .flags = IORESOURCE_MEM,
2376 + .start = AR2315_SPI_READ,
2377 + .end = AR2315_SPI_READ + 0x1000000 - 1,
2378 + },
2379 + {
2380 + .name = "spiflash_mmr",
2381 + .flags = IORESOURCE_MEM,
2382 + .start = AR2315_SPI_MMR,
2383 + .end = AR2315_SPI_MMR + 12 - 1,
2384 + },
2385 +};
2386 +
2387 +static struct platform_device ar2315_spiflash = {
2388 + .id = 0,
2389 + .name = "ar2315-spiflash",
2390 + .resource = ar2315_spiflash_res,
2391 + .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
2392 +};
2393 +
2394 +static struct resource ar2315_wdt_res[] = {
2395 + {
2396 + .flags = IORESOURCE_MEM,
2397 + .start = AR2315_WD,
2398 + .end = AR2315_WD + 8 - 1,
2399 + },
2400 + {
2401 + .flags = IORESOURCE_IRQ,
2402 + .start = AR2315_MISC_IRQ_WATCHDOG,
2403 + .end = AR2315_MISC_IRQ_WATCHDOG,
2404 + }
2405 +};
2406 +
2407 +static struct platform_device ar2315_wdt = {
2408 + .id = 0,
2409 + .name = "ar2315-wdt",
2410 + .resource = ar2315_wdt_res,
2411 + .num_resources = ARRAY_SIZE(ar2315_wdt_res)
2412 +};
2413 +
2414 +/*
2415 + * NB: We use mapping size that is larger than the actual flash size,
2416 + * but this shouldn't be a problem here, because the flash will simply
2417 + * be mapped multiple times.
2418 + */
2419 +static u8 __init *ar2315_flash_limit(void)
2420 +{
2421 + return (u8 *)KSEG1ADDR(ar2315_spiflash_res[0].end + 1);
2422 +}
2423 +
2424 +#ifdef CONFIG_LEDS_GPIO
2425 +static struct gpio_led ar2315_leds[6];
2426 +static struct gpio_led_platform_data ar2315_led_data = {
2427 + .leds = (void *)ar2315_leds,
2428 +};
2429 +
2430 +static struct platform_device ar2315_gpio_leds = {
2431 + .name = "leds-gpio",
2432 + .id = -1,
2433 + .dev = {
2434 + .platform_data = (void *)&ar2315_led_data,
2435 + }
2436 +};
2437 +
2438 +static void __init
2439 +ar2315_init_gpio_leds(void)
2440 +{
2441 + static char led_names[6][6];
2442 + int i, led = 0;
2443 +
2444 + ar2315_led_data.num_leds = 0;
2445 + for (i = 1; i < 8; i++) {
2446 + if ((i == AR2315_RESET_GPIO) ||
2447 + (i == ar231x_board.config->reset_config_gpio))
2448 + continue;
2449 +
2450 + if (i == ar231x_board.config->sys_led_gpio)
2451 + strcpy(led_names[led], "wlan");
2452 + else
2453 + sprintf(led_names[led], "gpio%d", i);
2454 +
2455 + ar2315_leds[led].name = led_names[led];
2456 + ar2315_leds[led].gpio = i;
2457 + ar2315_leds[led].active_low = 0;
2458 + led++;
2459 + }
2460 + ar2315_led_data.num_leds = led;
2461 + platform_device_register(&ar2315_gpio_leds);
2462 +}
2463 +#else
2464 +static inline void ar2315_init_gpio_leds(void)
2465 +{
2466 +}
2467 +#endif
2468 +
2469 +int __init
2470 +ar2315_init_devices(void)
2471 +{
2472 + if (!is_2315())
2473 + return 0;
2474 +
2475 + /* Find board configuration */
2476 + ar231x_find_config(ar2315_flash_limit());
2477 + ar2315_eth_data.macaddr = ar231x_board.config->enet0_mac;
2478 +
2479 + ar2315_init_gpio_leds();
2480 + platform_device_register(&ar2315_wdt);
2481 + platform_device_register(&ar2315_spiflash);
2482 + ar231x_add_ethernet(0, AR2315_ENET0, "eth0_mii", AR2315_ENET0_MII,
2483 + AR2315_IRQ_ENET0_INTRS, &ar2315_eth_data);
2484 + ar231x_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS);
2485 +
2486 + return 0;
2487 +}
2488 +
2489 +static void
2490 +ar2315_restart(char *command)
2491 +{
2492 + void (*mips_reset_vec)(void) = (void *)0xbfc00000;
2493 +
2494 + local_irq_disable();
2495 +
2496 + /* try reset the system via reset control */
2497 + ar231x_write_reg(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
2498 +
2499 + /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
2500 + * a workaround. Give it some time to attempt a gpio based hardware
2501 + * reset (atheros reference design workaround) */
2502 + gpio_request_one(AR2315_RESET_GPIO, GPIOF_OUT_INIT_LOW, "Reset");
2503 + mdelay(100);
2504 +
2505 + /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
2506 + * workaround. Attempt to jump to the mips reset location -
2507 + * the boot loader itself might be able to recover the system */
2508 + mips_reset_vec();
2509 +}
2510 +
2511 +/*
2512 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
2513 + * to determine the predevisor value.
2514 + */
2515 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
2516 +static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
2517 +
2518 +static unsigned int __init
2519 +ar2315_sys_clk(unsigned int clock_ctl)
2520 +{
2521 + unsigned int pllc_ctrl, cpu_div;
2522 + unsigned int pllc_out, refdiv, fdiv, divby2;
2523 + unsigned int clk_div;
2524 +
2525 + pllc_ctrl = ar231x_read_reg(AR2315_PLLC_CTL);
2526 + refdiv = (pllc_ctrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
2527 + refdiv = clockctl1_predivide_table[refdiv];
2528 + fdiv = (pllc_ctrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
2529 + divby2 = (pllc_ctrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
2530 + divby2 += 1;
2531 + pllc_out = (40000000/refdiv)*(2*divby2)*fdiv;
2532 +
2533 + /* clkm input selected */
2534 + switch (clock_ctl & CPUCLK_CLK_SEL_M) {
2535 + case 0:
2536 + case 1:
2537 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKM_DIV_M) >>
2538 + PLLC_CLKM_DIV_S];
2539 + break;
2540 + case 2:
2541 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKC_DIV_M) >>
2542 + PLLC_CLKC_DIV_S];
2543 + break;
2544 + default:
2545 + pllc_out = 40000000;
2546 + clk_div = 1;
2547 + break;
2548 + }
2549 +
2550 + cpu_div = (clock_ctl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
2551 + cpu_div = cpu_div * 2 ?: 1;
2552 +
2553 + return pllc_out / (clk_div * cpu_div);
2554 +}
2555 +
2556 +static inline unsigned int
2557 +ar2315_cpu_frequency(void)
2558 +{
2559 + return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK));
2560 +}
2561 +
2562 +static inline unsigned int
2563 +ar2315_apb_frequency(void)
2564 +{
2565 + return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK));
2566 +}
2567 +
2568 +void __init
2569 +ar2315_time_init(void)
2570 +{
2571 + if (!is_2315())
2572 + return;
2573 +
2574 + mips_hpt_frequency = ar2315_cpu_frequency() / 2;
2575 +}
2576 +
2577 +static int __init
2578 +ar2315_gpio_init(void)
2579 +{
2580 + int ret = gpiochip_add(&ar2315_gpio_chip);
2581 +
2582 + if (ret) {
2583 + pr_err("%s: failed to add gpiochip\n", ar2315_gpio_chip.label);
2584 + return ret;
2585 + }
2586 + pr_info("%s: registered %d GPIOs\n", ar2315_gpio_chip.label,
2587 + ar2315_gpio_chip.ngpio);
2588 + return ret;
2589 +}
2590 +
2591 +void __init
2592 +ar2315_prom_init(void)
2593 +{
2594 + u32 memsize, memcfg, devid;
2595 +
2596 + if (!is_2315())
2597 + return;
2598 +
2599 + memcfg = ar231x_read_reg(AR2315_MEM_CFG);
2600 + memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
2601 + memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
2602 + memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
2603 + memsize <<= 3;
2604 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2605 +
2606 + /* Detect the hardware based on the device ID */
2607 + devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP;
2608 + switch (devid) {
2609 + case 0x90:
2610 + case 0x91:
2611 + ar231x_devtype = DEV_TYPE_AR2317;
2612 + break;
2613 + default:
2614 + ar231x_devtype = DEV_TYPE_AR2315;
2615 + break;
2616 + }
2617 + ar2315_gpio_init();
2618 + ar231x_board.devid = devid;
2619 +}
2620 +
2621 +void __init
2622 +ar2315_plat_setup(void)
2623 +{
2624 + u32 config;
2625 +
2626 + if (!is_2315())
2627 + return;
2628 +
2629 + /* Clear any lingering AHB errors */
2630 + config = read_c0_config();
2631 + write_c0_config(config & ~0x3);
2632 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2633 + ar231x_read_reg(AR2315_AHB_ERR1);
2634 + ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION);
2635 +
2636 + _machine_restart = ar2315_restart;
2637 + ar231x_serial_setup(AR2315_UART0, AR2315_MISC_IRQ_UART0,
2638 + ar2315_apb_frequency());
2639 +}
2640 --- /dev/null
2641 +++ b/arch/mips/ar231x/ar2315.h
2642 @@ -0,0 +1,37 @@
2643 +#ifndef __AR2315_H
2644 +#define __AR2315_H
2645 +
2646 +#ifdef CONFIG_ATHEROS_AR2315
2647 +
2648 +void ar2315_irq_init(void);
2649 +int ar2315_init_devices(void);
2650 +void ar2315_prom_init(void);
2651 +void ar2315_plat_setup(void);
2652 +void ar2315_time_init(void);
2653 +
2654 +#else
2655 +
2656 +static inline void ar2315_irq_init(void)
2657 +{
2658 +}
2659 +
2660 +static inline int ar2315_init_devices(void)
2661 +{
2662 + return 0;
2663 +}
2664 +
2665 +static inline void ar2315_prom_init(void)
2666 +{
2667 +}
2668 +
2669 +static inline void ar2315_plat_setup(void)
2670 +{
2671 +}
2672 +
2673 +static inline void ar2315_time_init(void)
2674 +{
2675 +}
2676 +
2677 +#endif
2678 +
2679 +#endif
2680 --- /dev/null
2681 +++ b/arch/mips/ar231x/ar5312.h
2682 @@ -0,0 +1,37 @@
2683 +#ifndef __AR5312_H
2684 +#define __AR5312_H
2685 +
2686 +#ifdef CONFIG_ATHEROS_AR5312
2687 +
2688 +void ar5312_irq_init(void);
2689 +int ar5312_init_devices(void);
2690 +void ar5312_prom_init(void);
2691 +void ar5312_plat_setup(void);
2692 +void ar5312_time_init(void);
2693 +
2694 +#else
2695 +
2696 +static inline void ar5312_irq_init(void)
2697 +{
2698 +}
2699 +
2700 +static inline int ar5312_init_devices(void)
2701 +{
2702 + return 0;
2703 +}
2704 +
2705 +static inline void ar5312_prom_init(void)
2706 +{
2707 +}
2708 +
2709 +static inline void ar5312_plat_setup(void)
2710 +{
2711 +}
2712 +
2713 +static inline void ar5312_time_init(void)
2714 +{
2715 +}
2716 +
2717 +#endif
2718 +
2719 +#endif
2720 --- /dev/null
2721 +++ b/arch/mips/include/asm/mach-ar231x/ar231x.h
2722 @@ -0,0 +1,43 @@
2723 +#ifndef __ASM_MACH_AR231X_H
2724 +#define __ASM_MACH_AR231X_H
2725 +
2726 +#include <linux/types.h>
2727 +#include <linux/io.h>
2728 +
2729 +#define AR231X_MISC_IRQ_BASE 0x20
2730 +#define AR231X_GPIO_IRQ_BASE 0x30
2731 +
2732 +/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
2733 +#define AR231X_IRQ_NONE (MIPS_CPU_IRQ_BASE+0)
2734 +#define AR231X_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE+7) /* C0_CAUSE: 0x8000 */
2735 +
2736 +/* GPIO Interrupts, share ARXXXX_MISC_IRQ_GPIO */
2737 +#define AR231X_GPIO_IRQ_NONE (AR231X_GPIO_IRQ_BASE+0)
2738 +#define AR231X_GPIO_IRQ(n) (AR231X_GPIO_IRQ_BASE+n)
2739 +
2740 +static inline u32
2741 +ar231x_read_reg(u32 reg)
2742 +{
2743 + return __raw_readl((void __iomem *)KSEG1ADDR(reg));
2744 +}
2745 +
2746 +static inline void
2747 +ar231x_write_reg(u32 reg, u32 val)
2748 +{
2749 + __raw_writel(val, (void __iomem *)KSEG1ADDR(reg));
2750 +}
2751 +
2752 +static inline u32
2753 +ar231x_mask_reg(u32 reg, u32 mask, u32 val)
2754 +{
2755 + u32 ret;
2756 +
2757 + ret = ar231x_read_reg(reg);
2758 + ret &= ~mask;
2759 + ret |= val;
2760 + ar231x_write_reg(reg, ret);
2761 +
2762 + return ret;
2763 +}
2764 +
2765 +#endif /* __ASM_MACH_AR231X_H */
2766 --- /dev/null
2767 +++ b/arch/mips/ar231x/devices.h
2768 @@ -0,0 +1,38 @@
2769 +#ifndef __AR231X_DEVICES_H
2770 +#define __AR231X_DEVICES_H
2771 +
2772 +enum {
2773 + /* handled by ar5312.c */
2774 + DEV_TYPE_AR2312,
2775 + DEV_TYPE_AR2313,
2776 + DEV_TYPE_AR5312,
2777 +
2778 + /* handled by ar2315.c */
2779 + DEV_TYPE_AR2315,
2780 + DEV_TYPE_AR2316,
2781 + DEV_TYPE_AR2317,
2782 +
2783 + DEV_TYPE_UNKNOWN
2784 +};
2785 +
2786 +extern int ar231x_devtype;
2787 +extern struct ar231x_board_config ar231x_board;
2788 +extern asmlinkage void (*ar231x_irq_dispatch)(void);
2789 +
2790 +int ar231x_find_config(u8 *flash_limit);
2791 +void ar231x_serial_setup(u32 mapbase, int irq, unsigned int uartclk);
2792 +int ar231x_add_wmac(int nr, u32 base, int irq);
2793 +int ar231x_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
2794 + int irq, void *pdata);
2795 +
2796 +static inline bool is_2315(void)
2797 +{
2798 + return (current_cpu_data.cputype == CPU_4KEC);
2799 +}
2800 +
2801 +static inline bool is_5312(void)
2802 +{
2803 + return !is_2315();
2804 +}
2805 +
2806 +#endif
2807 --- /dev/null
2808 +++ b/arch/mips/ar231x/devices.c
2809 @@ -0,0 +1,180 @@
2810 +#include <linux/kernel.h>
2811 +#include <linux/init.h>
2812 +#include <linux/serial.h>
2813 +#include <linux/serial_core.h>
2814 +#include <linux/serial_8250.h>
2815 +#include <linux/platform_device.h>
2816 +#include <asm/bootinfo.h>
2817 +
2818 +#include <ar231x_platform.h>
2819 +#include <ar231x.h>
2820 +#include "devices.h"
2821 +#include "ar5312.h"
2822 +#include "ar2315.h"
2823 +
2824 +struct ar231x_board_config ar231x_board;
2825 +int ar231x_devtype = DEV_TYPE_UNKNOWN;
2826 +
2827 +static struct resource ar231x_eth0_res[] = {
2828 + {
2829 + .name = "eth0_membase",
2830 + .flags = IORESOURCE_MEM,
2831 + },
2832 + {
2833 + .name = "eth0_mii",
2834 + .flags = IORESOURCE_MEM,
2835 + },
2836 + {
2837 + .name = "eth0_irq",
2838 + .flags = IORESOURCE_IRQ,
2839 + }
2840 +};
2841 +
2842 +static struct resource ar231x_eth1_res[] = {
2843 + {
2844 + .name = "eth1_membase",
2845 + .flags = IORESOURCE_MEM,
2846 + },
2847 + {
2848 + .name = "eth1_mii",
2849 + .flags = IORESOURCE_MEM,
2850 + },
2851 + {
2852 + .name = "eth1_irq",
2853 + .flags = IORESOURCE_IRQ,
2854 + }
2855 +};
2856 +
2857 +static struct platform_device ar231x_eth[] = {
2858 + {
2859 + .id = 0,
2860 + .name = "ar231x-eth",
2861 + .resource = ar231x_eth0_res,
2862 + .num_resources = ARRAY_SIZE(ar231x_eth0_res)
2863 + },
2864 + {
2865 + .id = 1,
2866 + .name = "ar231x-eth",
2867 + .resource = ar231x_eth1_res,
2868 + .num_resources = ARRAY_SIZE(ar231x_eth1_res)
2869 + }
2870 +};
2871 +
2872 +static struct resource ar231x_wmac0_res[] = {
2873 + {
2874 + .name = "wmac0_membase",
2875 + .flags = IORESOURCE_MEM,
2876 + },
2877 + {
2878 + .name = "wmac0_irq",
2879 + .flags = IORESOURCE_IRQ,
2880 + }
2881 +};
2882 +
2883 +static struct resource ar231x_wmac1_res[] = {
2884 + {
2885 + .name = "wmac1_membase",
2886 + .flags = IORESOURCE_MEM,
2887 + },
2888 + {
2889 + .name = "wmac1_irq",
2890 + .flags = IORESOURCE_IRQ,
2891 + }
2892 +};
2893 +
2894 +static struct platform_device ar231x_wmac[] = {
2895 + {
2896 + .id = 0,
2897 + .name = "ar231x-wmac",
2898 + .resource = ar231x_wmac0_res,
2899 + .num_resources = ARRAY_SIZE(ar231x_wmac0_res),
2900 + .dev.platform_data = &ar231x_board,
2901 + },
2902 + {
2903 + .id = 1,
2904 + .name = "ar231x-wmac",
2905 + .resource = ar231x_wmac1_res,
2906 + .num_resources = ARRAY_SIZE(ar231x_wmac1_res),
2907 + .dev.platform_data = &ar231x_board,
2908 + },
2909 +};
2910 +
2911 +static const char * const devtype_strings[] = {
2912 + [DEV_TYPE_AR5312] = "Atheros AR5312",
2913 + [DEV_TYPE_AR2312] = "Atheros AR2312",
2914 + [DEV_TYPE_AR2313] = "Atheros AR2313",
2915 + [DEV_TYPE_AR2315] = "Atheros AR2315",
2916 + [DEV_TYPE_AR2316] = "Atheros AR2316",
2917 + [DEV_TYPE_AR2317] = "Atheros AR2317",
2918 + [DEV_TYPE_UNKNOWN] = "Atheros (unknown)",
2919 +};
2920 +
2921 +const char *get_system_type(void)
2922 +{
2923 + if ((ar231x_devtype >= ARRAY_SIZE(devtype_strings)) ||
2924 + !devtype_strings[ar231x_devtype])
2925 + return devtype_strings[DEV_TYPE_UNKNOWN];
2926 + return devtype_strings[ar231x_devtype];
2927 +}
2928 +
2929 +int __init
2930 +ar231x_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
2931 + int irq, void *pdata)
2932 +{
2933 + struct resource *res;
2934 +
2935 + ar231x_eth[nr].dev.platform_data = pdata;
2936 + res = &ar231x_eth[nr].resource[0];
2937 + res->start = base;
2938 + res->end = base + 0x2000 - 1;
2939 + res++;
2940 + res->name = mii_name;
2941 + res->start = mii_base;
2942 + res->end = mii_base + 8 - 1;
2943 + res++;
2944 + res->start = irq;
2945 + res->end = irq;
2946 + return platform_device_register(&ar231x_eth[nr]);
2947 +}
2948 +
2949 +void __init
2950 +ar231x_serial_setup(u32 mapbase, int irq, unsigned int uartclk)
2951 +{
2952 + struct uart_port s;
2953 +
2954 + memset(&s, 0, sizeof(s));
2955 +
2956 + s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP;
2957 + s.iotype = UPIO_MEM32;
2958 + s.irq = irq;
2959 + s.regshift = 2;
2960 + s.mapbase = mapbase;
2961 + s.uartclk = uartclk;
2962 +
2963 + early_serial_setup(&s);
2964 +}
2965 +
2966 +int __init
2967 +ar231x_add_wmac(int nr, u32 base, int irq)
2968 +{
2969 + struct resource *res;
2970 +
2971 + ar231x_wmac[nr].dev.platform_data = &ar231x_board;
2972 + res = &ar231x_wmac[nr].resource[0];
2973 + res->start = base;
2974 + res->end = base + 0x10000 - 1;
2975 + res++;
2976 + res->start = irq;
2977 + res->end = irq;
2978 + return platform_device_register(&ar231x_wmac[nr]);
2979 +}
2980 +
2981 +static int __init ar231x_register_devices(void)
2982 +{
2983 + ar5312_init_devices();
2984 + ar2315_init_devices();
2985 +
2986 + return 0;
2987 +}
2988 +
2989 +device_initcall(ar231x_register_devices);
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