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atheros: ar2315-pci: update host bridge resources
[openwrt/openwrt.git] / target / linux / atheros / patches-3.14 / 100-board.patch
1 --- a/arch/mips/Kconfig
2 +++ b/arch/mips/Kconfig
3 @@ -144,6 +144,19 @@ config BCM63XX
4 help
5 Support for BCM63XX based boards
6
7 +config ATHEROS_AR231X
8 + bool "Atheros 231x/531x SoC support"
9 + select CEVT_R4K
10 + select CSRC_R4K
11 + select DMA_NONCOHERENT
12 + select IRQ_CPU
13 + select SYS_HAS_CPU_MIPS32_R1
14 + select SYS_SUPPORTS_BIG_ENDIAN
15 + select SYS_SUPPORTS_32BIT_KERNEL
16 + select ARCH_REQUIRE_GPIOLIB
17 + help
18 + Support for AR231x and AR531x based boards
19 +
20 config MIPS_COBALT
21 bool "Cobalt Server"
22 select CEVT_R4K
23 @@ -795,6 +808,7 @@ config NLM_XLP_BOARD
24
25 endchoice
26
27 +source "arch/mips/ar231x/Kconfig"
28 source "arch/mips/alchemy/Kconfig"
29 source "arch/mips/ath79/Kconfig"
30 source "arch/mips/bcm47xx/Kconfig"
31 --- a/arch/mips/Kbuild.platforms
32 +++ b/arch/mips/Kbuild.platforms
33 @@ -6,6 +6,7 @@ platforms += ath79
34 platforms += bcm47xx
35 platforms += bcm63xx
36 platforms += cavium-octeon
37 +platforms += ar231x
38 platforms += cobalt
39 platforms += dec
40 platforms += emma
41 --- /dev/null
42 +++ b/arch/mips/ar231x/Platform
43 @@ -0,0 +1,6 @@
44 +#
45 +# Atheros AR531X/AR231X WiSoC
46 +#
47 +platform-$(CONFIG_ATHEROS_AR231X) += ar231x/
48 +cflags-$(CONFIG_ATHEROS_AR231X) += -I$(srctree)/arch/mips/include/asm/mach-ar231x
49 +load-$(CONFIG_ATHEROS_AR231X) += 0xffffffff80041000
50 --- /dev/null
51 +++ b/arch/mips/ar231x/Kconfig
52 @@ -0,0 +1,9 @@
53 +config ATHEROS_AR5312
54 + bool "Atheros 5312/2312+ support"
55 + depends on ATHEROS_AR231X
56 + default y
57 +
58 +config ATHEROS_AR2315
59 + bool "Atheros 2315+ support"
60 + depends on ATHEROS_AR231X
61 + default y
62 --- /dev/null
63 +++ b/arch/mips/ar231x/Makefile
64 @@ -0,0 +1,13 @@
65 +#
66 +# This file is subject to the terms and conditions of the GNU General Public
67 +# License. See the file "COPYING" in the main directory of this archive
68 +# for more details.
69 +#
70 +# Copyright (C) 2006 FON Technology, SL.
71 +# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
72 +# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
73 +#
74 +
75 +obj-y += board.o prom.o devices.o
76 +obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o
77 +obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o
78 --- /dev/null
79 +++ b/arch/mips/ar231x/board.c
80 @@ -0,0 +1,229 @@
81 +/*
82 + * This file is subject to the terms and conditions of the GNU General Public
83 + * License. See the file "COPYING" in the main directory of this archive
84 + * for more details.
85 + *
86 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
87 + * Copyright (C) 2006 FON Technology, SL.
88 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
89 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
90 + */
91 +
92 +#include <generated/autoconf.h>
93 +#include <linux/init.h>
94 +#include <linux/module.h>
95 +#include <linux/types.h>
96 +#include <linux/string.h>
97 +#include <linux/platform_device.h>
98 +#include <linux/kernel.h>
99 +#include <linux/random.h>
100 +#include <linux/etherdevice.h>
101 +#include <linux/irq.h>
102 +#include <linux/io.h>
103 +#include <asm/irq_cpu.h>
104 +#include <asm/reboot.h>
105 +#include <asm/bootinfo.h>
106 +#include <asm/time.h>
107 +
108 +#include <ar231x_platform.h>
109 +#include "devices.h"
110 +#include "ar5312.h"
111 +#include "ar2315.h"
112 +
113 +void (*ar231x_irq_dispatch)(void);
114 +
115 +static inline bool check_radio_magic(u8 *addr)
116 +{
117 + addr += 0x7a; /* offset for flash magic */
118 + return (addr[0] == 0x5a) && (addr[1] == 0xa5);
119 +}
120 +
121 +static inline bool check_notempty(u8 *addr)
122 +{
123 + return *(u32 *)addr != 0xffffffff;
124 +}
125 +
126 +static inline bool check_board_data(u8 *flash_limit, u8 *addr, bool broken)
127 +{
128 + /* config magic found */
129 + if (*((u32 *)addr) == AR231X_BD_MAGIC)
130 + return true;
131 +
132 + if (!broken)
133 + return false;
134 +
135 + if (check_radio_magic(addr + 0xf8))
136 + ar231x_board.radio = addr + 0xf8;
137 + if ((addr < flash_limit + 0x10000) &&
138 + check_radio_magic(addr + 0x10000))
139 + ar231x_board.radio = addr + 0x10000;
140 +
141 + if (ar231x_board.radio) {
142 + /* broken board data detected, use radio data to find the
143 + * offset, user will fix this */
144 + return true;
145 + }
146 +
147 + return false;
148 +}
149 +
150 +static u8 * __init find_board_config(u8 *flash_limit, bool broken)
151 +{
152 + u8 *addr;
153 + u8 *begin = flash_limit - 0x1000;
154 + u8 *end = flash_limit - 0x30000;
155 +
156 + for (addr = begin; addr >= end; addr -= 0x1000)
157 + if (check_board_data(flash_limit, addr, broken))
158 + return addr;
159 +
160 + return NULL;
161 +}
162 +
163 +static u8 * __init find_radio_config(u8 *flash_limit, u8 *bcfg)
164 +{
165 + u8 *rcfg, *begin, *end;
166 +
167 + /*
168 + * Now find the start of Radio Configuration data, using heuristics:
169 + * Search forward from Board Configuration data by 0x1000 bytes
170 + * at a time until we find non-0xffffffff.
171 + */
172 + begin = bcfg + 0x1000;
173 + end = flash_limit;
174 + for (rcfg = begin; rcfg < end; rcfg += 0x1000)
175 + if (check_notempty(rcfg) && check_radio_magic(rcfg))
176 + return rcfg;
177 +
178 + /* AR2316 relocates radio config to new location */
179 + begin = bcfg + 0xf8;
180 + end = flash_limit - 0x1000 + 0xf8;
181 + for (rcfg = begin; rcfg < end; rcfg += 0x1000)
182 + if (check_notempty(rcfg) && check_radio_magic(rcfg))
183 + return rcfg;
184 +
185 + pr_warn("WARNING: Could not find Radio Configuration data\n");
186 +
187 + return NULL;
188 +}
189 +
190 +int __init ar231x_find_config(u8 *flash_limit)
191 +{
192 + struct ar231x_boarddata *config;
193 + unsigned int rcfg_size;
194 + int broken_boarddata = 0;
195 + u8 *bcfg, *rcfg;
196 + u8 *board_data;
197 + u8 *radio_data;
198 + u8 *mac_addr;
199 + u32 offset;
200 +
201 + ar231x_board.config = NULL;
202 + ar231x_board.radio = NULL;
203 + /* Copy the board and radio data to RAM, because accessing the mapped
204 + * memory of the flash directly after booting is not safe */
205 +
206 + /* Try to find valid board and radio data */
207 + bcfg = find_board_config(flash_limit, false);
208 +
209 + /* If that fails, try to at least find valid radio data */
210 + if (!bcfg) {
211 + bcfg = find_board_config(flash_limit, true);
212 + broken_boarddata = 1;
213 + }
214 +
215 + if (!bcfg) {
216 + pr_warn("WARNING: No board configuration data found!\n");
217 + return -ENODEV;
218 + }
219 +
220 + board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
221 + ar231x_board.config = (struct ar231x_boarddata *)board_data;
222 + memcpy(board_data, bcfg, 0x100);
223 + if (broken_boarddata) {
224 + pr_warn("WARNING: broken board data detected\n");
225 + config = ar231x_board.config;
226 + if (is_zero_ether_addr(config->enet0_mac)) {
227 + pr_info("Fixing up empty mac addresses\n");
228 + config->reset_config_gpio = 0xffff;
229 + config->sys_led_gpio = 0xffff;
230 + random_ether_addr(config->wlan0_mac);
231 + config->wlan0_mac[0] &= ~0x06;
232 + random_ether_addr(config->enet0_mac);
233 + random_ether_addr(config->enet1_mac);
234 + }
235 + }
236 +
237 + /* Radio config starts 0x100 bytes after board config, regardless
238 + * of what the physical layout on the flash chip looks like */
239 +
240 + if (ar231x_board.radio)
241 + rcfg = (u8 *)ar231x_board.radio;
242 + else
243 + rcfg = find_radio_config(flash_limit, bcfg);
244 +
245 + if (!rcfg)
246 + return -ENODEV;
247 +
248 + radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
249 + ar231x_board.radio = radio_data;
250 + offset = radio_data - board_data;
251 + pr_info("Radio config found at offset 0x%x (0x%x)\n", rcfg - bcfg,
252 + offset);
253 + rcfg_size = BOARD_CONFIG_BUFSZ - offset;
254 + memcpy(radio_data, rcfg, rcfg_size);
255 +
256 + mac_addr = &radio_data[0x1d * 2];
257 + if (is_broadcast_ether_addr(mac_addr)) {
258 + pr_info("Radio MAC is blank; using board-data\n");
259 + ether_addr_copy(mac_addr, ar231x_board.config->wlan0_mac);
260 + }
261 +
262 + return 0;
263 +}
264 +
265 +static void ar231x_halt(void)
266 +{
267 + local_irq_disable();
268 + while (1)
269 + ;
270 +}
271 +
272 +void __init plat_mem_setup(void)
273 +{
274 + _machine_halt = ar231x_halt;
275 + pm_power_off = ar231x_halt;
276 +
277 + ar5312_plat_setup();
278 + ar2315_plat_setup();
279 +
280 + /* Disable data watchpoints */
281 + write_c0_watchlo0(0);
282 +}
283 +
284 +asmlinkage void plat_irq_dispatch(void)
285 +{
286 + ar231x_irq_dispatch();
287 +}
288 +
289 +void __init plat_time_init(void)
290 +{
291 + ar5312_time_init();
292 + ar2315_time_init();
293 +}
294 +
295 +unsigned int __cpuinit get_c0_compare_int(void)
296 +{
297 + return CP0_LEGACY_COMPARE_IRQ;
298 +}
299 +
300 +void __init arch_init_irq(void)
301 +{
302 + clear_c0_status(ST0_IM);
303 + mips_cpu_irq_init();
304 +
305 + /* Initialize interrupt controllers */
306 + ar5312_irq_init();
307 + ar2315_irq_init();
308 +}
309 +
310 --- /dev/null
311 +++ b/arch/mips/ar231x/prom.c
312 @@ -0,0 +1,37 @@
313 +/*
314 + * This file is subject to the terms and conditions of the GNU General Public
315 + * License. See the file "COPYING" in the main directory of this archive
316 + * for more details.
317 + *
318 + * Copyright MontaVista Software Inc
319 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
320 + * Copyright (C) 2006 FON Technology, SL.
321 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
322 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
323 + */
324 +
325 +/*
326 + * Prom setup file for ar231x
327 + */
328 +
329 +#include <linux/init.h>
330 +#include <generated/autoconf.h>
331 +#include <linux/kernel.h>
332 +#include <linux/string.h>
333 +#include <linux/mm.h>
334 +#include <linux/bootmem.h>
335 +
336 +#include <asm/bootinfo.h>
337 +#include <asm/addrspace.h>
338 +#include "ar5312.h"
339 +#include "ar2315.h"
340 +
341 +void __init prom_init(void)
342 +{
343 + ar5312_prom_init();
344 + ar2315_prom_init();
345 +}
346 +
347 +void __init prom_free_prom_memory(void)
348 +{
349 +}
350 --- /dev/null
351 +++ b/arch/mips/include/asm/mach-ar231x/ar231x_platform.h
352 @@ -0,0 +1,85 @@
353 +#ifndef __ASM_MACH_AR231X_PLATFORM_H
354 +#define __ASM_MACH_AR231X_PLATFORM_H
355 +
356 +#include <linux/etherdevice.h>
357 +
358 +/*
359 + * This is board-specific data that is stored in a "fixed" location in flash.
360 + * It is shared across operating systems, so it should not be changed lightly.
361 + * The main reason we need it is in order to extract the ethernet MAC
362 + * address(es).
363 + */
364 +struct ar231x_boarddata {
365 + u32 magic; /* board data is valid */
366 +#define AR231X_BD_MAGIC 0x35333131 /* "5311", for all 531x/231x platforms */
367 + u16 cksum; /* checksum (starting with BD_REV 2) */
368 + u16 rev; /* revision of this struct */
369 +#define BD_REV 4
370 + char board_name[64]; /* Name of board */
371 + u16 major; /* Board major number */
372 + u16 minor; /* Board minor number */
373 + u32 flags; /* Board configuration */
374 +#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
375 +#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
376 +#define BD_UART1 0x00000004 /* UART1 is stuffed */
377 +#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
378 +#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
379 +#define BD_SYSLED 0x00000020 /* System LED stuffed */
380 +#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
381 +#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
382 +#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
383 +#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
384 +#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ mem_cap for testing */
385 +#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
386 +#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
387 +#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
388 +#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
389 +#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
390 +#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
391 +#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
392 + u16 reset_config_gpio; /* Reset factory GPIO pin */
393 + u16 sys_led_gpio; /* System LED GPIO pin */
394 +
395 + u32 cpu_freq; /* CPU core frequency in Hz */
396 + u32 sys_freq; /* System frequency in Hz */
397 + u32 cnt_freq; /* Calculated C0_COUNT frequency */
398 +
399 + u8 wlan0_mac[ETH_ALEN];
400 + u8 enet0_mac[ETH_ALEN];
401 + u8 enet1_mac[ETH_ALEN];
402 +
403 + u16 pci_id; /* Pseudo PCIID for common code */
404 + u16 mem_cap; /* cap bank1 in MB */
405 +
406 + /* version 3 */
407 + u8 wlan1_mac[ETH_ALEN]; /* (ar5212) */
408 +};
409 +
410 +#define BOARD_CONFIG_BUFSZ 0x1000
411 +
412 +/*
413 + * Platform device information for the Wireless MAC
414 + */
415 +struct ar231x_board_config {
416 + u16 devid;
417 +
418 + /* board config data */
419 + struct ar231x_boarddata *config;
420 +
421 + /* radio calibration data */
422 + const char *radio;
423 +};
424 +
425 +/*
426 + * Platform device information for the Ethernet MAC
427 + */
428 +struct ar231x_eth {
429 + void (*reset_set)(u32);
430 + void (*reset_clear)(u32);
431 + u32 reset_mac;
432 + u32 reset_phy;
433 + struct ar231x_board_config *config;
434 + char *macaddr;
435 +};
436 +
437 +#endif /* __ASM_MACH_AR231X_PLATFORM_H */
438 --- /dev/null
439 +++ b/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h
440 @@ -0,0 +1,84 @@
441 +/*
442 + * Atheros AR231x/AR531x SoC specific CPU feature overrides
443 + *
444 + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
445 + *
446 + * This file was derived from: include/asm-mips/cpu-features.h
447 + * Copyright (C) 2003, 2004 Ralf Baechle
448 + * Copyright (C) 2004 Maciej W. Rozycki
449 + *
450 + * This program is free software; you can redistribute it and/or modify it
451 + * under the terms of the GNU General Public License version 2 as published
452 + * by the Free Software Foundation.
453 + *
454 + */
455 +#ifndef __ASM_MACH_AR231X_CPU_FEATURE_OVERRIDES_H
456 +#define __ASM_MACH_AR231X_CPU_FEATURE_OVERRIDES_H
457 +
458 +/*
459 + * The Atheros AR531x/AR231x SoCs have MIPS 4Kc/4KEc core.
460 + */
461 +#define cpu_has_tlb 1
462 +#define cpu_has_4kex 1
463 +#define cpu_has_3k_cache 0
464 +#define cpu_has_4k_cache 1
465 +#define cpu_has_tx39_cache 0
466 +#define cpu_has_sb1_cache 0
467 +#define cpu_has_fpu 0
468 +#define cpu_has_32fpr 0
469 +#define cpu_has_counter 1
470 +/* #define cpu_has_watch ? */
471 +/* #define cpu_has_divec ? */
472 +/* #define cpu_has_vce ? */
473 +/* #define cpu_has_cache_cdex_p ? */
474 +/* #define cpu_has_cache_cdex_s ? */
475 +/* #define cpu_has_prefetch ? */
476 +/* #define cpu_has_mcheck ? */
477 +#define cpu_has_ejtag 1
478 +
479 +#if !defined(CONFIG_ATHEROS_AR5312)
480 +# define cpu_has_llsc 1
481 +#else
482 +/*
483 + * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
484 + * ll/sc instructions.
485 + */
486 +# define cpu_has_llsc 0
487 +#endif
488 +
489 +#define cpu_has_mips16 0
490 +#define cpu_has_mdmx 0
491 +#define cpu_has_mips3d 0
492 +#define cpu_has_smartmips 0
493 +
494 +/* #define cpu_has_vtag_icache ? */
495 +/* #define cpu_has_dc_aliases ? */
496 +/* #define cpu_has_ic_fills_f_dc ? */
497 +/* #define cpu_has_pindexed_dcache ? */
498 +
499 +/* #define cpu_icache_snoops_remote_store ? */
500 +
501 +#define cpu_has_mips32r1 1
502 +
503 +#if !defined(CONFIG_ATHEROS_AR5312)
504 +# define cpu_has_mips32r2 1
505 +#endif
506 +
507 +#define cpu_has_mips64r1 0
508 +#define cpu_has_mips64r2 0
509 +
510 +#define cpu_has_dsp 0
511 +#define cpu_has_mipsmt 0
512 +
513 +/* #define cpu_has_nofpuex ? */
514 +#define cpu_has_64bits 0
515 +#define cpu_has_64bit_zero_reg 0
516 +#define cpu_has_64bit_gp_regs 0
517 +#define cpu_has_64bit_addresses 0
518 +
519 +/* #define cpu_has_inclusive_pcaches ? */
520 +
521 +/* #define cpu_dcache_line_size() ? */
522 +/* #define cpu_icache_line_size() ? */
523 +
524 +#endif /* __ASM_MACH_AR231X_CPU_FEATURE_OVERRIDES_H */
525 --- /dev/null
526 +++ b/arch/mips/include/asm/mach-ar231x/dma-coherence.h
527 @@ -0,0 +1,77 @@
528 +/*
529 + * This file is subject to the terms and conditions of the GNU General Public
530 + * License. See the file "COPYING" in the main directory of this archive
531 + * for more details.
532 + *
533 + * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
534 + * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
535 + *
536 + */
537 +#ifndef __ASM_MACH_AR231X_DMA_COHERENCE_H
538 +#define __ASM_MACH_AR231X_DMA_COHERENCE_H
539 +
540 +#define PCI_DMA_OFFSET 0x20000000
541 +
542 +#include <linux/device.h>
543 +
544 +static inline dma_addr_t ar231x_dev_offset(struct device *dev)
545 +{
546 +#ifdef CONFIG_PCI
547 + extern struct bus_type pci_bus_type;
548 +
549 + if (dev && dev->bus == &pci_bus_type)
550 + return PCI_DMA_OFFSET;
551 +#endif
552 + return 0;
553 +}
554 +
555 +static inline dma_addr_t
556 +plat_map_dma_mem(struct device *dev, void *addr, size_t size)
557 +{
558 + return virt_to_phys(addr) + ar231x_dev_offset(dev);
559 +}
560 +
561 +static inline dma_addr_t
562 +plat_map_dma_mem_page(struct device *dev, struct page *page)
563 +{
564 + return page_to_phys(page) + ar231x_dev_offset(dev);
565 +}
566 +
567 +static inline unsigned long
568 +plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
569 +{
570 + return dma_addr - ar231x_dev_offset(dev);
571 +}
572 +
573 +static inline void
574 +plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, size_t size,
575 + enum dma_data_direction direction)
576 +{
577 +}
578 +
579 +static inline int plat_dma_supported(struct device *dev, u64 mask)
580 +{
581 + return 1;
582 +}
583 +
584 +static inline void plat_extra_sync_for_device(struct device *dev)
585 +{
586 +}
587 +
588 +static inline int plat_dma_mapping_error(struct device *dev,
589 + dma_addr_t dma_addr)
590 +{
591 + return 0;
592 +}
593 +
594 +static inline int plat_device_is_coherent(struct device *dev)
595 +{
596 +#ifdef CONFIG_DMA_COHERENT
597 + return 1;
598 +#endif
599 +#ifdef CONFIG_DMA_NONCOHERENT
600 + return 0;
601 +#endif
602 +}
603 +
604 +#endif /* __ASM_MACH_AR231X_DMA_COHERENCE_H */
605 --- /dev/null
606 +++ b/arch/mips/include/asm/mach-ar231x/gpio.h
607 @@ -0,0 +1,30 @@
608 +#ifndef __ASM_MACH_AR231X_GPIO_H
609 +#define __ASM_MACH_AR231X_GPIO_H
610 +
611 +#include <ar231x.h>
612 +
613 +#define gpio_get_value __gpio_get_value
614 +#define gpio_set_value __gpio_set_value
615 +#define gpio_cansleep __gpio_cansleep
616 +
617 +/*
618 + * Wrappers for the generic GPIO layer
619 + */
620 +
621 +/* not sure if these are used? */
622 +
623 +/* Returns IRQ to attach for gpio. Unchecked function */
624 +static inline int gpio_to_irq(unsigned gpio)
625 +{
626 + return AR231X_GPIO_IRQ(gpio);
627 +}
628 +
629 +/* Returns gpio for IRQ attached. Unchecked function */
630 +static inline int irq_to_gpio(unsigned irq)
631 +{
632 + return irq - AR231X_GPIO_IRQ(0);
633 +}
634 +
635 +#include <asm-generic/gpio.h> /* cansleep wrappers */
636 +
637 +#endif /* __ASM_MACH_AR231X_GPIO_H */
638 --- /dev/null
639 +++ b/arch/mips/include/asm/mach-ar231x/reset.h
640 @@ -0,0 +1,6 @@
641 +#ifndef __ASM_MACH_AR231X_RESET_H
642 +#define __ASM_MACH_AR231X_RESET_H
643 +
644 +void ar231x_disable_reset_button(void);
645 +
646 +#endif /* __ASM_MACH_AR231X_RESET_H */
647 --- /dev/null
648 +++ b/arch/mips/include/asm/mach-ar231x/war.h
649 @@ -0,0 +1,25 @@
650 +/*
651 + * This file is subject to the terms and conditions of the GNU General Public
652 + * License. See the file "COPYING" in the main directory of this archive
653 + * for more details.
654 + *
655 + * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
656 + */
657 +#ifndef __ASM_MACH_AR231X_WAR_H
658 +#define __ASM_MACH_AR231X_WAR_H
659 +
660 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
661 +#define R4600_V1_HIT_CACHEOP_WAR 0
662 +#define R4600_V2_HIT_CACHEOP_WAR 0
663 +#define R5432_CP0_INTERRUPT_WAR 0
664 +#define BCM1250_M3_WAR 0
665 +#define SIBYTE_1956_WAR 0
666 +#define MIPS4K_ICACHE_REFILL_WAR 0
667 +#define MIPS_CACHE_SYNC_WAR 0
668 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
669 +#define RM9000_CDEX_SMP_WAR 0
670 +#define ICACHE_REFILLS_WORKAROUND_WAR 0
671 +#define R10000_LLSC_WAR 0
672 +#define MIPS34K_MISSED_ITLB_WAR 0
673 +
674 +#endif /* __ASM_MACH_AR231X_WAR_H */
675 --- /dev/null
676 +++ b/arch/mips/include/asm/mach-ar231x/ar2315_regs.h
677 @@ -0,0 +1,625 @@
678 +/*
679 + * Register definitions for AR2315+
680 + *
681 + * This file is subject to the terms and conditions of the GNU General Public
682 + * License. See the file "COPYING" in the main directory of this archive
683 + * for more details.
684 + *
685 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
686 + * Copyright (C) 2006 FON Technology, SL.
687 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
688 + * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
689 + */
690 +
691 +#ifndef __ASM_MACH_AR231X_AR2315_REGS_H
692 +#define __ASM_MACH_AR231X_AR2315_REGS_H
693 +
694 +/*
695 + * IRQs
696 + */
697 +#define AR2315_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
698 +#define AR2315_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
699 +#define AR2315_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
700 +#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
701 +#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
702 +
703 +/*
704 + * Miscellaneous interrupts, which share IP2.
705 + */
706 +#define AR2315_MISC_IRQ_NONE (AR231X_MISC_IRQ_BASE+0)
707 +#define AR2315_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+1)
708 +#define AR2315_MISC_IRQ_I2C_RSVD (AR231X_MISC_IRQ_BASE+2)
709 +#define AR2315_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+3)
710 +#define AR2315_MISC_IRQ_AHB (AR231X_MISC_IRQ_BASE+4)
711 +#define AR2315_MISC_IRQ_APB (AR231X_MISC_IRQ_BASE+5)
712 +#define AR2315_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+6)
713 +#define AR2315_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+7)
714 +#define AR2315_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+8)
715 +#define AR2315_MISC_IRQ_IR_RSVD (AR231X_MISC_IRQ_BASE+9)
716 +#define AR2315_MISC_IRQ_COUNT 10
717 +
718 +/*
719 + * PCI interrupts, which share IP5
720 + * Keep ordered according to AR2315_PCI_INT_XXX bits
721 + */
722 +#define AR2315_PCI_IRQ_BASE 0x50
723 +#define AR2315_PCI_IRQ_EXT (AR2315_PCI_IRQ_BASE+0)
724 +#define AR2315_PCI_IRQ_ABORT (AR2315_PCI_IRQ_BASE+1)
725 +#define AR2315_PCI_IRQ_COUNT 2
726 +#define AR2315_PCI_IRQ_SHIFT 25 /* in AR2315_PCI_INT_STATUS */
727 +
728 +/*
729 + * Address map
730 + */
731 +#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */
732 +#define AR2315_WLAN0 0x10000000 /* Wireless MMR */
733 +#define AR2315_PCI 0x10100000 /* PCI MMR */
734 +#define AR2315_SDRAMCTL 0x10300000 /* SDRAM MMR */
735 +#define AR2315_LOCAL 0x10400000 /* LOCAL BUS MMR */
736 +#define AR2315_ENET0 0x10500000 /* ETHERNET MMR */
737 +#define AR2315_DSLBASE 0x11000000 /* RESET CONTROL MMR */
738 +#define AR2315_UART0 0x11100000 /* UART MMR */
739 +#define AR2315_SPI_MMR 0x11300000 /* SPI FLASH MMR */
740 +#define AR2315_PCIEXT 0x80000000 /* pci external */
741 +#define AR2315_PCIEXT_SZ 0x40000000
742 +
743 +/* MII registers offset inside Ethernet MMR region */
744 +#define AR2315_ENET0_MII (AR2315_ENET0 + 0x14)
745 +
746 +/*
747 + * Cold reset register
748 + */
749 +#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000)
750 +
751 +#define AR2315_RESET_COLD_AHB 0x00000001
752 +#define AR2315_RESET_COLD_APB 0x00000002
753 +#define AR2315_RESET_COLD_CPU 0x00000004
754 +#define AR2315_RESET_COLD_CPUWARM 0x00000008
755 +#define AR2315_RESET_SYSTEM \
756 + (RESET_COLD_CPU |\
757 + RESET_COLD_APB |\
758 + RESET_COLD_AHB) /* full system */
759 +#define AR2317_RESET_SYSTEM 0x00000010
760 +
761 +/*
762 + * Reset register
763 + */
764 +#define AR2315_RESET (AR2315_DSLBASE + 0x0004)
765 +
766 +/* warm reset WLAN0 MAC */
767 +#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001
768 +/* warm reset WLAN0 BaseBand */
769 +#define AR2315_RESET_WARM_WLAN0_BB 0x00000002
770 +/* warm reset MPEG-TS */
771 +#define AR2315_RESET_MPEGTS_RSVD 0x00000004
772 +/* warm reset PCI ahb/dma */
773 +#define AR2315_RESET_PCIDMA 0x00000008
774 +/* warm reset memory controller */
775 +#define AR2315_RESET_MEMCTL 0x00000010
776 +/* warm reset local bus */
777 +#define AR2315_RESET_LOCAL 0x00000020
778 +/* warm reset I2C bus */
779 +#define AR2315_RESET_I2C_RSVD 0x00000040
780 +/* warm reset SPI interface */
781 +#define AR2315_RESET_SPI 0x00000080
782 +/* warm reset UART0 */
783 +#define AR2315_RESET_UART0 0x00000100
784 +/* warm reset IR interface */
785 +#define AR2315_RESET_IR_RSVD 0x00000200
786 +/* cold reset ENET0 phy */
787 +#define AR2315_RESET_EPHY0 0x00000400
788 +/* cold reset ENET0 mac */
789 +#define AR2315_RESET_ENET0 0x00000800
790 +
791 +/*
792 + * AHB master arbitration control
793 + */
794 +#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008)
795 +
796 +/* CPU, default */
797 +#define AR2315_ARB_CPU 0x00000001
798 +/* WLAN */
799 +#define AR2315_ARB_WLAN 0x00000002
800 +/* MPEG-TS */
801 +#define AR2315_ARB_MPEGTS_RSVD 0x00000004
802 +/* LOCAL */
803 +#define AR2315_ARB_LOCAL 0x00000008
804 +/* PCI */
805 +#define AR2315_ARB_PCI 0x00000010
806 +/* Ethernet */
807 +#define AR2315_ARB_ETHERNET 0x00000020
808 +/* retry policy, debug only */
809 +#define AR2315_ARB_RETRY 0x00000100
810 +
811 +/*
812 + * Config Register
813 + */
814 +#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c)
815 +
816 +/* EC - AHB bridge endianess */
817 +#define AR2315_CONFIG_AHB 0x00000001
818 +/* WLAN byteswap */
819 +#define AR2315_CONFIG_WLAN 0x00000002
820 +/* MPEG-TS byteswap */
821 +#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004
822 +/* PCI byteswap */
823 +#define AR2315_CONFIG_PCI 0x00000008
824 +/* Memory controller endianess */
825 +#define AR2315_CONFIG_MEMCTL 0x00000010
826 +/* Local bus byteswap */
827 +#define AR2315_CONFIG_LOCAL 0x00000020
828 +/* Ethernet byteswap */
829 +#define AR2315_CONFIG_ETHERNET 0x00000040
830 +
831 +/* CPU write buffer merge */
832 +#define AR2315_CONFIG_MERGE 0x00000200
833 +/* CPU big endian */
834 +#define AR2315_CONFIG_CPU 0x00000400
835 +#define AR2315_CONFIG_PCIAHB 0x00000800
836 +#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
837 +/* SPI byteswap */
838 +#define AR2315_CONFIG_SPI 0x00008000
839 +#define AR2315_CONFIG_CPU_DRAM 0x00010000
840 +#define AR2315_CONFIG_CPU_PCI 0x00020000
841 +#define AR2315_CONFIG_CPU_MMR 0x00040000
842 +#define AR2315_CONFIG_BIG 0x00000400
843 +
844 +/*
845 + * NMI control
846 + */
847 +#define AR2315_NMI_CTL (AR2315_DSLBASE + 0x0010)
848 +
849 +#define AR2315_NMI_EN 1
850 +
851 +/*
852 + * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR231X 1.0).
853 + */
854 +#define AR2315_SREV (AR2315_DSLBASE + 0x0014)
855 +
856 +#define AR2315_REV_MAJ 0x00f0
857 +#define AR2315_REV_MAJ_S 4
858 +#define AR2315_REV_MIN 0x000f
859 +#define AR2315_REV_MIN_S 0
860 +#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN)
861 +
862 +/*
863 + * Interface Enable
864 + */
865 +#define AR2315_IF_CTL (AR2315_DSLBASE + 0x0018)
866 +
867 +#define AR2315_IF_MASK 0x00000007
868 +#define AR2315_IF_DISABLED 0
869 +#define AR2315_IF_PCI 1
870 +#define AR2315_IF_TS_LOCAL 2
871 +/* only for emulation with separate pins */
872 +#define AR2315_IF_ALL 3
873 +#define AR2315_IF_LOCAL_HOST 0x00000008
874 +#define AR2315_IF_PCI_HOST 0x00000010
875 +#define AR2315_IF_PCI_INTR 0x00000020
876 +#define AR2315_IF_PCI_CLK_MASK 0x00030000
877 +#define AR2315_IF_PCI_CLK_INPUT 0
878 +#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
879 +#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
880 +#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
881 +#define AR2315_IF_PCI_CLK_SHIFT 16
882 +
883 +/*
884 + * APB Interrupt control
885 + */
886 +
887 +#define AR2315_ISR (AR2315_DSLBASE + 0x0020)
888 +#define AR2315_IMR (AR2315_DSLBASE + 0x0024)
889 +#define AR2315_GISR (AR2315_DSLBASE + 0x0028)
890 +
891 +#define AR2315_ISR_UART0 0x0001 /* high speed UART */
892 +#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */
893 +#define AR2315_ISR_SPI 0x0004 /* SPI bus */
894 +#define AR2315_ISR_AHB 0x0008 /* AHB error */
895 +#define AR2315_ISR_APB 0x0010 /* APB error */
896 +#define AR2315_ISR_TIMER 0x0020 /* timer */
897 +#define AR2315_ISR_GPIO 0x0040 /* GPIO */
898 +#define AR2315_ISR_WD 0x0080 /* watchdog */
899 +#define AR2315_ISR_IR_RSVD 0x0100 /* IR */
900 +
901 +#define AR2315_GISR_MISC 0x0001
902 +#define AR2315_GISR_WLAN0 0x0002
903 +#define AR2315_GISR_MPEGTS_RSVD 0x0004
904 +#define AR2315_GISR_LOCALPCI 0x0008
905 +#define AR2315_GISR_WMACPOLL 0x0010
906 +#define AR2315_GISR_TIMER 0x0020
907 +#define AR2315_GISR_ETHERNET 0x0040
908 +
909 +/*
910 + * Interrupt routing from IO to the processor IP bits
911 + * Define our inter mask and level
912 + */
913 +#define AR2315_INTR_MISCIO SR_IBIT3
914 +#define AR2315_INTR_WLAN0 SR_IBIT4
915 +#define AR2315_INTR_ENET0 SR_IBIT5
916 +#define AR2315_INTR_LOCALPCI SR_IBIT6
917 +#define AR2315_INTR_WMACPOLL SR_IBIT7
918 +#define AR2315_INTR_COMPARE SR_IBIT8
919 +
920 +/*
921 + * Timers
922 + */
923 +#define AR2315_TIMER (AR2315_DSLBASE + 0x0030)
924 +#define AR2315_RELOAD (AR2315_DSLBASE + 0x0034)
925 +#define AR2315_WD (AR2315_DSLBASE + 0x0038)
926 +#define AR2315_WDC (AR2315_DSLBASE + 0x003c)
927 +
928 +#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000
929 +#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */
930 +#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */
931 +
932 +/*
933 + * CPU Performance Counters
934 + */
935 +#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048)
936 +#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c)
937 +
938 +#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */
939 +#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */
940 +#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */
941 +#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */
942 +#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */
943 +#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */
944 +#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */
945 +
946 +#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */
947 +#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */
948 +#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */
949 +#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */
950 +#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */
951 +#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */
952 +#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */
953 +
954 +/*
955 + * AHB Error Reporting.
956 + */
957 +#define AR2315_AHB_ERR0 (AR2315_DSLBASE + 0x0050) /* error */
958 +#define AR2315_AHB_ERR1 (AR2315_DSLBASE + 0x0054) /* haddr */
959 +#define AR2315_AHB_ERR2 (AR2315_DSLBASE + 0x0058) /* hwdata */
960 +#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */
961 +#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */
962 +
963 +#define AHB_ERROR_DET 1 /* AHB Error has been detected, */
964 + /* write 1 to clear all bits in ERR0 */
965 +#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
966 +#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
967 +
968 +#define AR2315_PROCERR_HMAST 0x0000000f
969 +#define AR2315_PROCERR_HMAST_DFLT 0
970 +#define AR2315_PROCERR_HMAST_WMAC 1
971 +#define AR2315_PROCERR_HMAST_ENET 2
972 +#define AR2315_PROCERR_HMAST_PCIENDPT 3
973 +#define AR2315_PROCERR_HMAST_LOCAL 4
974 +#define AR2315_PROCERR_HMAST_CPU 5
975 +#define AR2315_PROCERR_HMAST_PCITGT 6
976 +
977 +#define AR2315_PROCERR_HMAST_S 0
978 +#define AR2315_PROCERR_HWRITE 0x00000010
979 +#define AR2315_PROCERR_HSIZE 0x00000060
980 +#define AR2315_PROCERR_HSIZE_S 5
981 +#define AR2315_PROCERR_HTRANS 0x00000180
982 +#define AR2315_PROCERR_HTRANS_S 7
983 +#define AR2315_PROCERR_HBURST 0x00000e00
984 +#define AR2315_PROCERR_HBURST_S 9
985 +
986 +/*
987 + * Clock Control
988 + */
989 +#define AR2315_PLLC_CTL (AR2315_DSLBASE + 0x0064)
990 +#define AR2315_PLLV_CTL (AR2315_DSLBASE + 0x0068)
991 +#define AR2315_CPUCLK (AR2315_DSLBASE + 0x006c)
992 +#define AR2315_AMBACLK (AR2315_DSLBASE + 0x0070)
993 +#define AR2315_SYNCCLK (AR2315_DSLBASE + 0x0074)
994 +#define AR2315_DSL_SLEEP_CTL (AR2315_DSLBASE + 0x0080)
995 +#define AR2315_DSL_SLEEP_DUR (AR2315_DSLBASE + 0x0084)
996 +
997 +/* PLLc Control fields */
998 +#define PLLC_REF_DIV_M 0x00000003
999 +#define PLLC_REF_DIV_S 0
1000 +#define PLLC_FDBACK_DIV_M 0x0000007C
1001 +#define PLLC_FDBACK_DIV_S 2
1002 +#define PLLC_ADD_FDBACK_DIV_M 0x00000080
1003 +#define PLLC_ADD_FDBACK_DIV_S 7
1004 +#define PLLC_CLKC_DIV_M 0x0001c000
1005 +#define PLLC_CLKC_DIV_S 14
1006 +#define PLLC_CLKM_DIV_M 0x00700000
1007 +#define PLLC_CLKM_DIV_S 20
1008 +
1009 +/* CPU CLK Control fields */
1010 +#define CPUCLK_CLK_SEL_M 0x00000003
1011 +#define CPUCLK_CLK_SEL_S 0
1012 +#define CPUCLK_CLK_DIV_M 0x0000000c
1013 +#define CPUCLK_CLK_DIV_S 2
1014 +
1015 +/* AMBA CLK Control fields */
1016 +#define AMBACLK_CLK_SEL_M 0x00000003
1017 +#define AMBACLK_CLK_SEL_S 0
1018 +#define AMBACLK_CLK_DIV_M 0x0000000c
1019 +#define AMBACLK_CLK_DIV_S 2
1020 +
1021 +/*
1022 + * GPIO
1023 + */
1024 +#define AR2315_GPIO_DI (AR2315_DSLBASE + 0x0088)
1025 +#define AR2315_GPIO_DO (AR2315_DSLBASE + 0x0090)
1026 +#define AR2315_GPIO_DIR (AR2315_DSLBASE + 0x0098)
1027 +#define AR2315_GPIO_INT (AR2315_DSLBASE + 0x00a0)
1028 +
1029 +#define AR2315_GPIO_DIR_M(x) (1 << (x)) /* mask for i/o */
1030 +#define AR2315_GPIO_DIR_O(x) (1 << (x)) /* output */
1031 +#define AR2315_GPIO_DIR_I(x) (0) /* input */
1032 +
1033 +#define AR2315_GPIO_INT_S(x) (x) /* interrupt enable */
1034 +#define AR2315_GPIO_INT_M (0x3F) /* mask for int */
1035 +#define AR2315_GPIO_INT_LVL(x) ((x) << 6) /* interrupt level */
1036 +#define AR2315_GPIO_INT_LVL_M ((0x3) << 6) /* mask for int level */
1037 +
1038 +#define AR2315_GPIO_INT_MAX_Y 1 /* Maximum value of Y for
1039 + * AR2315_GPIO_INT_* macros */
1040 +#define AR2315_GPIO_INT_LVL_OFF 0 /* Triggerring off */
1041 +#define AR2315_GPIO_INT_LVL_LOW 1 /* Low Level Triggered */
1042 +#define AR2315_GPIO_INT_LVL_HIGH 2 /* High Level Triggered */
1043 +#define AR2315_GPIO_INT_LVL_EDGE 3 /* Edge Triggered */
1044 +
1045 +#define AR2315_RESET_GPIO 5
1046 +#define AR2315_NUM_GPIO 22
1047 +
1048 +/*
1049 + * PCI Clock Control
1050 + */
1051 +#define AR2315_PCICLK (AR2315_DSLBASE + 0x00a4)
1052 +
1053 +#define AR2315_PCICLK_INPUT_M 0x3
1054 +#define AR2315_PCICLK_INPUT_S 0
1055 +
1056 +#define AR2315_PCICLK_PLLC_CLKM 0
1057 +#define AR2315_PCICLK_PLLC_CLKM1 1
1058 +#define AR2315_PCICLK_PLLC_CLKC 2
1059 +#define AR2315_PCICLK_REF_CLK 3
1060 +
1061 +#define AR2315_PCICLK_DIV_M 0xc
1062 +#define AR2315_PCICLK_DIV_S 2
1063 +
1064 +#define AR2315_PCICLK_IN_FREQ 0
1065 +#define AR2315_PCICLK_IN_FREQ_DIV_6 1
1066 +#define AR2315_PCICLK_IN_FREQ_DIV_8 2
1067 +#define AR2315_PCICLK_IN_FREQ_DIV_10 3
1068 +
1069 +/*
1070 + * Observation Control Register
1071 + */
1072 +#define AR2315_OCR (AR2315_DSLBASE + 0x00b0)
1073 +#define OCR_GPIO0_IRIN 0x0040
1074 +#define OCR_GPIO1_IROUT 0x0080
1075 +#define OCR_GPIO3_RXCLR 0x0200
1076 +
1077 +/*
1078 + * General Clock Control
1079 + */
1080 +
1081 +#define AR2315_MISCCLK (AR2315_DSLBASE + 0x00b4)
1082 +#define MISCCLK_PLLBYPASS_EN 0x00000001
1083 +#define MISCCLK_PROCREFCLK 0x00000002
1084 +
1085 +/*
1086 + * SDRAM Controller
1087 + * - No read or write buffers are included.
1088 + */
1089 +#define AR2315_MEM_CFG (AR2315_SDRAMCTL + 0x00)
1090 +#define AR2315_MEM_CTRL (AR2315_SDRAMCTL + 0x0c)
1091 +#define AR2315_MEM_REF (AR2315_SDRAMCTL + 0x10)
1092 +
1093 +#define SDRAM_DATA_WIDTH_M 0x00006000
1094 +#define SDRAM_DATA_WIDTH_S 13
1095 +
1096 +#define SDRAM_COL_WIDTH_M 0x00001E00
1097 +#define SDRAM_COL_WIDTH_S 9
1098 +
1099 +#define SDRAM_ROW_WIDTH_M 0x000001E0
1100 +#define SDRAM_ROW_WIDTH_S 5
1101 +
1102 +#define SDRAM_BANKADDR_BITS_M 0x00000018
1103 +#define SDRAM_BANKADDR_BITS_S 3
1104 +
1105 +/*
1106 + * PCI Bus Interface Registers
1107 + */
1108 +#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008)
1109 +#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1110 +
1111 +#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c)
1112 +#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
1113 +#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* mem or config cycles */
1114 +#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
1115 +#define AR2315_PCIMISC_RST_MODE 0x00000030
1116 +#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
1117 +#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
1118 +#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
1119 +#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
1120 +#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
1121 +#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
1122 +#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
1123 +#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache
1124 + * disable */
1125 +
1126 +#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010)
1127 +
1128 +#define AR2315_PCI_UNCACHE_CFG (AR2315_PCI + 0x0014)
1129 +
1130 +#define AR2315_PCI_IN_EN (AR2315_PCI + 0x0100)
1131 +#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
1132 +#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
1133 +#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
1134 +#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
1135 +
1136 +#define AR2315_PCI_IN_DIS (AR2315_PCI + 0x0104)
1137 +#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
1138 +#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
1139 +#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
1140 +#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
1141 +
1142 +#define AR2315_PCI_IN_PTR (AR2315_PCI + 0x0200)
1143 +
1144 +#define AR2315_PCI_OUT_EN (AR2315_PCI + 0x0400)
1145 +#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
1146 +
1147 +#define AR2315_PCI_OUT_DIS (AR2315_PCI + 0x0404)
1148 +#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
1149 +
1150 +#define AR2315_PCI_OUT_PTR (AR2315_PCI + 0x0408)
1151 +
1152 +#define AR2315_PCI_ISR (AR2315_PCI + 0x0500) /* write one to clr */
1153 +#define AR2315_PCI_INT_TX 0x00000001 /* Desc In Completed */
1154 +#define AR2315_PCI_INT_TXOK 0x00000002 /* Desc In OK */
1155 +#define AR2315_PCI_INT_TXERR 0x00000004 /* Desc In ERR */
1156 +#define AR2315_PCI_INT_TXEOL 0x00000008 /* Desc In End-of-List */
1157 +#define AR2315_PCI_INT_RX 0x00000010 /* Desc Out Completed */
1158 +#define AR2315_PCI_INT_RXOK 0x00000020 /* Desc Out OK */
1159 +#define AR2315_PCI_INT_RXERR 0x00000040 /* Desc Out ERR */
1160 +#define AR2315_PCI_INT_RXEOL 0x00000080 /* Desc Out EOL */
1161 +#define AR2315_PCI_INT_TXOOD 0x00000200 /* Desc In Out-of-Desc */
1162 +#define AR2315_PCI_INT_DESCMASK 0x0000FFFF /* Desc Mask */
1163 +#define AR2315_PCI_INT_EXT 0x02000000 /* Extern PCI INTA */
1164 +#define AR2315_PCI_INT_ABORT 0x04000000 /* PCI bus abort event */
1165 +
1166 +#define AR2315_PCI_IMR (AR2315_PCI + 0x0504) /* mask _PCI_ISR bits */
1167 +
1168 +#define AR2315_PCI_IER (AR2315_PCI + 0x0508) /* global PCI int en */
1169 +#define AR2315_PCI_IER_DISABLE 0x00 /* disable pci interrupts */
1170 +#define AR2315_PCI_IER_ENABLE 0x01 /* enable pci interrupts */
1171 +
1172 +#define AR2315_PCI_HOST_IN_EN (AR2315_PCI + 0x0800)
1173 +#define AR2315_PCI_HOST_IN_DIS (AR2315_PCI + 0x0804)
1174 +#define AR2315_PCI_HOST_IN_PTR (AR2315_PCI + 0x0810)
1175 +#define AR2315_PCI_HOST_OUT_EN (AR2315_PCI + 0x0900)
1176 +#define AR2315_PCI_HOST_OUT_DIS (AR2315_PCI + 0x0904)
1177 +#define AR2315_PCI_HOST_OUT_PTR (AR2315_PCI + 0x0908)
1178 +
1179 +/*
1180 + * Local Bus Interface Registers
1181 + */
1182 +#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000)
1183 +#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
1184 +#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
1185 +#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
1186 +#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
1187 +#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
1188 +#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
1189 +#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
1190 +#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
1191 +#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
1192 +#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
1193 +#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
1194 +#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
1195 +#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
1196 +#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
1197 +#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
1198 +#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
1199 +#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
1200 +#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
1201 +#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
1202 +#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
1203 +#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
1204 +#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */
1205 +#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
1206 +#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
1207 +#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
1208 +
1209 +#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004)
1210 +#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */
1211 +
1212 +#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008)
1213 +#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1214 +
1215 +#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C)
1216 +#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
1217 +#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
1218 +#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
1219 +#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
1220 +#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
1221 +#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80
1222 +#define AR2315_LBM_TIMEOUT_SHFT 7
1223 +#define AR2315_LBM_PORTMUX 0x07000000
1224 +
1225 +#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010)
1226 +
1227 +#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100)
1228 +#define AR2315_LB_TXEN_0 0x01
1229 +#define AR2315_LB_TXEN_1 0x02
1230 +#define AR2315_LB_TXEN_2 0x04
1231 +#define AR2315_LB_TXEN_3 0x08
1232 +
1233 +#define AR2315_LB_TX_CHAIN_DIS (AR2315_LOCAL + 0x0104)
1234 +#define AR2315_LB_TX_DESC_PTR (AR2315_LOCAL + 0x0200)
1235 +
1236 +#define AR2315_LB_RX_CHAIN_EN (AR2315_LOCAL + 0x0400)
1237 +#define AR2315_LB_RXEN 0x01
1238 +
1239 +#define AR2315_LB_RX_CHAIN_DIS (AR2315_LOCAL + 0x0404)
1240 +#define AR2315_LB_RX_DESC_PTR (AR2315_LOCAL + 0x0408)
1241 +
1242 +#define AR2315_LB_INT_STATUS (AR2315_LOCAL + 0x0500)
1243 +#define AR2315_INT_TX_DESC 0x0001
1244 +#define AR2315_INT_TX_OK 0x0002
1245 +#define AR2315_INT_TX_ERR 0x0004
1246 +#define AR2315_INT_TX_EOF 0x0008
1247 +#define AR2315_INT_RX_DESC 0x0010
1248 +#define AR2315_INT_RX_OK 0x0020
1249 +#define AR2315_INT_RX_ERR 0x0040
1250 +#define AR2315_INT_RX_EOF 0x0080
1251 +#define AR2315_INT_TX_TRUNC 0x0100
1252 +#define AR2315_INT_TX_STARVE 0x0200
1253 +#define AR2315_INT_LB_TIMEOUT 0x0400
1254 +#define AR2315_INT_LB_ERR 0x0800
1255 +#define AR2315_INT_MBOX_WR 0x1000
1256 +#define AR2315_INT_MBOX_RD 0x2000
1257 +
1258 +/* Bit definitions for INT MASK are the same as INT_STATUS */
1259 +#define AR2315_LB_INT_MASK (AR2315_LOCAL + 0x0504)
1260 +
1261 +#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508)
1262 +#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600)
1263 +
1264 +/*
1265 + * IR Interface Registers
1266 + */
1267 +#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000)
1268 +
1269 +#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */
1270 +
1271 +#define AR2315_IR_CONTROL (AR2315_IR + 0x0800)
1272 +#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */
1273 +#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */
1274 +#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor */
1275 +#define AR2315_IRCTL_SAMPLECLK_SHFT 1
1276 +#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk div */
1277 +#define AR2315_IRCTL_OUTPUTCLK_SHFT 14
1278 +
1279 +#define AR2315_IR_STATUS (AR2315_IR + 0x0804)
1280 +#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */
1281 +#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */
1282 +
1283 +#define AR2315_IR_CONFIG (AR2315_IR + 0x0808)
1284 +#define AR2315_IRCFG_INVIN 0x00000001 /* invert in polarity */
1285 +#define AR2315_IRCFG_INVOUT 0x00000002 /* invert out polarity */
1286 +#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */
1287 +#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0
1288 +#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100
1289 +#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00
1290 +#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000
1291 +#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000
1292 +#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000
1293 +
1294 +#define HOST_PCI_DEV_ID 3
1295 +#define HOST_PCI_MBAR0 0x10000000
1296 +#define HOST_PCI_MBAR1 0x20000000
1297 +#define HOST_PCI_MBAR2 0x30000000
1298 +
1299 +#define HOST_PCI_SDRAM_BASEADDR HOST_PCI_MBAR1
1300 +#define PCI_DEVICE_MEM_SPACE 0x800000
1301 +
1302 +#endif /* __ASM_MACH_AR231X_AR2315_REGS_H */
1303 --- /dev/null
1304 +++ b/arch/mips/include/asm/mach-ar231x/ar5312_regs.h
1305 @@ -0,0 +1,249 @@
1306 +/*
1307 + * This file is subject to the terms and conditions of the GNU General Public
1308 + * License. See the file "COPYING" in the main directory of this archive
1309 + * for more details.
1310 + *
1311 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1312 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1313 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1314 + */
1315 +
1316 +#ifndef __ASM_MACH_AR231X_AR5312_REGS_H
1317 +#define __ASM_MACH_AR231X_AR5312_REGS_H
1318 +
1319 +#include <asm/addrspace.h>
1320 +
1321 +/*
1322 + * IRQs
1323 + */
1324 +#define AR5312_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
1325 +#define AR5312_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
1326 +#define AR5312_IRQ_ENET1_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
1327 +#define AR5312_IRQ_WLAN1_INTRS (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
1328 +#define AR5312_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
1329 +
1330 +/*
1331 + * Miscellaneous interrupts, which share IP6.
1332 + */
1333 +#define AR5312_MISC_IRQ_NONE (AR231X_MISC_IRQ_BASE+0)
1334 +#define AR5312_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+1)
1335 +#define AR5312_MISC_IRQ_AHB_PROC (AR231X_MISC_IRQ_BASE+2)
1336 +#define AR5312_MISC_IRQ_AHB_DMA (AR231X_MISC_IRQ_BASE+3)
1337 +#define AR5312_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+4)
1338 +#define AR5312_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+5)
1339 +#define AR5312_MISC_IRQ_UART0_DMA (AR231X_MISC_IRQ_BASE+6)
1340 +#define AR5312_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+7)
1341 +#define AR5312_MISC_IRQ_LOCAL (AR231X_MISC_IRQ_BASE+8)
1342 +#define AR5312_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+9)
1343 +#define AR5312_MISC_IRQ_COUNT 10
1344 +
1345 +/*
1346 + * Address Map
1347 + */
1348 +#define AR5312_WLAN0 0x18000000
1349 +#define AR5312_WLAN1 0x18500000
1350 +#define AR5312_ENET0 0x18100000
1351 +#define AR5312_ENET1 0x18200000
1352 +#define AR5312_SDRAMCTL 0x18300000
1353 +#define AR5312_FLASHCTL 0x18400000
1354 +#define AR5312_APBBASE 0x1c000000
1355 +#define AR5312_UART0 0x1c000000 /* UART MMR */
1356 +#define AR5312_FLASH 0x1e000000
1357 +
1358 +/*
1359 + * AR5312_NUM_ENET_MAC defines the number of ethernet MACs that
1360 + * should be considered available. The AR5312 supports 2 enet MACS,
1361 + * even though many reference boards only actually use 1 of them
1362 + * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch.
1363 + * The AR2312 supports 1 enet MAC.
1364 + */
1365 +#define AR5312_NUM_ENET_MAC 2
1366 +
1367 +/*
1368 + * Need these defines to determine true number of ethernet MACs
1369 + */
1370 +#define AR5312_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
1371 +#define AR5312_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
1372 +#define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
1373 +
1374 +/* MII registers offset inside Ethernet MMR region */
1375 +#define AR5312_ENET0_MII (AR5312_ENET0 + 0x14)
1376 +#define AR5312_ENET1_MII (AR5312_ENET1 + 0x14)
1377 +
1378 +/*
1379 + * AR5312_NUM_WMAC defines the number of Wireless MACs that\
1380 + * should be considered available.
1381 + */
1382 +#define AR5312_NUM_WMAC 2
1383 +
1384 +/* Reset/Timer Block Address Map */
1385 +#define AR5312_RESETTMR (AR5312_APBBASE + 0x3000)
1386 +#define AR5312_TIMER (AR5312_RESETTMR + 0x0000) /* countdown timer */
1387 +#define AR5312_WD_CTRL (AR5312_RESETTMR + 0x0008) /* watchdog cntrl */
1388 +#define AR5312_WD_TIMER (AR5312_RESETTMR + 0x000c) /* watchdog timer */
1389 +#define AR5312_ISR (AR5312_RESETTMR + 0x0010) /* Intr Status Reg */
1390 +#define AR5312_IMR (AR5312_RESETTMR + 0x0014) /* Intr Mask Reg */
1391 +#define AR5312_RESET (AR5312_RESETTMR + 0x0020)
1392 +#define AR5312_CLOCKCTL1 (AR5312_RESETTMR + 0x0064)
1393 +#define AR5312_SCRATCH (AR5312_RESETTMR + 0x006c)
1394 +#define AR5312_PROCADDR (AR5312_RESETTMR + 0x0070)
1395 +#define AR5312_PROC1 (AR5312_RESETTMR + 0x0074)
1396 +#define AR5312_DMAADDR (AR5312_RESETTMR + 0x0078)
1397 +#define AR5312_DMA1 (AR5312_RESETTMR + 0x007c)
1398 +#define AR5312_ENABLE (AR5312_RESETTMR + 0x0080) /* interface enb */
1399 +#define AR5312_REV (AR5312_RESETTMR + 0x0090) /* revision */
1400 +
1401 +/* AR5312_WD_CTRL register bit field definitions */
1402 +#define AR5312_WD_CTRL_IGNORE_EXPIRATION 0x0000
1403 +#define AR5312_WD_CTRL_NMI 0x0001
1404 +#define AR5312_WD_CTRL_RESET 0x0002
1405 +
1406 +/* AR5312_ISR register bit field definitions */
1407 +#define AR5312_ISR_NONE 0x0000
1408 +#define AR5312_ISR_TIMER 0x0001
1409 +#define AR5312_ISR_AHBPROC 0x0002
1410 +#define AR5312_ISR_AHBDMA 0x0004
1411 +#define AR5312_ISR_GPIO 0x0008
1412 +#define AR5312_ISR_UART0 0x0010
1413 +#define AR5312_ISR_UART0DMA 0x0020
1414 +#define AR5312_ISR_WD 0x0040
1415 +#define AR5312_ISR_LOCAL 0x0080
1416 +
1417 +/* AR5312_RESET register bit field definitions */
1418 +#define AR5312_RESET_SYSTEM 0x00000001 /* cold reset full system */
1419 +#define AR5312_RESET_PROC 0x00000002 /* cold reset MIPS core */
1420 +#define AR5312_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
1421 +#define AR5312_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
1422 +#define AR5312_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
1423 +#define AR5312_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
1424 +#define AR5312_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
1425 +#define AR5312_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */
1426 +#define AR5312_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
1427 +#define AR5312_RESET_APB 0x00000400 /* cold reset APB (ar5312) */
1428 +#define AR5312_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
1429 +#define AR5312_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
1430 +#define AR5312_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */
1431 +#define AR5312_RESET_NMI 0x00010000 /* send an NMI to the processor */
1432 +#define AR5312_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */
1433 +#define AR5312_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */
1434 +#define AR5312_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
1435 +#define AR5312_RESET_WDOG 0x00100000 /* last reset was a watchdog */
1436 +
1437 +#define AR5312_RESET_WMAC0_BITS \
1438 + (AR5312_RESET_WLAN0 |\
1439 + AR5312_RESET_WARM_WLAN0_MAC |\
1440 + AR5312_RESET_WARM_WLAN0_BB)
1441 +
1442 +#define AR5312_RESET_WMAC1_BITS \
1443 + (AR5312_RESET_WLAN1 |\
1444 + AR5312_RESET_WARM_WLAN1_MAC |\
1445 + AR5312_RESET_WARM_WLAN1_BB)
1446 +
1447 +/* AR5312_CLOCKCTL1 register bit field definitions */
1448 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1449 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1450 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1451 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1452 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1453 +
1454 +/* Valid for AR5312 and AR2312 */
1455 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1456 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1457 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1458 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1459 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1460 +
1461 +/* Valid for AR2313 */
1462 +#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
1463 +#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
1464 +#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
1465 +#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
1466 +#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
1467 +
1468 +/* AR5312_ENABLE register bit field definitions */
1469 +#define AR5312_ENABLE_WLAN0 0x0001
1470 +#define AR5312_ENABLE_ENET0 0x0002
1471 +#define AR5312_ENABLE_ENET1 0x0004
1472 +#define AR5312_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */
1473 +#define AR5312_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */
1474 +#define AR5312_ENABLE_WLAN1 \
1475 + (AR5312_ENABLE_UART_AND_WLAN1_PIO |\
1476 + AR5312_ENABLE_WLAN1_DMA)
1477 +
1478 +/* AR5312_REV register bit field definitions */
1479 +#define AR5312_REV_WMAC_MAJ 0xf000
1480 +#define AR5312_REV_WMAC_MAJ_S 12
1481 +#define AR5312_REV_WMAC_MIN 0x0f00
1482 +#define AR5312_REV_WMAC_MIN_S 8
1483 +#define AR5312_REV_MAJ 0x00f0
1484 +#define AR5312_REV_MAJ_S 4
1485 +#define AR5312_REV_MIN 0x000f
1486 +#define AR5312_REV_MIN_S 0
1487 +#define AR5312_REV_CHIP (AR5312_REV_MAJ|AR5312_REV_MIN)
1488 +
1489 +/* Major revision numbers, bits 7..4 of Revision ID register */
1490 +#define AR5312_REV_MAJ_AR5312 0x4
1491 +#define AR5312_REV_MAJ_AR2313 0x5
1492 +
1493 +/* Minor revision numbers, bits 3..0 of Revision ID register */
1494 +#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
1495 +#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
1496 +
1497 +/* AR5312_FLASHCTL register bit field definitions */
1498 +#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */
1499 +#define FLASHCTL_IDCY_S 0
1500 +#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
1501 +#define FLASHCTL_WST1_S 5
1502 +#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
1503 +#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
1504 +#define FLASHCTL_WST2_S 11
1505 +#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */
1506 +#define FLASHCTL_AC_S 16
1507 +#define FLASHCTL_AC_128K 0x00000000
1508 +#define FLASHCTL_AC_256K 0x00010000
1509 +#define FLASHCTL_AC_512K 0x00020000
1510 +#define FLASHCTL_AC_1M 0x00030000
1511 +#define FLASHCTL_AC_2M 0x00040000
1512 +#define FLASHCTL_AC_4M 0x00050000
1513 +#define FLASHCTL_AC_8M 0x00060000
1514 +#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
1515 +#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
1516 +#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */
1517 +#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */
1518 +#define FLASHCTL_WP 0x04000000 /* Write protect */
1519 +#define FLASHCTL_BM 0x08000000 /* Burst mode */
1520 +#define FLASHCTL_MW 0x30000000 /* Memory width */
1521 +#define FLASHCTL_MW8 0x00000000 /* Memory width x8 */
1522 +#define FLASHCTL_MW16 0x10000000 /* Memory width x16 */
1523 +#define FLASHCTL_MW32 0x20000000 /* Memory width x32 (not supported) */
1524 +#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */
1525 +#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */
1526 +#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */
1527 +
1528 +/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
1529 +#define AR5312_FLASHCTL0 (AR5312_FLASHCTL + 0x00)
1530 +#define AR5312_FLASHCTL1 (AR5312_FLASHCTL + 0x04)
1531 +#define AR5312_FLASHCTL2 (AR5312_FLASHCTL + 0x08)
1532 +
1533 +/* ARM SDRAM Controller -- just enough to determine memory size */
1534 +#define AR5312_MEM_CFG1 (AR5312_SDRAMCTL + 0x04)
1535 +#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */
1536 +#define MEM_CFG1_AC0_S 8
1537 +#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */
1538 +#define MEM_CFG1_AC1_S 12
1539 +
1540 +/* GPIO Address Map */
1541 +#define AR5312_GPIO (AR5312_APBBASE + 0x2000)
1542 +#define AR5312_GPIO_DO (AR5312_GPIO + 0x00) /* output register */
1543 +#define AR5312_GPIO_DI (AR5312_GPIO + 0x04) /* intput register */
1544 +#define AR5312_GPIO_CR (AR5312_GPIO + 0x08) /* control register */
1545 +
1546 +/* GPIO Control Register bit field definitions */
1547 +#define AR5312_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
1548 +#define AR5312_GPIO_CR_O(x) (0 << (x)) /* mask for output */
1549 +#define AR5312_GPIO_CR_I(x) (1 << (x)) /* mask for input */
1550 +#define AR5312_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt*/
1551 +#define AR5312_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */
1552 +#define AR5312_NUM_GPIO 8
1553 +
1554 +#endif /* __ASM_MACH_AR231X_AR5312_REGS_H */
1555 --- /dev/null
1556 +++ b/arch/mips/ar231x/ar5312.c
1557 @@ -0,0 +1,534 @@
1558 +/*
1559 + * This file is subject to the terms and conditions of the GNU General Public
1560 + * License. See the file "COPYING" in the main directory of this archive
1561 + * for more details.
1562 + *
1563 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1564 + * Copyright (C) 2006 FON Technology, SL.
1565 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1566 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1567 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1568 + */
1569 +
1570 +/*
1571 + * Platform devices for Atheros SoCs
1572 + */
1573 +
1574 +#include <generated/autoconf.h>
1575 +#include <linux/init.h>
1576 +#include <linux/module.h>
1577 +#include <linux/types.h>
1578 +#include <linux/string.h>
1579 +#include <linux/mtd/physmap.h>
1580 +#include <linux/platform_device.h>
1581 +#include <linux/kernel.h>
1582 +#include <linux/reboot.h>
1583 +#include <linux/leds.h>
1584 +#include <linux/gpio.h>
1585 +#include <asm/bootinfo.h>
1586 +#include <asm/reboot.h>
1587 +#include <asm/time.h>
1588 +#include <linux/irq.h>
1589 +#include <linux/io.h>
1590 +
1591 +#include <ar231x_platform.h>
1592 +#include <ar5312_regs.h>
1593 +#include <ar231x.h>
1594 +#include "devices.h"
1595 +#include "ar5312.h"
1596 +
1597 +static void ar5312_misc_irq_handler(unsigned irq, struct irq_desc *desc)
1598 +{
1599 + unsigned int ar231x_misc_intrs = ar231x_read_reg(AR5312_ISR) &
1600 + ar231x_read_reg(AR5312_IMR);
1601 +
1602 + if (ar231x_misc_intrs & AR5312_ISR_TIMER) {
1603 + do_IRQ(AR5312_MISC_IRQ_TIMER);
1604 + (void)ar231x_read_reg(AR5312_TIMER);
1605 + } else if (ar231x_misc_intrs & AR5312_ISR_AHBPROC)
1606 + do_IRQ(AR5312_MISC_IRQ_AHB_PROC);
1607 + else if ((ar231x_misc_intrs & AR5312_ISR_UART0))
1608 + do_IRQ(AR5312_MISC_IRQ_UART0);
1609 + else if (ar231x_misc_intrs & AR5312_ISR_WD)
1610 + do_IRQ(AR5312_MISC_IRQ_WATCHDOG);
1611 + else
1612 + do_IRQ(AR5312_MISC_IRQ_NONE);
1613 +}
1614 +
1615 +static asmlinkage void
1616 +ar5312_irq_dispatch(void)
1617 +{
1618 + int pending = read_c0_status() & read_c0_cause();
1619 +
1620 + if (pending & CAUSEF_IP2)
1621 + do_IRQ(AR5312_IRQ_WLAN0_INTRS);
1622 + else if (pending & CAUSEF_IP3)
1623 + do_IRQ(AR5312_IRQ_ENET0_INTRS);
1624 + else if (pending & CAUSEF_IP4)
1625 + do_IRQ(AR5312_IRQ_ENET1_INTRS);
1626 + else if (pending & CAUSEF_IP5)
1627 + do_IRQ(AR5312_IRQ_WLAN1_INTRS);
1628 + else if (pending & CAUSEF_IP6)
1629 + do_IRQ(AR5312_IRQ_MISC_INTRS);
1630 + else if (pending & CAUSEF_IP7)
1631 + do_IRQ(AR231X_IRQ_CPU_CLOCK);
1632 +}
1633 +
1634 +/* Enable the specified AR5312_MISC_IRQ interrupt */
1635 +static void
1636 +ar5312_misc_irq_unmask(struct irq_data *d)
1637 +{
1638 + unsigned int imr;
1639 +
1640 + imr = ar231x_read_reg(AR5312_IMR);
1641 + imr |= (1 << (d->irq - AR231X_MISC_IRQ_BASE - 1));
1642 + ar231x_write_reg(AR5312_IMR, imr);
1643 +}
1644 +
1645 +/* Disable the specified AR5312_MISC_IRQ interrupt */
1646 +static void
1647 +ar5312_misc_irq_mask(struct irq_data *d)
1648 +{
1649 + unsigned int imr;
1650 +
1651 + imr = ar231x_read_reg(AR5312_IMR);
1652 + imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE - 1));
1653 + ar231x_write_reg(AR5312_IMR, imr);
1654 + ar231x_read_reg(AR5312_IMR); /* flush write buffer */
1655 +}
1656 +
1657 +static struct irq_chip ar5312_misc_irq_chip = {
1658 + .name = "AR5312-MISC",
1659 + .irq_unmask = ar5312_misc_irq_unmask,
1660 + .irq_mask = ar5312_misc_irq_mask,
1661 +};
1662 +
1663 +static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id)
1664 +{
1665 + u32 proc1 = ar231x_read_reg(AR5312_PROC1);
1666 + u32 proc_addr = ar231x_read_reg(AR5312_PROCADDR); /* clears error */
1667 + u32 dma1 = ar231x_read_reg(AR5312_DMA1);
1668 + u32 dma_addr = ar231x_read_reg(AR5312_DMAADDR); /* clears error */
1669 +
1670 + pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
1671 + proc_addr, proc1, dma_addr, dma1);
1672 +
1673 + machine_restart("AHB error"); /* Catastrophic failure */
1674 + return IRQ_HANDLED;
1675 +}
1676 +
1677 +static struct irqaction ar5312_ahb_proc_interrupt = {
1678 + .handler = ar5312_ahb_proc_handler,
1679 + .name = "ar5312_ahb_proc_interrupt",
1680 +};
1681 +
1682 +void __init ar5312_irq_init(void)
1683 +{
1684 + int i;
1685 +
1686 + if (!is_5312())
1687 + return;
1688 +
1689 + ar231x_irq_dispatch = ar5312_irq_dispatch;
1690 + for (i = 0; i < AR5312_MISC_IRQ_COUNT; i++) {
1691 + int irq = AR231X_MISC_IRQ_BASE + i;
1692 +
1693 + irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip,
1694 + handle_level_irq);
1695 + }
1696 + setup_irq(AR5312_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt);
1697 + irq_set_chained_handler(AR5312_IRQ_MISC_INTRS, ar5312_misc_irq_handler);
1698 +}
1699 +
1700 +/*
1701 + * gpiolib implementations
1702 + */
1703 +static int
1704 +ar5312_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
1705 +{
1706 + return (ar231x_read_reg(AR5312_GPIO_DI) >> gpio) & 1;
1707 +}
1708 +
1709 +static void
1710 +ar5312_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
1711 +{
1712 + u32 reg = ar231x_read_reg(AR5312_GPIO_DO);
1713 +
1714 + reg = value ? reg | (1 << gpio) : reg & ~(1 << gpio);
1715 + ar231x_write_reg(AR5312_GPIO_DO, reg);
1716 +}
1717 +
1718 +static int
1719 +ar5312_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
1720 +{
1721 + ar231x_mask_reg(AR5312_GPIO_CR, 0, 1 << gpio);
1722 + return 0;
1723 +}
1724 +
1725 +static int
1726 +ar5312_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
1727 +{
1728 + ar231x_mask_reg(AR5312_GPIO_CR, 1 << gpio, 0);
1729 + ar5312_gpio_set_value(chip, gpio, value);
1730 + return 0;
1731 +}
1732 +
1733 +static struct gpio_chip ar5312_gpio_chip = {
1734 + .label = "ar5312-gpio",
1735 + .direction_input = ar5312_gpio_direction_input,
1736 + .direction_output = ar5312_gpio_direction_output,
1737 + .set = ar5312_gpio_set_value,
1738 + .get = ar5312_gpio_get_value,
1739 + .base = 0,
1740 + .ngpio = AR5312_NUM_GPIO, /* 8 */
1741 +};
1742 +
1743 +/* end of gpiolib */
1744 +
1745 +static void ar5312_device_reset_set(u32 mask)
1746 +{
1747 + u32 val;
1748 +
1749 + val = ar231x_read_reg(AR5312_RESET);
1750 + ar231x_write_reg(AR5312_RESET, val | mask);
1751 +}
1752 +
1753 +static void ar5312_device_reset_clear(u32 mask)
1754 +{
1755 + u32 val;
1756 +
1757 + val = ar231x_read_reg(AR5312_RESET);
1758 + ar231x_write_reg(AR5312_RESET, val & ~mask);
1759 +}
1760 +
1761 +static struct physmap_flash_data ar5312_flash_data = {
1762 + .width = 2,
1763 +};
1764 +
1765 +static struct resource ar5312_flash_resource = {
1766 + .start = AR5312_FLASH,
1767 + .end = AR5312_FLASH + 0x800000 - 1,
1768 + .flags = IORESOURCE_MEM,
1769 +};
1770 +
1771 +static struct ar231x_eth ar5312_eth0_data = {
1772 + .reset_set = ar5312_device_reset_set,
1773 + .reset_clear = ar5312_device_reset_clear,
1774 + .reset_mac = AR5312_RESET_ENET0,
1775 + .reset_phy = AR5312_RESET_EPHY0,
1776 + .config = &ar231x_board,
1777 +};
1778 +
1779 +static struct ar231x_eth ar5312_eth1_data = {
1780 + .reset_set = ar5312_device_reset_set,
1781 + .reset_clear = ar5312_device_reset_clear,
1782 + .reset_mac = AR5312_RESET_ENET1,
1783 + .reset_phy = AR5312_RESET_EPHY1,
1784 + .config = &ar231x_board,
1785 +};
1786 +
1787 +static struct platform_device ar5312_physmap_flash = {
1788 + .name = "physmap-flash",
1789 + .id = 0,
1790 + .dev.platform_data = &ar5312_flash_data,
1791 + .resource = &ar5312_flash_resource,
1792 + .num_resources = 1,
1793 +};
1794 +
1795 +#ifdef CONFIG_LEDS_GPIO
1796 +static struct gpio_led ar5312_leds[] = {
1797 + { .name = "wlan", .gpio = 0, .active_low = 1, },
1798 +};
1799 +
1800 +static const struct gpio_led_platform_data ar5312_led_data = {
1801 + .num_leds = ARRAY_SIZE(ar5312_leds),
1802 + .leds = (void *)ar5312_leds,
1803 +};
1804 +
1805 +static struct platform_device ar5312_gpio_leds = {
1806 + .name = "leds-gpio",
1807 + .id = -1,
1808 + .dev.platform_data = (void *)&ar5312_led_data,
1809 +};
1810 +#endif
1811 +
1812 +/*
1813 + * NB: This mapping size is larger than the actual flash size,
1814 + * but this shouldn't be a problem here, because the flash
1815 + * will simply be mapped multiple times.
1816 + */
1817 +static char __init *ar5312_flash_limit(void)
1818 +{
1819 + u32 ctl;
1820 + /*
1821 + * Configure flash bank 0.
1822 + * Assume 8M window size. Flash will be aliased if it's smaller
1823 + */
1824 + ctl = FLASHCTL_E |
1825 + FLASHCTL_AC_8M |
1826 + FLASHCTL_RBLE |
1827 + (0x01 << FLASHCTL_IDCY_S) |
1828 + (0x07 << FLASHCTL_WST1_S) |
1829 + (0x07 << FLASHCTL_WST2_S) |
1830 + (ar231x_read_reg(AR5312_FLASHCTL0) & FLASHCTL_MW);
1831 +
1832 + ar231x_write_reg(AR5312_FLASHCTL0, ctl);
1833 +
1834 + /* Disable other flash banks */
1835 + ar231x_write_reg(AR5312_FLASHCTL1,
1836 + ar231x_read_reg(AR5312_FLASHCTL1) &
1837 + ~(FLASHCTL_E | FLASHCTL_AC));
1838 +
1839 + ar231x_write_reg(AR5312_FLASHCTL2,
1840 + ar231x_read_reg(AR5312_FLASHCTL2) &
1841 + ~(FLASHCTL_E | FLASHCTL_AC));
1842 +
1843 + return (char *)KSEG1ADDR(AR5312_FLASH + 0x800000);
1844 +}
1845 +
1846 +int __init ar5312_init_devices(void)
1847 +{
1848 + struct ar231x_boarddata *config;
1849 + u32 fctl = 0;
1850 + u8 *c;
1851 +
1852 + if (!is_5312())
1853 + return 0;
1854 +
1855 + /* Locate board/radio config data */
1856 + ar231x_find_config(ar5312_flash_limit());
1857 + config = ar231x_board.config;
1858 +
1859 + /* AR2313 has CPU minor rev. 10 */
1860 + if ((current_cpu_data.processor_id & 0xff) == 0x0a)
1861 + ar231x_devtype = DEV_TYPE_AR2313;
1862 +
1863 + /* AR2312 shares the same Silicon ID as AR5312 */
1864 + else if (config->flags & BD_ISCASPER)
1865 + ar231x_devtype = DEV_TYPE_AR2312;
1866 +
1867 + /* Everything else is probably AR5312 or compatible */
1868 + else
1869 + ar231x_devtype = DEV_TYPE_AR5312;
1870 +
1871 + /* fixup flash width */
1872 + fctl = ar231x_read_reg(AR5312_FLASHCTL) & FLASHCTL_MW;
1873 + switch (fctl) {
1874 + case FLASHCTL_MW16:
1875 + ar5312_flash_data.width = 2;
1876 + break;
1877 + case FLASHCTL_MW8:
1878 + default:
1879 + ar5312_flash_data.width = 1;
1880 + break;
1881 + }
1882 +
1883 + platform_device_register(&ar5312_physmap_flash);
1884 +
1885 +#ifdef CONFIG_LEDS_GPIO
1886 + ar5312_leds[0].gpio = config->sys_led_gpio;
1887 + platform_device_register(&ar5312_gpio_leds);
1888 +#endif
1889 +
1890 + /* Fix up MAC addresses if necessary */
1891 + if (is_broadcast_ether_addr(config->enet0_mac))
1892 + ether_addr_copy(config->enet0_mac, config->enet1_mac);
1893 +
1894 + /* If ENET0 and ENET1 have the same mac address,
1895 + * increment the one from ENET1 */
1896 + if (ether_addr_equal(config->enet0_mac, config->enet1_mac)) {
1897 + c = config->enet1_mac + 5;
1898 + while ((c >= config->enet1_mac) && !(++(*c)))
1899 + c--;
1900 + }
1901 +
1902 + switch (ar231x_devtype) {
1903 + case DEV_TYPE_AR5312:
1904 + ar5312_eth0_data.macaddr = config->enet0_mac;
1905 + ar231x_add_ethernet(0, AR5312_ENET0, "eth0_mii",
1906 + AR5312_ENET0_MII, AR5312_IRQ_ENET0_INTRS,
1907 + &ar5312_eth0_data);
1908 +
1909 + ar5312_eth1_data.macaddr = config->enet1_mac;
1910 + ar231x_add_ethernet(1, AR5312_ENET1, "eth1_mii",
1911 + AR5312_ENET1_MII, AR5312_IRQ_ENET1_INTRS,
1912 + &ar5312_eth1_data);
1913 +
1914 + if (!ar231x_board.radio)
1915 + return 0;
1916 +
1917 + if (!(config->flags & BD_WLAN0))
1918 + break;
1919 +
1920 + ar231x_add_wmac(0, AR5312_WLAN0, AR5312_IRQ_WLAN0_INTRS);
1921 + break;
1922 + /*
1923 + * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
1924 + * of ENET1. Atheros calls it 'twisted' for a reason :)
1925 + */
1926 + case DEV_TYPE_AR2312:
1927 + case DEV_TYPE_AR2313:
1928 + ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
1929 + ar5312_eth1_data.macaddr = config->enet0_mac;
1930 + ar231x_add_ethernet(1, AR5312_ENET1, "eth0_mii",
1931 + AR5312_ENET0_MII, AR5312_IRQ_ENET1_INTRS,
1932 + &ar5312_eth1_data);
1933 +
1934 + if (!ar231x_board.radio)
1935 + return 0;
1936 + break;
1937 + default:
1938 + break;
1939 + }
1940 +
1941 + if (config->flags & BD_WLAN1)
1942 + ar231x_add_wmac(1, AR5312_WLAN1, AR5312_IRQ_WLAN1_INTRS);
1943 +
1944 + return 0;
1945 +}
1946 +
1947 +static void ar5312_restart(char *command)
1948 +{
1949 + /* reset the system */
1950 + local_irq_disable();
1951 + while (1)
1952 + ar231x_write_reg(AR5312_RESET, AR5312_RESET_SYSTEM);
1953 +}
1954 +
1955 +/*
1956 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
1957 + * to determine the predevisor value.
1958 + */
1959 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
1960 +
1961 +static int __init
1962 +ar5312_cpu_frequency(void)
1963 +{
1964 + unsigned int scratch;
1965 + unsigned int predivide_mask, predivide_shift;
1966 + unsigned int multiplier_mask, multiplier_shift;
1967 + unsigned int clock_ctl1, predivide_select, predivisor, multiplier;
1968 + unsigned int doubler_mask;
1969 + u16 devid;
1970 +
1971 + /* Trust the bootrom's idea of cpu frequency. */
1972 + scratch = ar231x_read_reg(AR5312_SCRATCH);
1973 + if (scratch)
1974 + return scratch;
1975 +
1976 + devid = ar231x_read_reg(AR5312_REV);
1977 + devid &= AR5312_REV_MAJ;
1978 + devid >>= AR5312_REV_MAJ_S;
1979 + if (devid == AR5312_REV_MAJ_AR2313) {
1980 + predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
1981 + predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
1982 + multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
1983 + multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
1984 + doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
1985 + } else { /* AR5312 and AR2312 */
1986 + predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
1987 + predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
1988 + multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
1989 + multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
1990 + doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
1991 + }
1992 +
1993 + /*
1994 + * Clocking is derived from a fixed 40MHz input clock.
1995 + *
1996 + * cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
1997 + * sys_freq = cpu_freq / 4 (used for APB clock, serial,
1998 + * flash, Timer, Watchdog Timer)
1999 + *
2000 + * cnt_freq = cpu_freq / 2 (use for CPU count/compare)
2001 + *
2002 + * So, for example, with a PLL multiplier of 5, we have
2003 + *
2004 + * cpu_freq = 200MHz
2005 + * sys_freq = 50MHz
2006 + * cnt_freq = 100MHz
2007 + *
2008 + * We compute the CPU frequency, based on PLL settings.
2009 + */
2010 +
2011 + clock_ctl1 = ar231x_read_reg(AR5312_CLOCKCTL1);
2012 + predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
2013 + predivisor = clockctl1_predivide_table[predivide_select];
2014 + multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
2015 +
2016 + if (clock_ctl1 & doubler_mask)
2017 + multiplier = multiplier << 1;
2018 +
2019 + return (40000000 / predivisor) * multiplier;
2020 +}
2021 +
2022 +static inline int
2023 +ar5312_sys_frequency(void)
2024 +{
2025 + return ar5312_cpu_frequency() / 4;
2026 +}
2027 +
2028 +void __init
2029 +ar5312_time_init(void)
2030 +{
2031 + if (!is_5312())
2032 + return;
2033 +
2034 + mips_hpt_frequency = ar5312_cpu_frequency() / 2;
2035 +}
2036 +
2037 +static int __init
2038 +ar5312_gpio_init(void)
2039 +{
2040 + int ret = gpiochip_add(&ar5312_gpio_chip);
2041 +
2042 + if (ret) {
2043 + pr_err("%s: failed to add gpiochip\n", ar5312_gpio_chip.label);
2044 + return ret;
2045 + }
2046 + pr_info("%s: registered %d GPIOs\n", ar5312_gpio_chip.label,
2047 + ar5312_gpio_chip.ngpio);
2048 + return ret;
2049 +}
2050 +
2051 +void __init
2052 +ar5312_prom_init(void)
2053 +{
2054 + u32 memsize, memcfg, bank0AC, bank1AC;
2055 + u32 devid;
2056 +
2057 + if (!is_5312())
2058 + return;
2059 +
2060 + /* Detect memory size */
2061 + memcfg = ar231x_read_reg(AR5312_MEM_CFG1);
2062 + bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
2063 + bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
2064 + memsize = (bank0AC ? (1 << (bank0AC+1)) : 0) +
2065 + (bank1AC ? (1 << (bank1AC+1)) : 0);
2066 + memsize <<= 20;
2067 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2068 +
2069 + devid = ar231x_read_reg(AR5312_REV);
2070 + devid >>= AR5312_REV_WMAC_MIN_S;
2071 + devid &= AR5312_REV_CHIP;
2072 + ar231x_board.devid = (u16)devid;
2073 + ar5312_gpio_init();
2074 +}
2075 +
2076 +void __init
2077 +ar5312_plat_setup(void)
2078 +{
2079 + if (!is_5312())
2080 + return;
2081 +
2082 + /* Clear any lingering AHB errors */
2083 + ar231x_read_reg(AR5312_PROCADDR);
2084 + ar231x_read_reg(AR5312_DMAADDR);
2085 + ar231x_write_reg(AR5312_WD_CTRL, AR5312_WD_CTRL_IGNORE_EXPIRATION);
2086 +
2087 + _machine_restart = ar5312_restart;
2088 + ar231x_serial_setup(AR5312_UART0, AR5312_MISC_IRQ_UART0,
2089 + ar5312_sys_frequency());
2090 +}
2091 +
2092 --- /dev/null
2093 +++ b/arch/mips/ar231x/ar2315.c
2094 @@ -0,0 +1,556 @@
2095 +/*
2096 + * This file is subject to the terms and conditions of the GNU General Public
2097 + * License. See the file "COPYING" in the main directory of this archive
2098 + * for more details.
2099 + *
2100 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
2101 + * Copyright (C) 2006 FON Technology, SL.
2102 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
2103 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
2104 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
2105 + */
2106 +
2107 +/*
2108 + * Platform devices for Atheros SoCs
2109 + */
2110 +
2111 +#include <generated/autoconf.h>
2112 +#include <linux/init.h>
2113 +#include <linux/module.h>
2114 +#include <linux/types.h>
2115 +#include <linux/string.h>
2116 +#include <linux/platform_device.h>
2117 +#include <linux/kernel.h>
2118 +#include <linux/reboot.h>
2119 +#include <linux/delay.h>
2120 +#include <linux/leds.h>
2121 +#include <linux/gpio.h>
2122 +#include <asm/bootinfo.h>
2123 +#include <asm/reboot.h>
2124 +#include <asm/time.h>
2125 +#include <linux/irq.h>
2126 +#include <linux/io.h>
2127 +
2128 +#include <ar231x_platform.h>
2129 +#include <ar2315_regs.h>
2130 +#include <ar231x.h>
2131 +#include "devices.h"
2132 +#include "ar2315.h"
2133 +
2134 +static u32 gpiointmask, gpiointval;
2135 +
2136 +static void ar2315_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
2137 +{
2138 + u32 pend;
2139 + int bit = -1;
2140 +
2141 + /* only do one gpio interrupt at a time */
2142 + pend = (ar231x_read_reg(AR2315_GPIO_DI) ^ gpiointval) & gpiointmask;
2143 +
2144 + if (pend) {
2145 + bit = fls(pend) - 1;
2146 + pend &= ~(1 << bit);
2147 + gpiointval ^= (1 << bit);
2148 + }
2149 +
2150 + if (!pend)
2151 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO);
2152 +
2153 + /* Enable interrupt with edge detection */
2154 + if ((ar231x_read_reg(AR2315_GPIO_DIR) & AR2315_GPIO_DIR_M(bit)) !=
2155 + AR2315_GPIO_DIR_I(bit))
2156 + return;
2157 +
2158 + if (bit >= 0)
2159 + do_IRQ(AR231X_GPIO_IRQ_BASE + bit);
2160 +}
2161 +
2162 +static void ar2315_misc_irq_handler(unsigned irq, struct irq_desc *desc)
2163 +{
2164 + unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) &
2165 + ar231x_read_reg(AR2315_IMR);
2166 +
2167 + if (misc_intr & AR2315_ISR_SPI)
2168 + do_IRQ(AR2315_MISC_IRQ_SPI);
2169 + else if (misc_intr & AR2315_ISR_TIMER)
2170 + do_IRQ(AR2315_MISC_IRQ_TIMER);
2171 + else if (misc_intr & AR2315_ISR_AHB)
2172 + do_IRQ(AR2315_MISC_IRQ_AHB);
2173 + else if (misc_intr & AR2315_ISR_GPIO)
2174 + do_IRQ(AR2315_MISC_IRQ_GPIO);
2175 + else if (misc_intr & AR2315_ISR_UART0)
2176 + do_IRQ(AR2315_MISC_IRQ_UART0);
2177 + else if (misc_intr & AR2315_ISR_WD) {
2178 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_WD);
2179 + do_IRQ(AR2315_MISC_IRQ_WATCHDOG);
2180 + } else
2181 + do_IRQ(AR2315_MISC_IRQ_NONE);
2182 +}
2183 +
2184 +/*
2185 + * Called when an interrupt is received, this function
2186 + * determines exactly which interrupt it was, and it
2187 + * invokes the appropriate handler.
2188 + *
2189 + * Implicitly, we also define interrupt priority by
2190 + * choosing which to dispatch first.
2191 + */
2192 +static asmlinkage void
2193 +ar2315_irq_dispatch(void)
2194 +{
2195 + int pending = read_c0_status() & read_c0_cause();
2196 +
2197 + if (pending & CAUSEF_IP3)
2198 + do_IRQ(AR2315_IRQ_WLAN0_INTRS);
2199 + else if (pending & CAUSEF_IP4)
2200 + do_IRQ(AR2315_IRQ_ENET0_INTRS);
2201 + else if (pending & CAUSEF_IP2)
2202 + do_IRQ(AR2315_IRQ_MISC_INTRS);
2203 + else if (pending & CAUSEF_IP7)
2204 + do_IRQ(AR231X_IRQ_CPU_CLOCK);
2205 +}
2206 +
2207 +static void ar2315_set_gpiointmask(int gpio, int level)
2208 +{
2209 + u32 reg;
2210 +
2211 + reg = ar231x_read_reg(AR2315_GPIO_INT);
2212 + reg &= ~(AR2315_GPIO_INT_M | AR2315_GPIO_INT_LVL_M);
2213 + reg |= gpio | AR2315_GPIO_INT_LVL(level);
2214 + ar231x_write_reg(AR2315_GPIO_INT, reg);
2215 +}
2216 +
2217 +static void ar2315_gpio_irq_unmask(struct irq_data *d)
2218 +{
2219 + unsigned int gpio = d->irq - AR231X_GPIO_IRQ_BASE;
2220 +
2221 + /* Enable interrupt with edge detection */
2222 + if ((ar231x_read_reg(AR2315_GPIO_DIR) & AR2315_GPIO_DIR_M(gpio)) !=
2223 + AR2315_GPIO_DIR_I(gpio))
2224 + return;
2225 +
2226 + gpiointmask |= (1 << gpio);
2227 + ar2315_set_gpiointmask(gpio, 3);
2228 +}
2229 +
2230 +static void ar2315_gpio_irq_mask(struct irq_data *d)
2231 +{
2232 + unsigned int gpio = d->irq - AR231X_GPIO_IRQ_BASE;
2233 +
2234 + /* Disable interrupt */
2235 + gpiointmask &= ~(1 << gpio);
2236 + ar2315_set_gpiointmask(gpio, 0);
2237 +}
2238 +
2239 +static struct irq_chip ar2315_gpio_irq_chip = {
2240 + .name = "AR2315-GPIO",
2241 + .irq_unmask = ar2315_gpio_irq_unmask,
2242 + .irq_mask = ar2315_gpio_irq_mask,
2243 +};
2244 +
2245 +static void
2246 +ar2315_misc_irq_unmask(struct irq_data *d)
2247 +{
2248 + unsigned int imr;
2249 +
2250 + imr = ar231x_read_reg(AR2315_IMR);
2251 + imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE - 1);
2252 + ar231x_write_reg(AR2315_IMR, imr);
2253 +}
2254 +
2255 +static void
2256 +ar2315_misc_irq_mask(struct irq_data *d)
2257 +{
2258 + unsigned int imr;
2259 +
2260 + imr = ar231x_read_reg(AR2315_IMR);
2261 + imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE - 1));
2262 + ar231x_write_reg(AR2315_IMR, imr);
2263 +}
2264 +
2265 +static struct irq_chip ar2315_misc_irq_chip = {
2266 + .name = "AR2315-MISC",
2267 + .irq_unmask = ar2315_misc_irq_unmask,
2268 + .irq_mask = ar2315_misc_irq_mask,
2269 +};
2270 +
2271 +static irqreturn_t ar2315_ahb_proc_handler(int cpl, void *dev_id)
2272 +{
2273 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2274 + ar231x_read_reg(AR2315_AHB_ERR1);
2275 +
2276 + pr_emerg("AHB fatal error\n");
2277 + machine_restart("AHB error"); /* Catastrophic failure */
2278 +
2279 + return IRQ_HANDLED;
2280 +}
2281 +
2282 +static struct irqaction ar2315_ahb_proc_interrupt = {
2283 + .handler = ar2315_ahb_proc_handler,
2284 + .name = "ar2315_ahb_proc_interrupt",
2285 +};
2286 +
2287 +void
2288 +ar2315_irq_init(void)
2289 +{
2290 + int i;
2291 +
2292 + if (!is_2315())
2293 + return;
2294 +
2295 + ar231x_irq_dispatch = ar2315_irq_dispatch;
2296 + gpiointval = ar231x_read_reg(AR2315_GPIO_DI);
2297 + for (i = 0; i < AR2315_MISC_IRQ_COUNT; i++) {
2298 + int irq = AR231X_MISC_IRQ_BASE + i;
2299 +
2300 + irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip,
2301 + handle_level_irq);
2302 + }
2303 + for (i = 0; i < AR2315_NUM_GPIO; i++) {
2304 + int irq = AR231X_GPIO_IRQ_BASE + i;
2305 +
2306 + irq_set_chip_and_handler(irq, &ar2315_gpio_irq_chip,
2307 + handle_level_irq);
2308 + }
2309 + irq_set_chained_handler(AR2315_MISC_IRQ_GPIO, ar2315_gpio_irq_handler);
2310 + setup_irq(AR2315_MISC_IRQ_AHB, &ar2315_ahb_proc_interrupt);
2311 + irq_set_chained_handler(AR2315_IRQ_MISC_INTRS, ar2315_misc_irq_handler);
2312 +}
2313 +
2314 +/*
2315 + * gpiolib implementation
2316 + */
2317 +static int
2318 +ar2315_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
2319 +{
2320 + return (ar231x_read_reg(AR2315_GPIO_DI) >> gpio) & 1;
2321 +}
2322 +
2323 +static void
2324 +ar2315_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
2325 +{
2326 + u32 reg = ar231x_read_reg(AR2315_GPIO_DO);
2327 +
2328 + reg = value ? reg | (1 << gpio) : reg & ~(1 << gpio);
2329 + ar231x_write_reg(AR2315_GPIO_DO, reg);
2330 +}
2331 +
2332 +static int
2333 +ar2315_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
2334 +{
2335 + ar231x_mask_reg(AR2315_GPIO_DIR, 1 << gpio, 0);
2336 + return 0;
2337 +}
2338 +
2339 +static int
2340 +ar2315_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
2341 +{
2342 + ar231x_mask_reg(AR2315_GPIO_DIR, 0, 1 << gpio);
2343 + ar2315_gpio_set_value(chip, gpio, value);
2344 + return 0;
2345 +}
2346 +
2347 +static struct gpio_chip ar2315_gpio_chip = {
2348 + .label = "ar2315-gpio",
2349 + .direction_input = ar2315_gpio_direction_input,
2350 + .direction_output = ar2315_gpio_direction_output,
2351 + .set = ar2315_gpio_set_value,
2352 + .get = ar2315_gpio_get_value,
2353 + .base = 0,
2354 + .ngpio = AR2315_NUM_GPIO, /* 22 */
2355 +};
2356 +
2357 +/* end of gpiolib */
2358 +
2359 +static void ar2315_device_reset_set(u32 mask)
2360 +{
2361 + u32 val;
2362 +
2363 + val = ar231x_read_reg(AR2315_RESET);
2364 + ar231x_write_reg(AR2315_RESET, val | mask);
2365 +}
2366 +
2367 +static void ar2315_device_reset_clear(u32 mask)
2368 +{
2369 + u32 val;
2370 +
2371 + val = ar231x_read_reg(AR2315_RESET);
2372 + ar231x_write_reg(AR2315_RESET, val & ~mask);
2373 +}
2374 +
2375 +static struct ar231x_eth ar2315_eth_data = {
2376 + .reset_set = ar2315_device_reset_set,
2377 + .reset_clear = ar2315_device_reset_clear,
2378 + .reset_mac = AR2315_RESET_ENET0,
2379 + .reset_phy = AR2315_RESET_EPHY0,
2380 + .config = &ar231x_board,
2381 +};
2382 +
2383 +static struct resource ar2315_spiflash_res[] = {
2384 + {
2385 + .name = "spiflash_read",
2386 + .flags = IORESOURCE_MEM,
2387 + .start = AR2315_SPI_READ,
2388 + .end = AR2315_SPI_READ + 0x1000000 - 1,
2389 + },
2390 + {
2391 + .name = "spiflash_mmr",
2392 + .flags = IORESOURCE_MEM,
2393 + .start = AR2315_SPI_MMR,
2394 + .end = AR2315_SPI_MMR + 12 - 1,
2395 + },
2396 +};
2397 +
2398 +static struct platform_device ar2315_spiflash = {
2399 + .id = 0,
2400 + .name = "ar2315-spiflash",
2401 + .resource = ar2315_spiflash_res,
2402 + .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
2403 +};
2404 +
2405 +static struct resource ar2315_wdt_res[] = {
2406 + {
2407 + .flags = IORESOURCE_MEM,
2408 + .start = AR2315_WD,
2409 + .end = AR2315_WD + 8 - 1,
2410 + },
2411 + {
2412 + .flags = IORESOURCE_IRQ,
2413 + .start = AR2315_MISC_IRQ_WATCHDOG,
2414 + .end = AR2315_MISC_IRQ_WATCHDOG,
2415 + }
2416 +};
2417 +
2418 +static struct platform_device ar2315_wdt = {
2419 + .id = 0,
2420 + .name = "ar2315-wdt",
2421 + .resource = ar2315_wdt_res,
2422 + .num_resources = ARRAY_SIZE(ar2315_wdt_res)
2423 +};
2424 +
2425 +/*
2426 + * NB: We use mapping size that is larger than the actual flash size,
2427 + * but this shouldn't be a problem here, because the flash will simply
2428 + * be mapped multiple times.
2429 + */
2430 +static u8 __init *ar2315_flash_limit(void)
2431 +{
2432 + return (u8 *)KSEG1ADDR(ar2315_spiflash_res[0].end + 1);
2433 +}
2434 +
2435 +#ifdef CONFIG_LEDS_GPIO
2436 +static struct gpio_led ar2315_leds[6];
2437 +static struct gpio_led_platform_data ar2315_led_data = {
2438 + .leds = (void *)ar2315_leds,
2439 +};
2440 +
2441 +static struct platform_device ar2315_gpio_leds = {
2442 + .name = "leds-gpio",
2443 + .id = -1,
2444 + .dev = {
2445 + .platform_data = (void *)&ar2315_led_data,
2446 + }
2447 +};
2448 +
2449 +static void __init
2450 +ar2315_init_gpio_leds(void)
2451 +{
2452 + static char led_names[6][6];
2453 + int i, led = 0;
2454 +
2455 + ar2315_led_data.num_leds = 0;
2456 + for (i = 1; i < 8; i++) {
2457 + if ((i == AR2315_RESET_GPIO) ||
2458 + (i == ar231x_board.config->reset_config_gpio))
2459 + continue;
2460 +
2461 + if (i == ar231x_board.config->sys_led_gpio)
2462 + strcpy(led_names[led], "wlan");
2463 + else
2464 + sprintf(led_names[led], "gpio%d", i);
2465 +
2466 + ar2315_leds[led].name = led_names[led];
2467 + ar2315_leds[led].gpio = i;
2468 + ar2315_leds[led].active_low = 0;
2469 + led++;
2470 + }
2471 + ar2315_led_data.num_leds = led;
2472 + platform_device_register(&ar2315_gpio_leds);
2473 +}
2474 +#else
2475 +static inline void ar2315_init_gpio_leds(void)
2476 +{
2477 +}
2478 +#endif
2479 +
2480 +int __init
2481 +ar2315_init_devices(void)
2482 +{
2483 + if (!is_2315())
2484 + return 0;
2485 +
2486 + /* Find board configuration */
2487 + ar231x_find_config(ar2315_flash_limit());
2488 + ar2315_eth_data.macaddr = ar231x_board.config->enet0_mac;
2489 +
2490 + ar2315_init_gpio_leds();
2491 + platform_device_register(&ar2315_wdt);
2492 + platform_device_register(&ar2315_spiflash);
2493 + ar231x_add_ethernet(0, AR2315_ENET0, "eth0_mii", AR2315_ENET0_MII,
2494 + AR2315_IRQ_ENET0_INTRS, &ar2315_eth_data);
2495 + ar231x_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS);
2496 +
2497 + return 0;
2498 +}
2499 +
2500 +static void
2501 +ar2315_restart(char *command)
2502 +{
2503 + void (*mips_reset_vec)(void) = (void *)0xbfc00000;
2504 +
2505 + local_irq_disable();
2506 +
2507 + /* try reset the system via reset control */
2508 + ar231x_write_reg(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
2509 +
2510 + /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
2511 + * a workaround. Give it some time to attempt a gpio based hardware
2512 + * reset (atheros reference design workaround) */
2513 + gpio_request_one(AR2315_RESET_GPIO, GPIOF_OUT_INIT_LOW, "Reset");
2514 + mdelay(100);
2515 +
2516 + /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
2517 + * workaround. Attempt to jump to the mips reset location -
2518 + * the boot loader itself might be able to recover the system */
2519 + mips_reset_vec();
2520 +}
2521 +
2522 +/*
2523 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
2524 + * to determine the predevisor value.
2525 + */
2526 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
2527 +static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
2528 +
2529 +static unsigned int __init
2530 +ar2315_sys_clk(unsigned int clock_ctl)
2531 +{
2532 + unsigned int pllc_ctrl, cpu_div;
2533 + unsigned int pllc_out, refdiv, fdiv, divby2;
2534 + unsigned int clk_div;
2535 +
2536 + pllc_ctrl = ar231x_read_reg(AR2315_PLLC_CTL);
2537 + refdiv = (pllc_ctrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
2538 + refdiv = clockctl1_predivide_table[refdiv];
2539 + fdiv = (pllc_ctrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
2540 + divby2 = (pllc_ctrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
2541 + divby2 += 1;
2542 + pllc_out = (40000000/refdiv)*(2*divby2)*fdiv;
2543 +
2544 + /* clkm input selected */
2545 + switch (clock_ctl & CPUCLK_CLK_SEL_M) {
2546 + case 0:
2547 + case 1:
2548 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKM_DIV_M) >>
2549 + PLLC_CLKM_DIV_S];
2550 + break;
2551 + case 2:
2552 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKC_DIV_M) >>
2553 + PLLC_CLKC_DIV_S];
2554 + break;
2555 + default:
2556 + pllc_out = 40000000;
2557 + clk_div = 1;
2558 + break;
2559 + }
2560 +
2561 + cpu_div = (clock_ctl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
2562 + cpu_div = cpu_div * 2 ?: 1;
2563 +
2564 + return pllc_out / (clk_div * cpu_div);
2565 +}
2566 +
2567 +static inline unsigned int
2568 +ar2315_cpu_frequency(void)
2569 +{
2570 + return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK));
2571 +}
2572 +
2573 +static inline unsigned int
2574 +ar2315_apb_frequency(void)
2575 +{
2576 + return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK));
2577 +}
2578 +
2579 +void __init
2580 +ar2315_time_init(void)
2581 +{
2582 + if (!is_2315())
2583 + return;
2584 +
2585 + mips_hpt_frequency = ar2315_cpu_frequency() / 2;
2586 +}
2587 +
2588 +static int __init
2589 +ar2315_gpio_init(void)
2590 +{
2591 + int ret = gpiochip_add(&ar2315_gpio_chip);
2592 +
2593 + if (ret) {
2594 + pr_err("%s: failed to add gpiochip\n", ar2315_gpio_chip.label);
2595 + return ret;
2596 + }
2597 + pr_info("%s: registered %d GPIOs\n", ar2315_gpio_chip.label,
2598 + ar2315_gpio_chip.ngpio);
2599 + return ret;
2600 +}
2601 +
2602 +void __init
2603 +ar2315_prom_init(void)
2604 +{
2605 + u32 memsize, memcfg, devid;
2606 +
2607 + if (!is_2315())
2608 + return;
2609 +
2610 + memcfg = ar231x_read_reg(AR2315_MEM_CFG);
2611 + memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
2612 + memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
2613 + memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
2614 + memsize <<= 3;
2615 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2616 +
2617 + /* Detect the hardware based on the device ID */
2618 + devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP;
2619 + switch (devid) {
2620 + case 0x90:
2621 + case 0x91:
2622 + ar231x_devtype = DEV_TYPE_AR2317;
2623 + break;
2624 + default:
2625 + ar231x_devtype = DEV_TYPE_AR2315;
2626 + break;
2627 + }
2628 + ar2315_gpio_init();
2629 + ar231x_board.devid = devid;
2630 +}
2631 +
2632 +void __init
2633 +ar2315_plat_setup(void)
2634 +{
2635 + u32 config;
2636 +
2637 + if (!is_2315())
2638 + return;
2639 +
2640 + /* Clear any lingering AHB errors */
2641 + config = read_c0_config();
2642 + write_c0_config(config & ~0x3);
2643 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2644 + ar231x_read_reg(AR2315_AHB_ERR1);
2645 + ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION);
2646 +
2647 + _machine_restart = ar2315_restart;
2648 + ar231x_serial_setup(AR2315_UART0, AR2315_MISC_IRQ_UART0,
2649 + ar2315_apb_frequency());
2650 +}
2651 --- /dev/null
2652 +++ b/arch/mips/ar231x/ar2315.h
2653 @@ -0,0 +1,37 @@
2654 +#ifndef __AR2315_H
2655 +#define __AR2315_H
2656 +
2657 +#ifdef CONFIG_ATHEROS_AR2315
2658 +
2659 +void ar2315_irq_init(void);
2660 +int ar2315_init_devices(void);
2661 +void ar2315_prom_init(void);
2662 +void ar2315_plat_setup(void);
2663 +void ar2315_time_init(void);
2664 +
2665 +#else
2666 +
2667 +static inline void ar2315_irq_init(void)
2668 +{
2669 +}
2670 +
2671 +static inline int ar2315_init_devices(void)
2672 +{
2673 + return 0;
2674 +}
2675 +
2676 +static inline void ar2315_prom_init(void)
2677 +{
2678 +}
2679 +
2680 +static inline void ar2315_plat_setup(void)
2681 +{
2682 +}
2683 +
2684 +static inline void ar2315_time_init(void)
2685 +{
2686 +}
2687 +
2688 +#endif
2689 +
2690 +#endif
2691 --- /dev/null
2692 +++ b/arch/mips/ar231x/ar5312.h
2693 @@ -0,0 +1,37 @@
2694 +#ifndef __AR5312_H
2695 +#define __AR5312_H
2696 +
2697 +#ifdef CONFIG_ATHEROS_AR5312
2698 +
2699 +void ar5312_irq_init(void);
2700 +int ar5312_init_devices(void);
2701 +void ar5312_prom_init(void);
2702 +void ar5312_plat_setup(void);
2703 +void ar5312_time_init(void);
2704 +
2705 +#else
2706 +
2707 +static inline void ar5312_irq_init(void)
2708 +{
2709 +}
2710 +
2711 +static inline int ar5312_init_devices(void)
2712 +{
2713 + return 0;
2714 +}
2715 +
2716 +static inline void ar5312_prom_init(void)
2717 +{
2718 +}
2719 +
2720 +static inline void ar5312_plat_setup(void)
2721 +{
2722 +}
2723 +
2724 +static inline void ar5312_time_init(void)
2725 +{
2726 +}
2727 +
2728 +#endif
2729 +
2730 +#endif
2731 --- /dev/null
2732 +++ b/arch/mips/include/asm/mach-ar231x/ar231x.h
2733 @@ -0,0 +1,43 @@
2734 +#ifndef __ASM_MACH_AR231X_H
2735 +#define __ASM_MACH_AR231X_H
2736 +
2737 +#include <linux/types.h>
2738 +#include <linux/io.h>
2739 +
2740 +#define AR231X_MISC_IRQ_BASE 0x20
2741 +#define AR231X_GPIO_IRQ_BASE 0x30
2742 +
2743 +/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
2744 +#define AR231X_IRQ_NONE (MIPS_CPU_IRQ_BASE+0)
2745 +#define AR231X_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE+7) /* C0_CAUSE: 0x8000 */
2746 +
2747 +/* GPIO Interrupts, share ARXXXX_MISC_IRQ_GPIO */
2748 +#define AR231X_GPIO_IRQ_NONE (AR231X_GPIO_IRQ_BASE+0)
2749 +#define AR231X_GPIO_IRQ(n) (AR231X_GPIO_IRQ_BASE+n)
2750 +
2751 +static inline u32
2752 +ar231x_read_reg(u32 reg)
2753 +{
2754 + return __raw_readl((void __iomem *)KSEG1ADDR(reg));
2755 +}
2756 +
2757 +static inline void
2758 +ar231x_write_reg(u32 reg, u32 val)
2759 +{
2760 + __raw_writel(val, (void __iomem *)KSEG1ADDR(reg));
2761 +}
2762 +
2763 +static inline u32
2764 +ar231x_mask_reg(u32 reg, u32 mask, u32 val)
2765 +{
2766 + u32 ret;
2767 +
2768 + ret = ar231x_read_reg(reg);
2769 + ret &= ~mask;
2770 + ret |= val;
2771 + ar231x_write_reg(reg, ret);
2772 +
2773 + return ret;
2774 +}
2775 +
2776 +#endif /* __ASM_MACH_AR231X_H */
2777 --- /dev/null
2778 +++ b/arch/mips/ar231x/devices.h
2779 @@ -0,0 +1,38 @@
2780 +#ifndef __AR231X_DEVICES_H
2781 +#define __AR231X_DEVICES_H
2782 +
2783 +enum {
2784 + /* handled by ar5312.c */
2785 + DEV_TYPE_AR2312,
2786 + DEV_TYPE_AR2313,
2787 + DEV_TYPE_AR5312,
2788 +
2789 + /* handled by ar2315.c */
2790 + DEV_TYPE_AR2315,
2791 + DEV_TYPE_AR2316,
2792 + DEV_TYPE_AR2317,
2793 +
2794 + DEV_TYPE_UNKNOWN
2795 +};
2796 +
2797 +extern int ar231x_devtype;
2798 +extern struct ar231x_board_config ar231x_board;
2799 +extern asmlinkage void (*ar231x_irq_dispatch)(void);
2800 +
2801 +int ar231x_find_config(u8 *flash_limit);
2802 +void ar231x_serial_setup(u32 mapbase, int irq, unsigned int uartclk);
2803 +int ar231x_add_wmac(int nr, u32 base, int irq);
2804 +int ar231x_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
2805 + int irq, void *pdata);
2806 +
2807 +static inline bool is_2315(void)
2808 +{
2809 + return (current_cpu_data.cputype == CPU_4KEC);
2810 +}
2811 +
2812 +static inline bool is_5312(void)
2813 +{
2814 + return !is_2315();
2815 +}
2816 +
2817 +#endif
2818 --- /dev/null
2819 +++ b/arch/mips/ar231x/devices.c
2820 @@ -0,0 +1,180 @@
2821 +#include <linux/kernel.h>
2822 +#include <linux/init.h>
2823 +#include <linux/serial.h>
2824 +#include <linux/serial_core.h>
2825 +#include <linux/serial_8250.h>
2826 +#include <linux/platform_device.h>
2827 +#include <asm/bootinfo.h>
2828 +
2829 +#include <ar231x_platform.h>
2830 +#include <ar231x.h>
2831 +#include "devices.h"
2832 +#include "ar5312.h"
2833 +#include "ar2315.h"
2834 +
2835 +struct ar231x_board_config ar231x_board;
2836 +int ar231x_devtype = DEV_TYPE_UNKNOWN;
2837 +
2838 +static struct resource ar231x_eth0_res[] = {
2839 + {
2840 + .name = "eth0_membase",
2841 + .flags = IORESOURCE_MEM,
2842 + },
2843 + {
2844 + .name = "eth0_mii",
2845 + .flags = IORESOURCE_MEM,
2846 + },
2847 + {
2848 + .name = "eth0_irq",
2849 + .flags = IORESOURCE_IRQ,
2850 + }
2851 +};
2852 +
2853 +static struct resource ar231x_eth1_res[] = {
2854 + {
2855 + .name = "eth1_membase",
2856 + .flags = IORESOURCE_MEM,
2857 + },
2858 + {
2859 + .name = "eth1_mii",
2860 + .flags = IORESOURCE_MEM,
2861 + },
2862 + {
2863 + .name = "eth1_irq",
2864 + .flags = IORESOURCE_IRQ,
2865 + }
2866 +};
2867 +
2868 +static struct platform_device ar231x_eth[] = {
2869 + {
2870 + .id = 0,
2871 + .name = "ar231x-eth",
2872 + .resource = ar231x_eth0_res,
2873 + .num_resources = ARRAY_SIZE(ar231x_eth0_res)
2874 + },
2875 + {
2876 + .id = 1,
2877 + .name = "ar231x-eth",
2878 + .resource = ar231x_eth1_res,
2879 + .num_resources = ARRAY_SIZE(ar231x_eth1_res)
2880 + }
2881 +};
2882 +
2883 +static struct resource ar231x_wmac0_res[] = {
2884 + {
2885 + .name = "wmac0_membase",
2886 + .flags = IORESOURCE_MEM,
2887 + },
2888 + {
2889 + .name = "wmac0_irq",
2890 + .flags = IORESOURCE_IRQ,
2891 + }
2892 +};
2893 +
2894 +static struct resource ar231x_wmac1_res[] = {
2895 + {
2896 + .name = "wmac1_membase",
2897 + .flags = IORESOURCE_MEM,
2898 + },
2899 + {
2900 + .name = "wmac1_irq",
2901 + .flags = IORESOURCE_IRQ,
2902 + }
2903 +};
2904 +
2905 +static struct platform_device ar231x_wmac[] = {
2906 + {
2907 + .id = 0,
2908 + .name = "ar231x-wmac",
2909 + .resource = ar231x_wmac0_res,
2910 + .num_resources = ARRAY_SIZE(ar231x_wmac0_res),
2911 + .dev.platform_data = &ar231x_board,
2912 + },
2913 + {
2914 + .id = 1,
2915 + .name = "ar231x-wmac",
2916 + .resource = ar231x_wmac1_res,
2917 + .num_resources = ARRAY_SIZE(ar231x_wmac1_res),
2918 + .dev.platform_data = &ar231x_board,
2919 + },
2920 +};
2921 +
2922 +static const char * const devtype_strings[] = {
2923 + [DEV_TYPE_AR5312] = "Atheros AR5312",
2924 + [DEV_TYPE_AR2312] = "Atheros AR2312",
2925 + [DEV_TYPE_AR2313] = "Atheros AR2313",
2926 + [DEV_TYPE_AR2315] = "Atheros AR2315",
2927 + [DEV_TYPE_AR2316] = "Atheros AR2316",
2928 + [DEV_TYPE_AR2317] = "Atheros AR2317",
2929 + [DEV_TYPE_UNKNOWN] = "Atheros (unknown)",
2930 +};
2931 +
2932 +const char *get_system_type(void)
2933 +{
2934 + if ((ar231x_devtype >= ARRAY_SIZE(devtype_strings)) ||
2935 + !devtype_strings[ar231x_devtype])
2936 + return devtype_strings[DEV_TYPE_UNKNOWN];
2937 + return devtype_strings[ar231x_devtype];
2938 +}
2939 +
2940 +int __init
2941 +ar231x_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
2942 + int irq, void *pdata)
2943 +{
2944 + struct resource *res;
2945 +
2946 + ar231x_eth[nr].dev.platform_data = pdata;
2947 + res = &ar231x_eth[nr].resource[0];
2948 + res->start = base;
2949 + res->end = base + 0x2000 - 1;
2950 + res++;
2951 + res->name = mii_name;
2952 + res->start = mii_base;
2953 + res->end = mii_base + 8 - 1;
2954 + res++;
2955 + res->start = irq;
2956 + res->end = irq;
2957 + return platform_device_register(&ar231x_eth[nr]);
2958 +}
2959 +
2960 +void __init
2961 +ar231x_serial_setup(u32 mapbase, int irq, unsigned int uartclk)
2962 +{
2963 + struct uart_port s;
2964 +
2965 + memset(&s, 0, sizeof(s));
2966 +
2967 + s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP;
2968 + s.iotype = UPIO_MEM32;
2969 + s.irq = irq;
2970 + s.regshift = 2;
2971 + s.mapbase = mapbase;
2972 + s.uartclk = uartclk;
2973 +
2974 + early_serial_setup(&s);
2975 +}
2976 +
2977 +int __init
2978 +ar231x_add_wmac(int nr, u32 base, int irq)
2979 +{
2980 + struct resource *res;
2981 +
2982 + ar231x_wmac[nr].dev.platform_data = &ar231x_board;
2983 + res = &ar231x_wmac[nr].resource[0];
2984 + res->start = base;
2985 + res->end = base + 0x10000 - 1;
2986 + res++;
2987 + res->start = irq;
2988 + res->end = irq;
2989 + return platform_device_register(&ar231x_wmac[nr]);
2990 +}
2991 +
2992 +static int __init ar231x_register_devices(void)
2993 +{
2994 + ar5312_init_devices();
2995 + ar2315_init_devices();
2996 +
2997 + return 0;
2998 +}
2999 +
3000 +device_initcall(ar231x_register_devices);
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