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atheros: convert gpio.h to stub
[openwrt/openwrt.git] / target / linux / atheros / patches-3.14 / 100-board.patch
1 --- a/arch/mips/Kconfig
2 +++ b/arch/mips/Kconfig
3 @@ -144,6 +144,19 @@ config BCM63XX
4 help
5 Support for BCM63XX based boards
6
7 +config ATHEROS_AR231X
8 + bool "Atheros 231x/531x SoC support"
9 + select CEVT_R4K
10 + select CSRC_R4K
11 + select DMA_NONCOHERENT
12 + select IRQ_CPU
13 + select SYS_HAS_CPU_MIPS32_R1
14 + select SYS_SUPPORTS_BIG_ENDIAN
15 + select SYS_SUPPORTS_32BIT_KERNEL
16 + select ARCH_REQUIRE_GPIOLIB
17 + help
18 + Support for AR231x and AR531x based boards
19 +
20 config MIPS_COBALT
21 bool "Cobalt Server"
22 select CEVT_R4K
23 @@ -795,6 +808,7 @@ config NLM_XLP_BOARD
24
25 endchoice
26
27 +source "arch/mips/ar231x/Kconfig"
28 source "arch/mips/alchemy/Kconfig"
29 source "arch/mips/ath79/Kconfig"
30 source "arch/mips/bcm47xx/Kconfig"
31 --- a/arch/mips/Kbuild.platforms
32 +++ b/arch/mips/Kbuild.platforms
33 @@ -6,6 +6,7 @@ platforms += ath79
34 platforms += bcm47xx
35 platforms += bcm63xx
36 platforms += cavium-octeon
37 +platforms += ar231x
38 platforms += cobalt
39 platforms += dec
40 platforms += emma
41 --- /dev/null
42 +++ b/arch/mips/ar231x/Platform
43 @@ -0,0 +1,6 @@
44 +#
45 +# Atheros AR531X/AR231X WiSoC
46 +#
47 +platform-$(CONFIG_ATHEROS_AR231X) += ar231x/
48 +cflags-$(CONFIG_ATHEROS_AR231X) += -I$(srctree)/arch/mips/include/asm/mach-ar231x
49 +load-$(CONFIG_ATHEROS_AR231X) += 0xffffffff80041000
50 --- /dev/null
51 +++ b/arch/mips/ar231x/Kconfig
52 @@ -0,0 +1,9 @@
53 +config SOC_AR5312
54 + bool "Atheros 5312/2312+ support"
55 + depends on ATHEROS_AR231X
56 + default y
57 +
58 +config SOC_AR2315
59 + bool "Atheros 2315+ support"
60 + depends on ATHEROS_AR231X
61 + default y
62 --- /dev/null
63 +++ b/arch/mips/ar231x/Makefile
64 @@ -0,0 +1,13 @@
65 +#
66 +# This file is subject to the terms and conditions of the GNU General Public
67 +# License. See the file "COPYING" in the main directory of this archive
68 +# for more details.
69 +#
70 +# Copyright (C) 2006 FON Technology, SL.
71 +# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
72 +# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
73 +#
74 +
75 +obj-y += board.o prom.o devices.o
76 +obj-$(CONFIG_SOC_AR5312) += ar5312.o
77 +obj-$(CONFIG_SOC_AR2315) += ar2315.o
78 --- /dev/null
79 +++ b/arch/mips/ar231x/board.c
80 @@ -0,0 +1,229 @@
81 +/*
82 + * This file is subject to the terms and conditions of the GNU General Public
83 + * License. See the file "COPYING" in the main directory of this archive
84 + * for more details.
85 + *
86 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
87 + * Copyright (C) 2006 FON Technology, SL.
88 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
89 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
90 + */
91 +
92 +#include <generated/autoconf.h>
93 +#include <linux/init.h>
94 +#include <linux/module.h>
95 +#include <linux/types.h>
96 +#include <linux/string.h>
97 +#include <linux/platform_device.h>
98 +#include <linux/kernel.h>
99 +#include <linux/random.h>
100 +#include <linux/etherdevice.h>
101 +#include <linux/irq.h>
102 +#include <linux/io.h>
103 +#include <asm/irq_cpu.h>
104 +#include <asm/reboot.h>
105 +#include <asm/bootinfo.h>
106 +#include <asm/time.h>
107 +
108 +#include <ar231x_platform.h>
109 +#include "devices.h"
110 +#include "ar5312.h"
111 +#include "ar2315.h"
112 +
113 +void (*ar231x_irq_dispatch)(void);
114 +
115 +static inline bool check_radio_magic(u8 *addr)
116 +{
117 + addr += 0x7a; /* offset for flash magic */
118 + return (addr[0] == 0x5a) && (addr[1] == 0xa5);
119 +}
120 +
121 +static inline bool check_notempty(u8 *addr)
122 +{
123 + return *(u32 *)addr != 0xffffffff;
124 +}
125 +
126 +static inline bool check_board_data(u8 *flash_limit, u8 *addr, bool broken)
127 +{
128 + /* config magic found */
129 + if (*((u32 *)addr) == AR231X_BD_MAGIC)
130 + return true;
131 +
132 + if (!broken)
133 + return false;
134 +
135 + if (check_radio_magic(addr + 0xf8))
136 + ar231x_board.radio = addr + 0xf8;
137 + if ((addr < flash_limit + 0x10000) &&
138 + check_radio_magic(addr + 0x10000))
139 + ar231x_board.radio = addr + 0x10000;
140 +
141 + if (ar231x_board.radio) {
142 + /* broken board data detected, use radio data to find the
143 + * offset, user will fix this */
144 + return true;
145 + }
146 +
147 + return false;
148 +}
149 +
150 +static u8 * __init find_board_config(u8 *flash_limit, bool broken)
151 +{
152 + u8 *addr;
153 + u8 *begin = flash_limit - 0x1000;
154 + u8 *end = flash_limit - 0x30000;
155 +
156 + for (addr = begin; addr >= end; addr -= 0x1000)
157 + if (check_board_data(flash_limit, addr, broken))
158 + return addr;
159 +
160 + return NULL;
161 +}
162 +
163 +static u8 * __init find_radio_config(u8 *flash_limit, u8 *bcfg)
164 +{
165 + u8 *rcfg, *begin, *end;
166 +
167 + /*
168 + * Now find the start of Radio Configuration data, using heuristics:
169 + * Search forward from Board Configuration data by 0x1000 bytes
170 + * at a time until we find non-0xffffffff.
171 + */
172 + begin = bcfg + 0x1000;
173 + end = flash_limit;
174 + for (rcfg = begin; rcfg < end; rcfg += 0x1000)
175 + if (check_notempty(rcfg) && check_radio_magic(rcfg))
176 + return rcfg;
177 +
178 + /* AR2316 relocates radio config to new location */
179 + begin = bcfg + 0xf8;
180 + end = flash_limit - 0x1000 + 0xf8;
181 + for (rcfg = begin; rcfg < end; rcfg += 0x1000)
182 + if (check_notempty(rcfg) && check_radio_magic(rcfg))
183 + return rcfg;
184 +
185 + pr_warn("WARNING: Could not find Radio Configuration data\n");
186 +
187 + return NULL;
188 +}
189 +
190 +int __init ar231x_find_config(u8 *flash_limit)
191 +{
192 + struct ar231x_boarddata *config;
193 + unsigned int rcfg_size;
194 + int broken_boarddata = 0;
195 + u8 *bcfg, *rcfg;
196 + u8 *board_data;
197 + u8 *radio_data;
198 + u8 *mac_addr;
199 + u32 offset;
200 +
201 + ar231x_board.config = NULL;
202 + ar231x_board.radio = NULL;
203 + /* Copy the board and radio data to RAM, because accessing the mapped
204 + * memory of the flash directly after booting is not safe */
205 +
206 + /* Try to find valid board and radio data */
207 + bcfg = find_board_config(flash_limit, false);
208 +
209 + /* If that fails, try to at least find valid radio data */
210 + if (!bcfg) {
211 + bcfg = find_board_config(flash_limit, true);
212 + broken_boarddata = 1;
213 + }
214 +
215 + if (!bcfg) {
216 + pr_warn("WARNING: No board configuration data found!\n");
217 + return -ENODEV;
218 + }
219 +
220 + board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
221 + ar231x_board.config = (struct ar231x_boarddata *)board_data;
222 + memcpy(board_data, bcfg, 0x100);
223 + if (broken_boarddata) {
224 + pr_warn("WARNING: broken board data detected\n");
225 + config = ar231x_board.config;
226 + if (is_zero_ether_addr(config->enet0_mac)) {
227 + pr_info("Fixing up empty mac addresses\n");
228 + config->reset_config_gpio = 0xffff;
229 + config->sys_led_gpio = 0xffff;
230 + random_ether_addr(config->wlan0_mac);
231 + config->wlan0_mac[0] &= ~0x06;
232 + random_ether_addr(config->enet0_mac);
233 + random_ether_addr(config->enet1_mac);
234 + }
235 + }
236 +
237 + /* Radio config starts 0x100 bytes after board config, regardless
238 + * of what the physical layout on the flash chip looks like */
239 +
240 + if (ar231x_board.radio)
241 + rcfg = (u8 *)ar231x_board.radio;
242 + else
243 + rcfg = find_radio_config(flash_limit, bcfg);
244 +
245 + if (!rcfg)
246 + return -ENODEV;
247 +
248 + radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
249 + ar231x_board.radio = radio_data;
250 + offset = radio_data - board_data;
251 + pr_info("Radio config found at offset 0x%x (0x%x)\n", rcfg - bcfg,
252 + offset);
253 + rcfg_size = BOARD_CONFIG_BUFSZ - offset;
254 + memcpy(radio_data, rcfg, rcfg_size);
255 +
256 + mac_addr = &radio_data[0x1d * 2];
257 + if (is_broadcast_ether_addr(mac_addr)) {
258 + pr_info("Radio MAC is blank; using board-data\n");
259 + ether_addr_copy(mac_addr, ar231x_board.config->wlan0_mac);
260 + }
261 +
262 + return 0;
263 +}
264 +
265 +static void ar231x_halt(void)
266 +{
267 + local_irq_disable();
268 + while (1)
269 + ;
270 +}
271 +
272 +void __init plat_mem_setup(void)
273 +{
274 + _machine_halt = ar231x_halt;
275 + pm_power_off = ar231x_halt;
276 +
277 + ar5312_plat_setup();
278 + ar2315_plat_setup();
279 +
280 + /* Disable data watchpoints */
281 + write_c0_watchlo0(0);
282 +}
283 +
284 +asmlinkage void plat_irq_dispatch(void)
285 +{
286 + ar231x_irq_dispatch();
287 +}
288 +
289 +void __init plat_time_init(void)
290 +{
291 + ar5312_time_init();
292 + ar2315_time_init();
293 +}
294 +
295 +unsigned int __cpuinit get_c0_compare_int(void)
296 +{
297 + return CP0_LEGACY_COMPARE_IRQ;
298 +}
299 +
300 +void __init arch_init_irq(void)
301 +{
302 + clear_c0_status(ST0_IM);
303 + mips_cpu_irq_init();
304 +
305 + /* Initialize interrupt controllers */
306 + ar5312_irq_init();
307 + ar2315_irq_init();
308 +}
309 +
310 --- /dev/null
311 +++ b/arch/mips/ar231x/prom.c
312 @@ -0,0 +1,37 @@
313 +/*
314 + * This file is subject to the terms and conditions of the GNU General Public
315 + * License. See the file "COPYING" in the main directory of this archive
316 + * for more details.
317 + *
318 + * Copyright MontaVista Software Inc
319 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
320 + * Copyright (C) 2006 FON Technology, SL.
321 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
322 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
323 + */
324 +
325 +/*
326 + * Prom setup file for ar231x
327 + */
328 +
329 +#include <linux/init.h>
330 +#include <generated/autoconf.h>
331 +#include <linux/kernel.h>
332 +#include <linux/string.h>
333 +#include <linux/mm.h>
334 +#include <linux/bootmem.h>
335 +
336 +#include <asm/bootinfo.h>
337 +#include <asm/addrspace.h>
338 +#include "ar5312.h"
339 +#include "ar2315.h"
340 +
341 +void __init prom_init(void)
342 +{
343 + ar5312_prom_init();
344 + ar2315_prom_init();
345 +}
346 +
347 +void __init prom_free_prom_memory(void)
348 +{
349 +}
350 --- /dev/null
351 +++ b/arch/mips/include/asm/mach-ar231x/ar231x_platform.h
352 @@ -0,0 +1,85 @@
353 +#ifndef __ASM_MACH_AR231X_PLATFORM_H
354 +#define __ASM_MACH_AR231X_PLATFORM_H
355 +
356 +#include <linux/etherdevice.h>
357 +
358 +/*
359 + * This is board-specific data that is stored in a "fixed" location in flash.
360 + * It is shared across operating systems, so it should not be changed lightly.
361 + * The main reason we need it is in order to extract the ethernet MAC
362 + * address(es).
363 + */
364 +struct ar231x_boarddata {
365 + u32 magic; /* board data is valid */
366 +#define AR231X_BD_MAGIC 0x35333131 /* "5311", for all 531x/231x platforms */
367 + u16 cksum; /* checksum (starting with BD_REV 2) */
368 + u16 rev; /* revision of this struct */
369 +#define BD_REV 4
370 + char board_name[64]; /* Name of board */
371 + u16 major; /* Board major number */
372 + u16 minor; /* Board minor number */
373 + u32 flags; /* Board configuration */
374 +#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
375 +#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
376 +#define BD_UART1 0x00000004 /* UART1 is stuffed */
377 +#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
378 +#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
379 +#define BD_SYSLED 0x00000020 /* System LED stuffed */
380 +#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
381 +#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
382 +#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
383 +#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
384 +#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ mem_cap for testing */
385 +#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
386 +#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
387 +#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
388 +#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
389 +#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
390 +#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
391 +#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
392 + u16 reset_config_gpio; /* Reset factory GPIO pin */
393 + u16 sys_led_gpio; /* System LED GPIO pin */
394 +
395 + u32 cpu_freq; /* CPU core frequency in Hz */
396 + u32 sys_freq; /* System frequency in Hz */
397 + u32 cnt_freq; /* Calculated C0_COUNT frequency */
398 +
399 + u8 wlan0_mac[ETH_ALEN];
400 + u8 enet0_mac[ETH_ALEN];
401 + u8 enet1_mac[ETH_ALEN];
402 +
403 + u16 pci_id; /* Pseudo PCIID for common code */
404 + u16 mem_cap; /* cap bank1 in MB */
405 +
406 + /* version 3 */
407 + u8 wlan1_mac[ETH_ALEN]; /* (ar5212) */
408 +};
409 +
410 +#define BOARD_CONFIG_BUFSZ 0x1000
411 +
412 +/*
413 + * Platform device information for the Wireless MAC
414 + */
415 +struct ar231x_board_config {
416 + u16 devid;
417 +
418 + /* board config data */
419 + struct ar231x_boarddata *config;
420 +
421 + /* radio calibration data */
422 + const char *radio;
423 +};
424 +
425 +/*
426 + * Platform device information for the Ethernet MAC
427 + */
428 +struct ar231x_eth {
429 + void (*reset_set)(u32);
430 + void (*reset_clear)(u32);
431 + u32 reset_mac;
432 + u32 reset_phy;
433 + struct ar231x_board_config *config;
434 + char *macaddr;
435 +};
436 +
437 +#endif /* __ASM_MACH_AR231X_PLATFORM_H */
438 --- /dev/null
439 +++ b/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h
440 @@ -0,0 +1,84 @@
441 +/*
442 + * Atheros AR231x/AR531x SoC specific CPU feature overrides
443 + *
444 + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
445 + *
446 + * This file was derived from: include/asm-mips/cpu-features.h
447 + * Copyright (C) 2003, 2004 Ralf Baechle
448 + * Copyright (C) 2004 Maciej W. Rozycki
449 + *
450 + * This program is free software; you can redistribute it and/or modify it
451 + * under the terms of the GNU General Public License version 2 as published
452 + * by the Free Software Foundation.
453 + *
454 + */
455 +#ifndef __ASM_MACH_AR231X_CPU_FEATURE_OVERRIDES_H
456 +#define __ASM_MACH_AR231X_CPU_FEATURE_OVERRIDES_H
457 +
458 +/*
459 + * The Atheros AR531x/AR231x SoCs have MIPS 4Kc/4KEc core.
460 + */
461 +#define cpu_has_tlb 1
462 +#define cpu_has_4kex 1
463 +#define cpu_has_3k_cache 0
464 +#define cpu_has_4k_cache 1
465 +#define cpu_has_tx39_cache 0
466 +#define cpu_has_sb1_cache 0
467 +#define cpu_has_fpu 0
468 +#define cpu_has_32fpr 0
469 +#define cpu_has_counter 1
470 +/* #define cpu_has_watch ? */
471 +/* #define cpu_has_divec ? */
472 +/* #define cpu_has_vce ? */
473 +/* #define cpu_has_cache_cdex_p ? */
474 +/* #define cpu_has_cache_cdex_s ? */
475 +/* #define cpu_has_prefetch ? */
476 +/* #define cpu_has_mcheck ? */
477 +#define cpu_has_ejtag 1
478 +
479 +#if !defined(CONFIG_SOC_AR5312)
480 +# define cpu_has_llsc 1
481 +#else
482 +/*
483 + * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
484 + * ll/sc instructions.
485 + */
486 +# define cpu_has_llsc 0
487 +#endif
488 +
489 +#define cpu_has_mips16 0
490 +#define cpu_has_mdmx 0
491 +#define cpu_has_mips3d 0
492 +#define cpu_has_smartmips 0
493 +
494 +/* #define cpu_has_vtag_icache ? */
495 +/* #define cpu_has_dc_aliases ? */
496 +/* #define cpu_has_ic_fills_f_dc ? */
497 +/* #define cpu_has_pindexed_dcache ? */
498 +
499 +/* #define cpu_icache_snoops_remote_store ? */
500 +
501 +#define cpu_has_mips32r1 1
502 +
503 +#if !defined(CONFIG_SOC_AR5312)
504 +# define cpu_has_mips32r2 1
505 +#endif
506 +
507 +#define cpu_has_mips64r1 0
508 +#define cpu_has_mips64r2 0
509 +
510 +#define cpu_has_dsp 0
511 +#define cpu_has_mipsmt 0
512 +
513 +/* #define cpu_has_nofpuex ? */
514 +#define cpu_has_64bits 0
515 +#define cpu_has_64bit_zero_reg 0
516 +#define cpu_has_64bit_gp_regs 0
517 +#define cpu_has_64bit_addresses 0
518 +
519 +/* #define cpu_has_inclusive_pcaches ? */
520 +
521 +/* #define cpu_dcache_line_size() ? */
522 +/* #define cpu_icache_line_size() ? */
523 +
524 +#endif /* __ASM_MACH_AR231X_CPU_FEATURE_OVERRIDES_H */
525 --- /dev/null
526 +++ b/arch/mips/include/asm/mach-ar231x/dma-coherence.h
527 @@ -0,0 +1,76 @@
528 +/*
529 + * This file is subject to the terms and conditions of the GNU General Public
530 + * License. See the file "COPYING" in the main directory of this archive
531 + * for more details.
532 + *
533 + * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
534 + * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
535 + *
536 + */
537 +#ifndef __ASM_MACH_AR231X_DMA_COHERENCE_H
538 +#define __ASM_MACH_AR231X_DMA_COHERENCE_H
539 +
540 +#include <linux/device.h>
541 +#include <ar2315_regs.h>
542 +
543 +static inline dma_addr_t ar231x_dev_offset(struct device *dev)
544 +{
545 +#ifdef CONFIG_PCI
546 + extern struct bus_type pci_bus_type;
547 +
548 + if (dev && dev->bus == &pci_bus_type)
549 + return AR2315_PCI_HOST_SDRAM_BASEADDR;
550 +#endif
551 + return 0;
552 +}
553 +
554 +static inline dma_addr_t
555 +plat_map_dma_mem(struct device *dev, void *addr, size_t size)
556 +{
557 + return virt_to_phys(addr) + ar231x_dev_offset(dev);
558 +}
559 +
560 +static inline dma_addr_t
561 +plat_map_dma_mem_page(struct device *dev, struct page *page)
562 +{
563 + return page_to_phys(page) + ar231x_dev_offset(dev);
564 +}
565 +
566 +static inline unsigned long
567 +plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
568 +{
569 + return dma_addr - ar231x_dev_offset(dev);
570 +}
571 +
572 +static inline void
573 +plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, size_t size,
574 + enum dma_data_direction direction)
575 +{
576 +}
577 +
578 +static inline int plat_dma_supported(struct device *dev, u64 mask)
579 +{
580 + return 1;
581 +}
582 +
583 +static inline void plat_extra_sync_for_device(struct device *dev)
584 +{
585 +}
586 +
587 +static inline int plat_dma_mapping_error(struct device *dev,
588 + dma_addr_t dma_addr)
589 +{
590 + return 0;
591 +}
592 +
593 +static inline int plat_device_is_coherent(struct device *dev)
594 +{
595 +#ifdef CONFIG_DMA_COHERENT
596 + return 1;
597 +#endif
598 +#ifdef CONFIG_DMA_NONCOHERENT
599 + return 0;
600 +#endif
601 +}
602 +
603 +#endif /* __ASM_MACH_AR231X_DMA_COHERENCE_H */
604 --- /dev/null
605 +++ b/arch/mips/include/asm/mach-ar231x/gpio.h
606 @@ -0,0 +1,16 @@
607 +#ifndef __ASM_MACH_AR231X_GPIO_H
608 +#define __ASM_MACH_AR231X_GPIO_H
609 +
610 +#include <asm-generic/gpio.h>
611 +
612 +#define gpio_get_value __gpio_get_value
613 +#define gpio_set_value __gpio_set_value
614 +#define gpio_cansleep __gpio_cansleep
615 +#define gpio_to_irq __gpio_to_irq
616 +
617 +static inline int irq_to_gpio(unsigned irq)
618 +{
619 + return -EINVAL;
620 +}
621 +
622 +#endif /* __ASM_MACH_AR231X_GPIO_H */
623 --- /dev/null
624 +++ b/arch/mips/include/asm/mach-ar231x/reset.h
625 @@ -0,0 +1,6 @@
626 +#ifndef __ASM_MACH_AR231X_RESET_H
627 +#define __ASM_MACH_AR231X_RESET_H
628 +
629 +void ar231x_disable_reset_button(void);
630 +
631 +#endif /* __ASM_MACH_AR231X_RESET_H */
632 --- /dev/null
633 +++ b/arch/mips/include/asm/mach-ar231x/war.h
634 @@ -0,0 +1,25 @@
635 +/*
636 + * This file is subject to the terms and conditions of the GNU General Public
637 + * License. See the file "COPYING" in the main directory of this archive
638 + * for more details.
639 + *
640 + * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
641 + */
642 +#ifndef __ASM_MACH_AR231X_WAR_H
643 +#define __ASM_MACH_AR231X_WAR_H
644 +
645 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
646 +#define R4600_V1_HIT_CACHEOP_WAR 0
647 +#define R4600_V2_HIT_CACHEOP_WAR 0
648 +#define R5432_CP0_INTERRUPT_WAR 0
649 +#define BCM1250_M3_WAR 0
650 +#define SIBYTE_1956_WAR 0
651 +#define MIPS4K_ICACHE_REFILL_WAR 0
652 +#define MIPS_CACHE_SYNC_WAR 0
653 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
654 +#define RM9000_CDEX_SMP_WAR 0
655 +#define ICACHE_REFILLS_WORKAROUND_WAR 0
656 +#define R10000_LLSC_WAR 0
657 +#define MIPS34K_MISSED_ITLB_WAR 0
658 +
659 +#endif /* __ASM_MACH_AR231X_WAR_H */
660 --- /dev/null
661 +++ b/arch/mips/include/asm/mach-ar231x/ar2315_regs.h
662 @@ -0,0 +1,631 @@
663 +/*
664 + * Register definitions for AR2315+
665 + *
666 + * This file is subject to the terms and conditions of the GNU General Public
667 + * License. See the file "COPYING" in the main directory of this archive
668 + * for more details.
669 + *
670 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
671 + * Copyright (C) 2006 FON Technology, SL.
672 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
673 + * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
674 + */
675 +
676 +#ifndef __ASM_MACH_AR231X_AR2315_REGS_H
677 +#define __ASM_MACH_AR231X_AR2315_REGS_H
678 +
679 +/*
680 + * IRQs
681 + */
682 +#define AR2315_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
683 +#define AR2315_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
684 +#define AR2315_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
685 +#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
686 +#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
687 +
688 +/*
689 + * Miscellaneous interrupts, which share IP2.
690 + */
691 +#define AR2315_MISC_IRQ_NONE (AR231X_MISC_IRQ_BASE+0)
692 +#define AR2315_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+1)
693 +#define AR2315_MISC_IRQ_I2C_RSVD (AR231X_MISC_IRQ_BASE+2)
694 +#define AR2315_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+3)
695 +#define AR2315_MISC_IRQ_AHB (AR231X_MISC_IRQ_BASE+4)
696 +#define AR2315_MISC_IRQ_APB (AR231X_MISC_IRQ_BASE+5)
697 +#define AR2315_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+6)
698 +#define AR2315_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+7)
699 +#define AR2315_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+8)
700 +#define AR2315_MISC_IRQ_IR_RSVD (AR231X_MISC_IRQ_BASE+9)
701 +#define AR2315_MISC_IRQ_COUNT 10
702 +
703 +/*
704 + * PCI interrupts, which share IP5
705 + * Keep ordered according to AR2315_PCI_INT_XXX bits
706 + */
707 +#define AR2315_PCI_IRQ_BASE 0x50
708 +#define AR2315_PCI_IRQ_EXT (AR2315_PCI_IRQ_BASE+0)
709 +#define AR2315_PCI_IRQ_ABORT (AR2315_PCI_IRQ_BASE+1)
710 +#define AR2315_PCI_IRQ_COUNT 2
711 +#define AR2315_PCI_IRQ_SHIFT 25 /* in AR2315_PCI_INT_STATUS */
712 +
713 +/*
714 + * Address map
715 + */
716 +#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */
717 +#define AR2315_WLAN0 0x10000000 /* Wireless MMR */
718 +#define AR2315_PCI 0x10100000 /* PCI MMR */
719 +#define AR2315_SDRAMCTL 0x10300000 /* SDRAM MMR */
720 +#define AR2315_LOCAL 0x10400000 /* LOCAL BUS MMR */
721 +#define AR2315_ENET0 0x10500000 /* ETHERNET MMR */
722 +#define AR2315_DSLBASE 0x11000000 /* RESET CONTROL MMR */
723 +#define AR2315_UART0 0x11100000 /* UART MMR */
724 +#define AR2315_SPI_MMR 0x11300000 /* SPI FLASH MMR */
725 +#define AR2315_PCIEXT 0x80000000 /* pci external */
726 +#define AR2315_PCIEXT_SZ 0x40000000
727 +
728 +/* MII registers offset inside Ethernet MMR region */
729 +#define AR2315_ENET0_MII (AR2315_ENET0 + 0x14)
730 +
731 +/*
732 + * Cold reset register
733 + */
734 +#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000)
735 +
736 +#define AR2315_RESET_COLD_AHB 0x00000001
737 +#define AR2315_RESET_COLD_APB 0x00000002
738 +#define AR2315_RESET_COLD_CPU 0x00000004
739 +#define AR2315_RESET_COLD_CPUWARM 0x00000008
740 +#define AR2315_RESET_SYSTEM \
741 + (RESET_COLD_CPU |\
742 + RESET_COLD_APB |\
743 + RESET_COLD_AHB) /* full system */
744 +#define AR2317_RESET_SYSTEM 0x00000010
745 +
746 +/*
747 + * Reset register
748 + */
749 +#define AR2315_RESET (AR2315_DSLBASE + 0x0004)
750 +
751 +/* warm reset WLAN0 MAC */
752 +#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001
753 +/* warm reset WLAN0 BaseBand */
754 +#define AR2315_RESET_WARM_WLAN0_BB 0x00000002
755 +/* warm reset MPEG-TS */
756 +#define AR2315_RESET_MPEGTS_RSVD 0x00000004
757 +/* warm reset PCI ahb/dma */
758 +#define AR2315_RESET_PCIDMA 0x00000008
759 +/* warm reset memory controller */
760 +#define AR2315_RESET_MEMCTL 0x00000010
761 +/* warm reset local bus */
762 +#define AR2315_RESET_LOCAL 0x00000020
763 +/* warm reset I2C bus */
764 +#define AR2315_RESET_I2C_RSVD 0x00000040
765 +/* warm reset SPI interface */
766 +#define AR2315_RESET_SPI 0x00000080
767 +/* warm reset UART0 */
768 +#define AR2315_RESET_UART0 0x00000100
769 +/* warm reset IR interface */
770 +#define AR2315_RESET_IR_RSVD 0x00000200
771 +/* cold reset ENET0 phy */
772 +#define AR2315_RESET_EPHY0 0x00000400
773 +/* cold reset ENET0 mac */
774 +#define AR2315_RESET_ENET0 0x00000800
775 +
776 +/*
777 + * AHB master arbitration control
778 + */
779 +#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008)
780 +
781 +/* CPU, default */
782 +#define AR2315_ARB_CPU 0x00000001
783 +/* WLAN */
784 +#define AR2315_ARB_WLAN 0x00000002
785 +/* MPEG-TS */
786 +#define AR2315_ARB_MPEGTS_RSVD 0x00000004
787 +/* LOCAL */
788 +#define AR2315_ARB_LOCAL 0x00000008
789 +/* PCI */
790 +#define AR2315_ARB_PCI 0x00000010
791 +/* Ethernet */
792 +#define AR2315_ARB_ETHERNET 0x00000020
793 +/* retry policy, debug only */
794 +#define AR2315_ARB_RETRY 0x00000100
795 +
796 +/*
797 + * Config Register
798 + */
799 +#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c)
800 +
801 +/* EC - AHB bridge endianess */
802 +#define AR2315_CONFIG_AHB 0x00000001
803 +/* WLAN byteswap */
804 +#define AR2315_CONFIG_WLAN 0x00000002
805 +/* MPEG-TS byteswap */
806 +#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004
807 +/* PCI byteswap */
808 +#define AR2315_CONFIG_PCI 0x00000008
809 +/* Memory controller endianess */
810 +#define AR2315_CONFIG_MEMCTL 0x00000010
811 +/* Local bus byteswap */
812 +#define AR2315_CONFIG_LOCAL 0x00000020
813 +/* Ethernet byteswap */
814 +#define AR2315_CONFIG_ETHERNET 0x00000040
815 +
816 +/* CPU write buffer merge */
817 +#define AR2315_CONFIG_MERGE 0x00000200
818 +/* CPU big endian */
819 +#define AR2315_CONFIG_CPU 0x00000400
820 +#define AR2315_CONFIG_PCIAHB 0x00000800
821 +#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
822 +/* SPI byteswap */
823 +#define AR2315_CONFIG_SPI 0x00008000
824 +#define AR2315_CONFIG_CPU_DRAM 0x00010000
825 +#define AR2315_CONFIG_CPU_PCI 0x00020000
826 +#define AR2315_CONFIG_CPU_MMR 0x00040000
827 +#define AR2315_CONFIG_BIG 0x00000400
828 +
829 +/*
830 + * NMI control
831 + */
832 +#define AR2315_NMI_CTL (AR2315_DSLBASE + 0x0010)
833 +
834 +#define AR2315_NMI_EN 1
835 +
836 +/*
837 + * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR231X 1.0).
838 + */
839 +#define AR2315_SREV (AR2315_DSLBASE + 0x0014)
840 +
841 +#define AR2315_REV_MAJ 0x00f0
842 +#define AR2315_REV_MAJ_S 4
843 +#define AR2315_REV_MIN 0x000f
844 +#define AR2315_REV_MIN_S 0
845 +#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN)
846 +
847 +/*
848 + * Interface Enable
849 + */
850 +#define AR2315_IF_CTL (AR2315_DSLBASE + 0x0018)
851 +
852 +#define AR2315_IF_MASK 0x00000007
853 +#define AR2315_IF_DISABLED 0
854 +#define AR2315_IF_PCI 1
855 +#define AR2315_IF_TS_LOCAL 2
856 +/* only for emulation with separate pins */
857 +#define AR2315_IF_ALL 3
858 +#define AR2315_IF_LOCAL_HOST 0x00000008
859 +#define AR2315_IF_PCI_HOST 0x00000010
860 +#define AR2315_IF_PCI_INTR 0x00000020
861 +#define AR2315_IF_PCI_CLK_MASK 0x00030000
862 +#define AR2315_IF_PCI_CLK_INPUT 0
863 +#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
864 +#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
865 +#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
866 +#define AR2315_IF_PCI_CLK_SHIFT 16
867 +
868 +/*
869 + * APB Interrupt control
870 + */
871 +
872 +#define AR2315_ISR (AR2315_DSLBASE + 0x0020)
873 +#define AR2315_IMR (AR2315_DSLBASE + 0x0024)
874 +#define AR2315_GISR (AR2315_DSLBASE + 0x0028)
875 +
876 +#define AR2315_ISR_UART0 0x0001 /* high speed UART */
877 +#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */
878 +#define AR2315_ISR_SPI 0x0004 /* SPI bus */
879 +#define AR2315_ISR_AHB 0x0008 /* AHB error */
880 +#define AR2315_ISR_APB 0x0010 /* APB error */
881 +#define AR2315_ISR_TIMER 0x0020 /* timer */
882 +#define AR2315_ISR_GPIO 0x0040 /* GPIO */
883 +#define AR2315_ISR_WD 0x0080 /* watchdog */
884 +#define AR2315_ISR_IR_RSVD 0x0100 /* IR */
885 +
886 +#define AR2315_GISR_MISC 0x0001
887 +#define AR2315_GISR_WLAN0 0x0002
888 +#define AR2315_GISR_MPEGTS_RSVD 0x0004
889 +#define AR2315_GISR_LOCALPCI 0x0008
890 +#define AR2315_GISR_WMACPOLL 0x0010
891 +#define AR2315_GISR_TIMER 0x0020
892 +#define AR2315_GISR_ETHERNET 0x0040
893 +
894 +/*
895 + * Interrupt routing from IO to the processor IP bits
896 + * Define our inter mask and level
897 + */
898 +#define AR2315_INTR_MISCIO SR_IBIT3
899 +#define AR2315_INTR_WLAN0 SR_IBIT4
900 +#define AR2315_INTR_ENET0 SR_IBIT5
901 +#define AR2315_INTR_LOCALPCI SR_IBIT6
902 +#define AR2315_INTR_WMACPOLL SR_IBIT7
903 +#define AR2315_INTR_COMPARE SR_IBIT8
904 +
905 +/*
906 + * Timers
907 + */
908 +#define AR2315_TIMER (AR2315_DSLBASE + 0x0030)
909 +#define AR2315_RELOAD (AR2315_DSLBASE + 0x0034)
910 +#define AR2315_WD (AR2315_DSLBASE + 0x0038)
911 +#define AR2315_WDC (AR2315_DSLBASE + 0x003c)
912 +
913 +#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000
914 +#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */
915 +#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */
916 +
917 +/*
918 + * CPU Performance Counters
919 + */
920 +#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048)
921 +#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c)
922 +
923 +#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */
924 +#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */
925 +#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */
926 +#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */
927 +#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */
928 +#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */
929 +#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */
930 +
931 +#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */
932 +#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */
933 +#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */
934 +#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */
935 +#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */
936 +#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */
937 +#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */
938 +
939 +/*
940 + * AHB Error Reporting.
941 + */
942 +#define AR2315_AHB_ERR0 (AR2315_DSLBASE + 0x0050) /* error */
943 +#define AR2315_AHB_ERR1 (AR2315_DSLBASE + 0x0054) /* haddr */
944 +#define AR2315_AHB_ERR2 (AR2315_DSLBASE + 0x0058) /* hwdata */
945 +#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */
946 +#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */
947 +
948 +#define AHB_ERROR_DET 1 /* AHB Error has been detected, */
949 + /* write 1 to clear all bits in ERR0 */
950 +#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
951 +#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
952 +
953 +#define AR2315_PROCERR_HMAST 0x0000000f
954 +#define AR2315_PROCERR_HMAST_DFLT 0
955 +#define AR2315_PROCERR_HMAST_WMAC 1
956 +#define AR2315_PROCERR_HMAST_ENET 2
957 +#define AR2315_PROCERR_HMAST_PCIENDPT 3
958 +#define AR2315_PROCERR_HMAST_LOCAL 4
959 +#define AR2315_PROCERR_HMAST_CPU 5
960 +#define AR2315_PROCERR_HMAST_PCITGT 6
961 +
962 +#define AR2315_PROCERR_HMAST_S 0
963 +#define AR2315_PROCERR_HWRITE 0x00000010
964 +#define AR2315_PROCERR_HSIZE 0x00000060
965 +#define AR2315_PROCERR_HSIZE_S 5
966 +#define AR2315_PROCERR_HTRANS 0x00000180
967 +#define AR2315_PROCERR_HTRANS_S 7
968 +#define AR2315_PROCERR_HBURST 0x00000e00
969 +#define AR2315_PROCERR_HBURST_S 9
970 +
971 +/*
972 + * Clock Control
973 + */
974 +#define AR2315_PLLC_CTL (AR2315_DSLBASE + 0x0064)
975 +#define AR2315_PLLV_CTL (AR2315_DSLBASE + 0x0068)
976 +#define AR2315_CPUCLK (AR2315_DSLBASE + 0x006c)
977 +#define AR2315_AMBACLK (AR2315_DSLBASE + 0x0070)
978 +#define AR2315_SYNCCLK (AR2315_DSLBASE + 0x0074)
979 +#define AR2315_DSL_SLEEP_CTL (AR2315_DSLBASE + 0x0080)
980 +#define AR2315_DSL_SLEEP_DUR (AR2315_DSLBASE + 0x0084)
981 +
982 +/* PLLc Control fields */
983 +#define PLLC_REF_DIV_M 0x00000003
984 +#define PLLC_REF_DIV_S 0
985 +#define PLLC_FDBACK_DIV_M 0x0000007C
986 +#define PLLC_FDBACK_DIV_S 2
987 +#define PLLC_ADD_FDBACK_DIV_M 0x00000080
988 +#define PLLC_ADD_FDBACK_DIV_S 7
989 +#define PLLC_CLKC_DIV_M 0x0001c000
990 +#define PLLC_CLKC_DIV_S 14
991 +#define PLLC_CLKM_DIV_M 0x00700000
992 +#define PLLC_CLKM_DIV_S 20
993 +
994 +/* CPU CLK Control fields */
995 +#define CPUCLK_CLK_SEL_M 0x00000003
996 +#define CPUCLK_CLK_SEL_S 0
997 +#define CPUCLK_CLK_DIV_M 0x0000000c
998 +#define CPUCLK_CLK_DIV_S 2
999 +
1000 +/* AMBA CLK Control fields */
1001 +#define AMBACLK_CLK_SEL_M 0x00000003
1002 +#define AMBACLK_CLK_SEL_S 0
1003 +#define AMBACLK_CLK_DIV_M 0x0000000c
1004 +#define AMBACLK_CLK_DIV_S 2
1005 +
1006 +/*
1007 + * GPIO
1008 + */
1009 +#define AR2315_GPIO_DI (AR2315_DSLBASE + 0x0088)
1010 +#define AR2315_GPIO_DO (AR2315_DSLBASE + 0x0090)
1011 +#define AR2315_GPIO_DIR (AR2315_DSLBASE + 0x0098)
1012 +#define AR2315_GPIO_INT (AR2315_DSLBASE + 0x00a0)
1013 +
1014 +#define AR2315_GPIO_DIR_M(x) (1 << (x)) /* mask for i/o */
1015 +#define AR2315_GPIO_DIR_O(x) (1 << (x)) /* output */
1016 +#define AR2315_GPIO_DIR_I(x) (0) /* input */
1017 +
1018 +#define AR2315_GPIO_INT_S(x) (x) /* interrupt enable */
1019 +#define AR2315_GPIO_INT_M (0x3F) /* mask for int */
1020 +#define AR2315_GPIO_INT_LVL(x) ((x) << 6) /* interrupt level */
1021 +#define AR2315_GPIO_INT_LVL_M ((0x3) << 6) /* mask for int level */
1022 +
1023 +#define AR2315_GPIO_INT_MAX_Y 1 /* Maximum value of Y for
1024 + * AR2315_GPIO_INT_* macros */
1025 +#define AR2315_GPIO_INT_LVL_OFF 0 /* Triggerring off */
1026 +#define AR2315_GPIO_INT_LVL_LOW 1 /* Low Level Triggered */
1027 +#define AR2315_GPIO_INT_LVL_HIGH 2 /* High Level Triggered */
1028 +#define AR2315_GPIO_INT_LVL_EDGE 3 /* Edge Triggered */
1029 +
1030 +#define AR2315_RESET_GPIO 5
1031 +#define AR2315_NUM_GPIO 22
1032 +
1033 +/*
1034 + * PCI Clock Control
1035 + */
1036 +#define AR2315_PCICLK (AR2315_DSLBASE + 0x00a4)
1037 +
1038 +#define AR2315_PCICLK_INPUT_M 0x3
1039 +#define AR2315_PCICLK_INPUT_S 0
1040 +
1041 +#define AR2315_PCICLK_PLLC_CLKM 0
1042 +#define AR2315_PCICLK_PLLC_CLKM1 1
1043 +#define AR2315_PCICLK_PLLC_CLKC 2
1044 +#define AR2315_PCICLK_REF_CLK 3
1045 +
1046 +#define AR2315_PCICLK_DIV_M 0xc
1047 +#define AR2315_PCICLK_DIV_S 2
1048 +
1049 +#define AR2315_PCICLK_IN_FREQ 0
1050 +#define AR2315_PCICLK_IN_FREQ_DIV_6 1
1051 +#define AR2315_PCICLK_IN_FREQ_DIV_8 2
1052 +#define AR2315_PCICLK_IN_FREQ_DIV_10 3
1053 +
1054 +/*
1055 + * Observation Control Register
1056 + */
1057 +#define AR2315_OCR (AR2315_DSLBASE + 0x00b0)
1058 +#define OCR_GPIO0_IRIN 0x0040
1059 +#define OCR_GPIO1_IROUT 0x0080
1060 +#define OCR_GPIO3_RXCLR 0x0200
1061 +
1062 +/*
1063 + * General Clock Control
1064 + */
1065 +
1066 +#define AR2315_MISCCLK (AR2315_DSLBASE + 0x00b4)
1067 +#define MISCCLK_PLLBYPASS_EN 0x00000001
1068 +#define MISCCLK_PROCREFCLK 0x00000002
1069 +
1070 +/*
1071 + * SDRAM Controller
1072 + * - No read or write buffers are included.
1073 + */
1074 +#define AR2315_MEM_CFG (AR2315_SDRAMCTL + 0x00)
1075 +#define AR2315_MEM_CTRL (AR2315_SDRAMCTL + 0x0c)
1076 +#define AR2315_MEM_REF (AR2315_SDRAMCTL + 0x10)
1077 +
1078 +#define SDRAM_DATA_WIDTH_M 0x00006000
1079 +#define SDRAM_DATA_WIDTH_S 13
1080 +
1081 +#define SDRAM_COL_WIDTH_M 0x00001E00
1082 +#define SDRAM_COL_WIDTH_S 9
1083 +
1084 +#define SDRAM_ROW_WIDTH_M 0x000001E0
1085 +#define SDRAM_ROW_WIDTH_S 5
1086 +
1087 +#define SDRAM_BANKADDR_BITS_M 0x00000018
1088 +#define SDRAM_BANKADDR_BITS_S 3
1089 +
1090 +/*
1091 + * PCI Bus Interface Registers
1092 + */
1093 +#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008)
1094 +#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1095 +
1096 +#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c)
1097 +#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
1098 +#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* mem or config cycles */
1099 +#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
1100 +#define AR2315_PCIMISC_RST_MODE 0x00000030
1101 +#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
1102 +#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
1103 +#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
1104 +#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
1105 +#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
1106 +#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
1107 +#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
1108 +#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache
1109 + * disable */
1110 +
1111 +#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010)
1112 +
1113 +#define AR2315_PCI_UNCACHE_CFG (AR2315_PCI + 0x0014)
1114 +
1115 +#define AR2315_PCI_IN_EN (AR2315_PCI + 0x0100)
1116 +#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
1117 +#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
1118 +#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
1119 +#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
1120 +
1121 +#define AR2315_PCI_IN_DIS (AR2315_PCI + 0x0104)
1122 +#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
1123 +#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
1124 +#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
1125 +#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
1126 +
1127 +#define AR2315_PCI_IN_PTR (AR2315_PCI + 0x0200)
1128 +
1129 +#define AR2315_PCI_OUT_EN (AR2315_PCI + 0x0400)
1130 +#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
1131 +
1132 +#define AR2315_PCI_OUT_DIS (AR2315_PCI + 0x0404)
1133 +#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
1134 +
1135 +#define AR2315_PCI_OUT_PTR (AR2315_PCI + 0x0408)
1136 +
1137 +#define AR2315_PCI_ISR (AR2315_PCI + 0x0500) /* write one to clr */
1138 +#define AR2315_PCI_INT_TX 0x00000001 /* Desc In Completed */
1139 +#define AR2315_PCI_INT_TXOK 0x00000002 /* Desc In OK */
1140 +#define AR2315_PCI_INT_TXERR 0x00000004 /* Desc In ERR */
1141 +#define AR2315_PCI_INT_TXEOL 0x00000008 /* Desc In End-of-List */
1142 +#define AR2315_PCI_INT_RX 0x00000010 /* Desc Out Completed */
1143 +#define AR2315_PCI_INT_RXOK 0x00000020 /* Desc Out OK */
1144 +#define AR2315_PCI_INT_RXERR 0x00000040 /* Desc Out ERR */
1145 +#define AR2315_PCI_INT_RXEOL 0x00000080 /* Desc Out EOL */
1146 +#define AR2315_PCI_INT_TXOOD 0x00000200 /* Desc In Out-of-Desc */
1147 +#define AR2315_PCI_INT_DESCMASK 0x0000FFFF /* Desc Mask */
1148 +#define AR2315_PCI_INT_EXT 0x02000000 /* Extern PCI INTA */
1149 +#define AR2315_PCI_INT_ABORT 0x04000000 /* PCI bus abort event */
1150 +
1151 +#define AR2315_PCI_IMR (AR2315_PCI + 0x0504) /* mask _PCI_ISR bits */
1152 +
1153 +#define AR2315_PCI_IER (AR2315_PCI + 0x0508) /* global PCI int en */
1154 +#define AR2315_PCI_IER_DISABLE 0x00 /* disable pci interrupts */
1155 +#define AR2315_PCI_IER_ENABLE 0x01 /* enable pci interrupts */
1156 +
1157 +#define AR2315_PCI_HOST_IN_EN (AR2315_PCI + 0x0800)
1158 +#define AR2315_PCI_HOST_IN_DIS (AR2315_PCI + 0x0804)
1159 +#define AR2315_PCI_HOST_IN_PTR (AR2315_PCI + 0x0810)
1160 +#define AR2315_PCI_HOST_OUT_EN (AR2315_PCI + 0x0900)
1161 +#define AR2315_PCI_HOST_OUT_DIS (AR2315_PCI + 0x0904)
1162 +#define AR2315_PCI_HOST_OUT_PTR (AR2315_PCI + 0x0908)
1163 +
1164 +/*
1165 + * Local Bus Interface Registers
1166 + */
1167 +#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000)
1168 +#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
1169 +#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
1170 +#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
1171 +#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
1172 +#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
1173 +#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
1174 +#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
1175 +#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
1176 +#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
1177 +#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
1178 +#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
1179 +#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
1180 +#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
1181 +#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
1182 +#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
1183 +#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
1184 +#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
1185 +#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
1186 +#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
1187 +#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
1188 +#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
1189 +#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */
1190 +#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
1191 +#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
1192 +#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
1193 +
1194 +#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004)
1195 +#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */
1196 +
1197 +#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008)
1198 +#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1199 +
1200 +#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C)
1201 +#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
1202 +#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
1203 +#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
1204 +#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
1205 +#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
1206 +#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80
1207 +#define AR2315_LBM_TIMEOUT_SHFT 7
1208 +#define AR2315_LBM_PORTMUX 0x07000000
1209 +
1210 +#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010)
1211 +
1212 +#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100)
1213 +#define AR2315_LB_TXEN_0 0x01
1214 +#define AR2315_LB_TXEN_1 0x02
1215 +#define AR2315_LB_TXEN_2 0x04
1216 +#define AR2315_LB_TXEN_3 0x08
1217 +
1218 +#define AR2315_LB_TX_CHAIN_DIS (AR2315_LOCAL + 0x0104)
1219 +#define AR2315_LB_TX_DESC_PTR (AR2315_LOCAL + 0x0200)
1220 +
1221 +#define AR2315_LB_RX_CHAIN_EN (AR2315_LOCAL + 0x0400)
1222 +#define AR2315_LB_RXEN 0x01
1223 +
1224 +#define AR2315_LB_RX_CHAIN_DIS (AR2315_LOCAL + 0x0404)
1225 +#define AR2315_LB_RX_DESC_PTR (AR2315_LOCAL + 0x0408)
1226 +
1227 +#define AR2315_LB_INT_STATUS (AR2315_LOCAL + 0x0500)
1228 +#define AR2315_INT_TX_DESC 0x0001
1229 +#define AR2315_INT_TX_OK 0x0002
1230 +#define AR2315_INT_TX_ERR 0x0004
1231 +#define AR2315_INT_TX_EOF 0x0008
1232 +#define AR2315_INT_RX_DESC 0x0010
1233 +#define AR2315_INT_RX_OK 0x0020
1234 +#define AR2315_INT_RX_ERR 0x0040
1235 +#define AR2315_INT_RX_EOF 0x0080
1236 +#define AR2315_INT_TX_TRUNC 0x0100
1237 +#define AR2315_INT_TX_STARVE 0x0200
1238 +#define AR2315_INT_LB_TIMEOUT 0x0400
1239 +#define AR2315_INT_LB_ERR 0x0800
1240 +#define AR2315_INT_MBOX_WR 0x1000
1241 +#define AR2315_INT_MBOX_RD 0x2000
1242 +
1243 +/* Bit definitions for INT MASK are the same as INT_STATUS */
1244 +#define AR2315_LB_INT_MASK (AR2315_LOCAL + 0x0504)
1245 +
1246 +#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508)
1247 +#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600)
1248 +
1249 +/*
1250 + * IR Interface Registers
1251 + */
1252 +#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000)
1253 +
1254 +#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */
1255 +
1256 +#define AR2315_IR_CONTROL (AR2315_IR + 0x0800)
1257 +#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */
1258 +#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */
1259 +#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor */
1260 +#define AR2315_IRCTL_SAMPLECLK_SHFT 1
1261 +#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk div */
1262 +#define AR2315_IRCTL_OUTPUTCLK_SHFT 14
1263 +
1264 +#define AR2315_IR_STATUS (AR2315_IR + 0x0804)
1265 +#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */
1266 +#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */
1267 +
1268 +#define AR2315_IR_CONFIG (AR2315_IR + 0x0808)
1269 +#define AR2315_IRCFG_INVIN 0x00000001 /* invert in polarity */
1270 +#define AR2315_IRCFG_INVOUT 0x00000002 /* invert out polarity */
1271 +#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */
1272 +#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0
1273 +#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100
1274 +#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00
1275 +#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000
1276 +#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000
1277 +#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000
1278 +
1279 +/*
1280 + * We need some arbitrary non-zero value to be programmed to the BAR1 register
1281 + * of PCI host controller to enable DMA. The same value should be used as the
1282 + * offset to calculate the physical address of DMA buffer for PCI devices.
1283 + */
1284 +#define AR2315_PCI_HOST_SDRAM_BASEADDR 0x20000000
1285 +
1286 +/* ??? access BAR */
1287 +#define AR2315_PCI_HOST_MBAR0 0x10000000
1288 +/* RAM access BAR */
1289 +#define AR2315_PCI_HOST_MBAR1 AR2315_PCI_HOST_SDRAM_BASEADDR
1290 +/* ??? access BAR */
1291 +#define AR2315_PCI_HOST_MBAR2 0x30000000
1292 +
1293 +#endif /* __ASM_MACH_AR231X_AR2315_REGS_H */
1294 --- /dev/null
1295 +++ b/arch/mips/include/asm/mach-ar231x/ar5312_regs.h
1296 @@ -0,0 +1,249 @@
1297 +/*
1298 + * This file is subject to the terms and conditions of the GNU General Public
1299 + * License. See the file "COPYING" in the main directory of this archive
1300 + * for more details.
1301 + *
1302 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1303 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1304 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1305 + */
1306 +
1307 +#ifndef __ASM_MACH_AR231X_AR5312_REGS_H
1308 +#define __ASM_MACH_AR231X_AR5312_REGS_H
1309 +
1310 +#include <asm/addrspace.h>
1311 +
1312 +/*
1313 + * IRQs
1314 + */
1315 +#define AR5312_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
1316 +#define AR5312_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
1317 +#define AR5312_IRQ_ENET1_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
1318 +#define AR5312_IRQ_WLAN1_INTRS (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
1319 +#define AR5312_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
1320 +
1321 +/*
1322 + * Miscellaneous interrupts, which share IP6.
1323 + */
1324 +#define AR5312_MISC_IRQ_NONE (AR231X_MISC_IRQ_BASE+0)
1325 +#define AR5312_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+1)
1326 +#define AR5312_MISC_IRQ_AHB_PROC (AR231X_MISC_IRQ_BASE+2)
1327 +#define AR5312_MISC_IRQ_AHB_DMA (AR231X_MISC_IRQ_BASE+3)
1328 +#define AR5312_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+4)
1329 +#define AR5312_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+5)
1330 +#define AR5312_MISC_IRQ_UART0_DMA (AR231X_MISC_IRQ_BASE+6)
1331 +#define AR5312_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+7)
1332 +#define AR5312_MISC_IRQ_LOCAL (AR231X_MISC_IRQ_BASE+8)
1333 +#define AR5312_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+9)
1334 +#define AR5312_MISC_IRQ_COUNT 10
1335 +
1336 +/*
1337 + * Address Map
1338 + */
1339 +#define AR5312_WLAN0 0x18000000
1340 +#define AR5312_WLAN1 0x18500000
1341 +#define AR5312_ENET0 0x18100000
1342 +#define AR5312_ENET1 0x18200000
1343 +#define AR5312_SDRAMCTL 0x18300000
1344 +#define AR5312_FLASHCTL 0x18400000
1345 +#define AR5312_APBBASE 0x1c000000
1346 +#define AR5312_UART0 0x1c000000 /* UART MMR */
1347 +#define AR5312_FLASH 0x1e000000
1348 +
1349 +/*
1350 + * AR5312_NUM_ENET_MAC defines the number of ethernet MACs that
1351 + * should be considered available. The AR5312 supports 2 enet MACS,
1352 + * even though many reference boards only actually use 1 of them
1353 + * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch.
1354 + * The AR2312 supports 1 enet MAC.
1355 + */
1356 +#define AR5312_NUM_ENET_MAC 2
1357 +
1358 +/*
1359 + * Need these defines to determine true number of ethernet MACs
1360 + */
1361 +#define AR5312_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
1362 +#define AR5312_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
1363 +#define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
1364 +
1365 +/* MII registers offset inside Ethernet MMR region */
1366 +#define AR5312_ENET0_MII (AR5312_ENET0 + 0x14)
1367 +#define AR5312_ENET1_MII (AR5312_ENET1 + 0x14)
1368 +
1369 +/*
1370 + * AR5312_NUM_WMAC defines the number of Wireless MACs that\
1371 + * should be considered available.
1372 + */
1373 +#define AR5312_NUM_WMAC 2
1374 +
1375 +/* Reset/Timer Block Address Map */
1376 +#define AR5312_RESETTMR (AR5312_APBBASE + 0x3000)
1377 +#define AR5312_TIMER (AR5312_RESETTMR + 0x0000) /* countdown timer */
1378 +#define AR5312_WD_CTRL (AR5312_RESETTMR + 0x0008) /* watchdog cntrl */
1379 +#define AR5312_WD_TIMER (AR5312_RESETTMR + 0x000c) /* watchdog timer */
1380 +#define AR5312_ISR (AR5312_RESETTMR + 0x0010) /* Intr Status Reg */
1381 +#define AR5312_IMR (AR5312_RESETTMR + 0x0014) /* Intr Mask Reg */
1382 +#define AR5312_RESET (AR5312_RESETTMR + 0x0020)
1383 +#define AR5312_CLOCKCTL1 (AR5312_RESETTMR + 0x0064)
1384 +#define AR5312_SCRATCH (AR5312_RESETTMR + 0x006c)
1385 +#define AR5312_PROCADDR (AR5312_RESETTMR + 0x0070)
1386 +#define AR5312_PROC1 (AR5312_RESETTMR + 0x0074)
1387 +#define AR5312_DMAADDR (AR5312_RESETTMR + 0x0078)
1388 +#define AR5312_DMA1 (AR5312_RESETTMR + 0x007c)
1389 +#define AR5312_ENABLE (AR5312_RESETTMR + 0x0080) /* interface enb */
1390 +#define AR5312_REV (AR5312_RESETTMR + 0x0090) /* revision */
1391 +
1392 +/* AR5312_WD_CTRL register bit field definitions */
1393 +#define AR5312_WD_CTRL_IGNORE_EXPIRATION 0x0000
1394 +#define AR5312_WD_CTRL_NMI 0x0001
1395 +#define AR5312_WD_CTRL_RESET 0x0002
1396 +
1397 +/* AR5312_ISR register bit field definitions */
1398 +#define AR5312_ISR_NONE 0x0000
1399 +#define AR5312_ISR_TIMER 0x0001
1400 +#define AR5312_ISR_AHBPROC 0x0002
1401 +#define AR5312_ISR_AHBDMA 0x0004
1402 +#define AR5312_ISR_GPIO 0x0008
1403 +#define AR5312_ISR_UART0 0x0010
1404 +#define AR5312_ISR_UART0DMA 0x0020
1405 +#define AR5312_ISR_WD 0x0040
1406 +#define AR5312_ISR_LOCAL 0x0080
1407 +
1408 +/* AR5312_RESET register bit field definitions */
1409 +#define AR5312_RESET_SYSTEM 0x00000001 /* cold reset full system */
1410 +#define AR5312_RESET_PROC 0x00000002 /* cold reset MIPS core */
1411 +#define AR5312_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
1412 +#define AR5312_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
1413 +#define AR5312_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
1414 +#define AR5312_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
1415 +#define AR5312_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
1416 +#define AR5312_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */
1417 +#define AR5312_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
1418 +#define AR5312_RESET_APB 0x00000400 /* cold reset APB (ar5312) */
1419 +#define AR5312_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
1420 +#define AR5312_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
1421 +#define AR5312_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */
1422 +#define AR5312_RESET_NMI 0x00010000 /* send an NMI to the processor */
1423 +#define AR5312_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */
1424 +#define AR5312_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */
1425 +#define AR5312_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
1426 +#define AR5312_RESET_WDOG 0x00100000 /* last reset was a watchdog */
1427 +
1428 +#define AR5312_RESET_WMAC0_BITS \
1429 + (AR5312_RESET_WLAN0 |\
1430 + AR5312_RESET_WARM_WLAN0_MAC |\
1431 + AR5312_RESET_WARM_WLAN0_BB)
1432 +
1433 +#define AR5312_RESET_WMAC1_BITS \
1434 + (AR5312_RESET_WLAN1 |\
1435 + AR5312_RESET_WARM_WLAN1_MAC |\
1436 + AR5312_RESET_WARM_WLAN1_BB)
1437 +
1438 +/* AR5312_CLOCKCTL1 register bit field definitions */
1439 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1440 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1441 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1442 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1443 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1444 +
1445 +/* Valid for AR5312 and AR2312 */
1446 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1447 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1448 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1449 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1450 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1451 +
1452 +/* Valid for AR2313 */
1453 +#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
1454 +#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
1455 +#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
1456 +#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
1457 +#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
1458 +
1459 +/* AR5312_ENABLE register bit field definitions */
1460 +#define AR5312_ENABLE_WLAN0 0x0001
1461 +#define AR5312_ENABLE_ENET0 0x0002
1462 +#define AR5312_ENABLE_ENET1 0x0004
1463 +#define AR5312_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */
1464 +#define AR5312_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */
1465 +#define AR5312_ENABLE_WLAN1 \
1466 + (AR5312_ENABLE_UART_AND_WLAN1_PIO |\
1467 + AR5312_ENABLE_WLAN1_DMA)
1468 +
1469 +/* AR5312_REV register bit field definitions */
1470 +#define AR5312_REV_WMAC_MAJ 0xf000
1471 +#define AR5312_REV_WMAC_MAJ_S 12
1472 +#define AR5312_REV_WMAC_MIN 0x0f00
1473 +#define AR5312_REV_WMAC_MIN_S 8
1474 +#define AR5312_REV_MAJ 0x00f0
1475 +#define AR5312_REV_MAJ_S 4
1476 +#define AR5312_REV_MIN 0x000f
1477 +#define AR5312_REV_MIN_S 0
1478 +#define AR5312_REV_CHIP (AR5312_REV_MAJ|AR5312_REV_MIN)
1479 +
1480 +/* Major revision numbers, bits 7..4 of Revision ID register */
1481 +#define AR5312_REV_MAJ_AR5312 0x4
1482 +#define AR5312_REV_MAJ_AR2313 0x5
1483 +
1484 +/* Minor revision numbers, bits 3..0 of Revision ID register */
1485 +#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
1486 +#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
1487 +
1488 +/* AR5312_FLASHCTL register bit field definitions */
1489 +#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */
1490 +#define FLASHCTL_IDCY_S 0
1491 +#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
1492 +#define FLASHCTL_WST1_S 5
1493 +#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
1494 +#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
1495 +#define FLASHCTL_WST2_S 11
1496 +#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */
1497 +#define FLASHCTL_AC_S 16
1498 +#define FLASHCTL_AC_128K 0x00000000
1499 +#define FLASHCTL_AC_256K 0x00010000
1500 +#define FLASHCTL_AC_512K 0x00020000
1501 +#define FLASHCTL_AC_1M 0x00030000
1502 +#define FLASHCTL_AC_2M 0x00040000
1503 +#define FLASHCTL_AC_4M 0x00050000
1504 +#define FLASHCTL_AC_8M 0x00060000
1505 +#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
1506 +#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
1507 +#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */
1508 +#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */
1509 +#define FLASHCTL_WP 0x04000000 /* Write protect */
1510 +#define FLASHCTL_BM 0x08000000 /* Burst mode */
1511 +#define FLASHCTL_MW 0x30000000 /* Memory width */
1512 +#define FLASHCTL_MW8 0x00000000 /* Memory width x8 */
1513 +#define FLASHCTL_MW16 0x10000000 /* Memory width x16 */
1514 +#define FLASHCTL_MW32 0x20000000 /* Memory width x32 (not supported) */
1515 +#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */
1516 +#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */
1517 +#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */
1518 +
1519 +/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
1520 +#define AR5312_FLASHCTL0 (AR5312_FLASHCTL + 0x00)
1521 +#define AR5312_FLASHCTL1 (AR5312_FLASHCTL + 0x04)
1522 +#define AR5312_FLASHCTL2 (AR5312_FLASHCTL + 0x08)
1523 +
1524 +/* ARM SDRAM Controller -- just enough to determine memory size */
1525 +#define AR5312_MEM_CFG1 (AR5312_SDRAMCTL + 0x04)
1526 +#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */
1527 +#define MEM_CFG1_AC0_S 8
1528 +#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */
1529 +#define MEM_CFG1_AC1_S 12
1530 +
1531 +/* GPIO Address Map */
1532 +#define AR5312_GPIO (AR5312_APBBASE + 0x2000)
1533 +#define AR5312_GPIO_DO (AR5312_GPIO + 0x00) /* output register */
1534 +#define AR5312_GPIO_DI (AR5312_GPIO + 0x04) /* intput register */
1535 +#define AR5312_GPIO_CR (AR5312_GPIO + 0x08) /* control register */
1536 +
1537 +/* GPIO Control Register bit field definitions */
1538 +#define AR5312_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
1539 +#define AR5312_GPIO_CR_O(x) (0 << (x)) /* mask for output */
1540 +#define AR5312_GPIO_CR_I(x) (1 << (x)) /* mask for input */
1541 +#define AR5312_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt*/
1542 +#define AR5312_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */
1543 +#define AR5312_NUM_GPIO 8
1544 +
1545 +#endif /* __ASM_MACH_AR231X_AR5312_REGS_H */
1546 --- /dev/null
1547 +++ b/arch/mips/ar231x/ar5312.c
1548 @@ -0,0 +1,534 @@
1549 +/*
1550 + * This file is subject to the terms and conditions of the GNU General Public
1551 + * License. See the file "COPYING" in the main directory of this archive
1552 + * for more details.
1553 + *
1554 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1555 + * Copyright (C) 2006 FON Technology, SL.
1556 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1557 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1558 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1559 + */
1560 +
1561 +/*
1562 + * Platform devices for Atheros SoCs
1563 + */
1564 +
1565 +#include <generated/autoconf.h>
1566 +#include <linux/init.h>
1567 +#include <linux/module.h>
1568 +#include <linux/types.h>
1569 +#include <linux/string.h>
1570 +#include <linux/mtd/physmap.h>
1571 +#include <linux/platform_device.h>
1572 +#include <linux/kernel.h>
1573 +#include <linux/reboot.h>
1574 +#include <linux/leds.h>
1575 +#include <linux/gpio.h>
1576 +#include <asm/bootinfo.h>
1577 +#include <asm/reboot.h>
1578 +#include <asm/time.h>
1579 +#include <linux/irq.h>
1580 +#include <linux/io.h>
1581 +
1582 +#include <ar231x_platform.h>
1583 +#include <ar5312_regs.h>
1584 +#include <ar231x.h>
1585 +#include "devices.h"
1586 +#include "ar5312.h"
1587 +
1588 +static void ar5312_misc_irq_handler(unsigned irq, struct irq_desc *desc)
1589 +{
1590 + unsigned int ar231x_misc_intrs = ar231x_read_reg(AR5312_ISR) &
1591 + ar231x_read_reg(AR5312_IMR);
1592 +
1593 + if (ar231x_misc_intrs & AR5312_ISR_TIMER) {
1594 + do_IRQ(AR5312_MISC_IRQ_TIMER);
1595 + (void)ar231x_read_reg(AR5312_TIMER);
1596 + } else if (ar231x_misc_intrs & AR5312_ISR_AHBPROC)
1597 + do_IRQ(AR5312_MISC_IRQ_AHB_PROC);
1598 + else if ((ar231x_misc_intrs & AR5312_ISR_UART0))
1599 + do_IRQ(AR5312_MISC_IRQ_UART0);
1600 + else if (ar231x_misc_intrs & AR5312_ISR_WD)
1601 + do_IRQ(AR5312_MISC_IRQ_WATCHDOG);
1602 + else
1603 + do_IRQ(AR5312_MISC_IRQ_NONE);
1604 +}
1605 +
1606 +static asmlinkage void
1607 +ar5312_irq_dispatch(void)
1608 +{
1609 + int pending = read_c0_status() & read_c0_cause();
1610 +
1611 + if (pending & CAUSEF_IP2)
1612 + do_IRQ(AR5312_IRQ_WLAN0_INTRS);
1613 + else if (pending & CAUSEF_IP3)
1614 + do_IRQ(AR5312_IRQ_ENET0_INTRS);
1615 + else if (pending & CAUSEF_IP4)
1616 + do_IRQ(AR5312_IRQ_ENET1_INTRS);
1617 + else if (pending & CAUSEF_IP5)
1618 + do_IRQ(AR5312_IRQ_WLAN1_INTRS);
1619 + else if (pending & CAUSEF_IP6)
1620 + do_IRQ(AR5312_IRQ_MISC_INTRS);
1621 + else if (pending & CAUSEF_IP7)
1622 + do_IRQ(AR231X_IRQ_CPU_CLOCK);
1623 +}
1624 +
1625 +/* Enable the specified AR5312_MISC_IRQ interrupt */
1626 +static void
1627 +ar5312_misc_irq_unmask(struct irq_data *d)
1628 +{
1629 + unsigned int imr;
1630 +
1631 + imr = ar231x_read_reg(AR5312_IMR);
1632 + imr |= (1 << (d->irq - AR231X_MISC_IRQ_BASE - 1));
1633 + ar231x_write_reg(AR5312_IMR, imr);
1634 +}
1635 +
1636 +/* Disable the specified AR5312_MISC_IRQ interrupt */
1637 +static void
1638 +ar5312_misc_irq_mask(struct irq_data *d)
1639 +{
1640 + unsigned int imr;
1641 +
1642 + imr = ar231x_read_reg(AR5312_IMR);
1643 + imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE - 1));
1644 + ar231x_write_reg(AR5312_IMR, imr);
1645 + ar231x_read_reg(AR5312_IMR); /* flush write buffer */
1646 +}
1647 +
1648 +static struct irq_chip ar5312_misc_irq_chip = {
1649 + .name = "AR5312-MISC",
1650 + .irq_unmask = ar5312_misc_irq_unmask,
1651 + .irq_mask = ar5312_misc_irq_mask,
1652 +};
1653 +
1654 +static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id)
1655 +{
1656 + u32 proc1 = ar231x_read_reg(AR5312_PROC1);
1657 + u32 proc_addr = ar231x_read_reg(AR5312_PROCADDR); /* clears error */
1658 + u32 dma1 = ar231x_read_reg(AR5312_DMA1);
1659 + u32 dma_addr = ar231x_read_reg(AR5312_DMAADDR); /* clears error */
1660 +
1661 + pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
1662 + proc_addr, proc1, dma_addr, dma1);
1663 +
1664 + machine_restart("AHB error"); /* Catastrophic failure */
1665 + return IRQ_HANDLED;
1666 +}
1667 +
1668 +static struct irqaction ar5312_ahb_proc_interrupt = {
1669 + .handler = ar5312_ahb_proc_handler,
1670 + .name = "ar5312_ahb_proc_interrupt",
1671 +};
1672 +
1673 +void __init ar5312_irq_init(void)
1674 +{
1675 + int i;
1676 +
1677 + if (!is_5312())
1678 + return;
1679 +
1680 + ar231x_irq_dispatch = ar5312_irq_dispatch;
1681 + for (i = 0; i < AR5312_MISC_IRQ_COUNT; i++) {
1682 + int irq = AR231X_MISC_IRQ_BASE + i;
1683 +
1684 + irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip,
1685 + handle_level_irq);
1686 + }
1687 + setup_irq(AR5312_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt);
1688 + irq_set_chained_handler(AR5312_IRQ_MISC_INTRS, ar5312_misc_irq_handler);
1689 +}
1690 +
1691 +/*
1692 + * gpiolib implementations
1693 + */
1694 +static int
1695 +ar5312_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
1696 +{
1697 + return (ar231x_read_reg(AR5312_GPIO_DI) >> gpio) & 1;
1698 +}
1699 +
1700 +static void
1701 +ar5312_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
1702 +{
1703 + u32 reg = ar231x_read_reg(AR5312_GPIO_DO);
1704 +
1705 + reg = value ? reg | (1 << gpio) : reg & ~(1 << gpio);
1706 + ar231x_write_reg(AR5312_GPIO_DO, reg);
1707 +}
1708 +
1709 +static int
1710 +ar5312_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
1711 +{
1712 + ar231x_mask_reg(AR5312_GPIO_CR, 0, 1 << gpio);
1713 + return 0;
1714 +}
1715 +
1716 +static int
1717 +ar5312_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
1718 +{
1719 + ar231x_mask_reg(AR5312_GPIO_CR, 1 << gpio, 0);
1720 + ar5312_gpio_set_value(chip, gpio, value);
1721 + return 0;
1722 +}
1723 +
1724 +static struct gpio_chip ar5312_gpio_chip = {
1725 + .label = "ar5312-gpio",
1726 + .direction_input = ar5312_gpio_direction_input,
1727 + .direction_output = ar5312_gpio_direction_output,
1728 + .set = ar5312_gpio_set_value,
1729 + .get = ar5312_gpio_get_value,
1730 + .base = 0,
1731 + .ngpio = AR5312_NUM_GPIO, /* 8 */
1732 +};
1733 +
1734 +/* end of gpiolib */
1735 +
1736 +static void ar5312_device_reset_set(u32 mask)
1737 +{
1738 + u32 val;
1739 +
1740 + val = ar231x_read_reg(AR5312_RESET);
1741 + ar231x_write_reg(AR5312_RESET, val | mask);
1742 +}
1743 +
1744 +static void ar5312_device_reset_clear(u32 mask)
1745 +{
1746 + u32 val;
1747 +
1748 + val = ar231x_read_reg(AR5312_RESET);
1749 + ar231x_write_reg(AR5312_RESET, val & ~mask);
1750 +}
1751 +
1752 +static struct physmap_flash_data ar5312_flash_data = {
1753 + .width = 2,
1754 +};
1755 +
1756 +static struct resource ar5312_flash_resource = {
1757 + .start = AR5312_FLASH,
1758 + .end = AR5312_FLASH + 0x800000 - 1,
1759 + .flags = IORESOURCE_MEM,
1760 +};
1761 +
1762 +static struct ar231x_eth ar5312_eth0_data = {
1763 + .reset_set = ar5312_device_reset_set,
1764 + .reset_clear = ar5312_device_reset_clear,
1765 + .reset_mac = AR5312_RESET_ENET0,
1766 + .reset_phy = AR5312_RESET_EPHY0,
1767 + .config = &ar231x_board,
1768 +};
1769 +
1770 +static struct ar231x_eth ar5312_eth1_data = {
1771 + .reset_set = ar5312_device_reset_set,
1772 + .reset_clear = ar5312_device_reset_clear,
1773 + .reset_mac = AR5312_RESET_ENET1,
1774 + .reset_phy = AR5312_RESET_EPHY1,
1775 + .config = &ar231x_board,
1776 +};
1777 +
1778 +static struct platform_device ar5312_physmap_flash = {
1779 + .name = "physmap-flash",
1780 + .id = 0,
1781 + .dev.platform_data = &ar5312_flash_data,
1782 + .resource = &ar5312_flash_resource,
1783 + .num_resources = 1,
1784 +};
1785 +
1786 +#ifdef CONFIG_LEDS_GPIO
1787 +static struct gpio_led ar5312_leds[] = {
1788 + { .name = "wlan", .gpio = 0, .active_low = 1, },
1789 +};
1790 +
1791 +static const struct gpio_led_platform_data ar5312_led_data = {
1792 + .num_leds = ARRAY_SIZE(ar5312_leds),
1793 + .leds = (void *)ar5312_leds,
1794 +};
1795 +
1796 +static struct platform_device ar5312_gpio_leds = {
1797 + .name = "leds-gpio",
1798 + .id = -1,
1799 + .dev.platform_data = (void *)&ar5312_led_data,
1800 +};
1801 +#endif
1802 +
1803 +/*
1804 + * NB: This mapping size is larger than the actual flash size,
1805 + * but this shouldn't be a problem here, because the flash
1806 + * will simply be mapped multiple times.
1807 + */
1808 +static char __init *ar5312_flash_limit(void)
1809 +{
1810 + u32 ctl;
1811 + /*
1812 + * Configure flash bank 0.
1813 + * Assume 8M window size. Flash will be aliased if it's smaller
1814 + */
1815 + ctl = FLASHCTL_E |
1816 + FLASHCTL_AC_8M |
1817 + FLASHCTL_RBLE |
1818 + (0x01 << FLASHCTL_IDCY_S) |
1819 + (0x07 << FLASHCTL_WST1_S) |
1820 + (0x07 << FLASHCTL_WST2_S) |
1821 + (ar231x_read_reg(AR5312_FLASHCTL0) & FLASHCTL_MW);
1822 +
1823 + ar231x_write_reg(AR5312_FLASHCTL0, ctl);
1824 +
1825 + /* Disable other flash banks */
1826 + ar231x_write_reg(AR5312_FLASHCTL1,
1827 + ar231x_read_reg(AR5312_FLASHCTL1) &
1828 + ~(FLASHCTL_E | FLASHCTL_AC));
1829 +
1830 + ar231x_write_reg(AR5312_FLASHCTL2,
1831 + ar231x_read_reg(AR5312_FLASHCTL2) &
1832 + ~(FLASHCTL_E | FLASHCTL_AC));
1833 +
1834 + return (char *)KSEG1ADDR(AR5312_FLASH + 0x800000);
1835 +}
1836 +
1837 +int __init ar5312_init_devices(void)
1838 +{
1839 + struct ar231x_boarddata *config;
1840 + u32 fctl = 0;
1841 + u8 *c;
1842 +
1843 + if (!is_5312())
1844 + return 0;
1845 +
1846 + /* Locate board/radio config data */
1847 + ar231x_find_config(ar5312_flash_limit());
1848 + config = ar231x_board.config;
1849 +
1850 + /* AR2313 has CPU minor rev. 10 */
1851 + if ((current_cpu_data.processor_id & 0xff) == 0x0a)
1852 + ar231x_devtype = DEV_TYPE_AR2313;
1853 +
1854 + /* AR2312 shares the same Silicon ID as AR5312 */
1855 + else if (config->flags & BD_ISCASPER)
1856 + ar231x_devtype = DEV_TYPE_AR2312;
1857 +
1858 + /* Everything else is probably AR5312 or compatible */
1859 + else
1860 + ar231x_devtype = DEV_TYPE_AR5312;
1861 +
1862 + /* fixup flash width */
1863 + fctl = ar231x_read_reg(AR5312_FLASHCTL) & FLASHCTL_MW;
1864 + switch (fctl) {
1865 + case FLASHCTL_MW16:
1866 + ar5312_flash_data.width = 2;
1867 + break;
1868 + case FLASHCTL_MW8:
1869 + default:
1870 + ar5312_flash_data.width = 1;
1871 + break;
1872 + }
1873 +
1874 + platform_device_register(&ar5312_physmap_flash);
1875 +
1876 +#ifdef CONFIG_LEDS_GPIO
1877 + ar5312_leds[0].gpio = config->sys_led_gpio;
1878 + platform_device_register(&ar5312_gpio_leds);
1879 +#endif
1880 +
1881 + /* Fix up MAC addresses if necessary */
1882 + if (is_broadcast_ether_addr(config->enet0_mac))
1883 + ether_addr_copy(config->enet0_mac, config->enet1_mac);
1884 +
1885 + /* If ENET0 and ENET1 have the same mac address,
1886 + * increment the one from ENET1 */
1887 + if (ether_addr_equal(config->enet0_mac, config->enet1_mac)) {
1888 + c = config->enet1_mac + 5;
1889 + while ((c >= config->enet1_mac) && !(++(*c)))
1890 + c--;
1891 + }
1892 +
1893 + switch (ar231x_devtype) {
1894 + case DEV_TYPE_AR5312:
1895 + ar5312_eth0_data.macaddr = config->enet0_mac;
1896 + ar231x_add_ethernet(0, AR5312_ENET0, "eth0_mii",
1897 + AR5312_ENET0_MII, AR5312_IRQ_ENET0_INTRS,
1898 + &ar5312_eth0_data);
1899 +
1900 + ar5312_eth1_data.macaddr = config->enet1_mac;
1901 + ar231x_add_ethernet(1, AR5312_ENET1, "eth1_mii",
1902 + AR5312_ENET1_MII, AR5312_IRQ_ENET1_INTRS,
1903 + &ar5312_eth1_data);
1904 +
1905 + if (!ar231x_board.radio)
1906 + return 0;
1907 +
1908 + if (!(config->flags & BD_WLAN0))
1909 + break;
1910 +
1911 + ar231x_add_wmac(0, AR5312_WLAN0, AR5312_IRQ_WLAN0_INTRS);
1912 + break;
1913 + /*
1914 + * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
1915 + * of ENET1. Atheros calls it 'twisted' for a reason :)
1916 + */
1917 + case DEV_TYPE_AR2312:
1918 + case DEV_TYPE_AR2313:
1919 + ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
1920 + ar5312_eth1_data.macaddr = config->enet0_mac;
1921 + ar231x_add_ethernet(1, AR5312_ENET1, "eth0_mii",
1922 + AR5312_ENET0_MII, AR5312_IRQ_ENET1_INTRS,
1923 + &ar5312_eth1_data);
1924 +
1925 + if (!ar231x_board.radio)
1926 + return 0;
1927 + break;
1928 + default:
1929 + break;
1930 + }
1931 +
1932 + if (config->flags & BD_WLAN1)
1933 + ar231x_add_wmac(1, AR5312_WLAN1, AR5312_IRQ_WLAN1_INTRS);
1934 +
1935 + return 0;
1936 +}
1937 +
1938 +static void ar5312_restart(char *command)
1939 +{
1940 + /* reset the system */
1941 + local_irq_disable();
1942 + while (1)
1943 + ar231x_write_reg(AR5312_RESET, AR5312_RESET_SYSTEM);
1944 +}
1945 +
1946 +/*
1947 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
1948 + * to determine the predevisor value.
1949 + */
1950 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
1951 +
1952 +static int __init
1953 +ar5312_cpu_frequency(void)
1954 +{
1955 + unsigned int scratch;
1956 + unsigned int predivide_mask, predivide_shift;
1957 + unsigned int multiplier_mask, multiplier_shift;
1958 + unsigned int clock_ctl1, predivide_select, predivisor, multiplier;
1959 + unsigned int doubler_mask;
1960 + u16 devid;
1961 +
1962 + /* Trust the bootrom's idea of cpu frequency. */
1963 + scratch = ar231x_read_reg(AR5312_SCRATCH);
1964 + if (scratch)
1965 + return scratch;
1966 +
1967 + devid = ar231x_read_reg(AR5312_REV);
1968 + devid &= AR5312_REV_MAJ;
1969 + devid >>= AR5312_REV_MAJ_S;
1970 + if (devid == AR5312_REV_MAJ_AR2313) {
1971 + predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
1972 + predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
1973 + multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
1974 + multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
1975 + doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
1976 + } else { /* AR5312 and AR2312 */
1977 + predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
1978 + predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
1979 + multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
1980 + multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
1981 + doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
1982 + }
1983 +
1984 + /*
1985 + * Clocking is derived from a fixed 40MHz input clock.
1986 + *
1987 + * cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
1988 + * sys_freq = cpu_freq / 4 (used for APB clock, serial,
1989 + * flash, Timer, Watchdog Timer)
1990 + *
1991 + * cnt_freq = cpu_freq / 2 (use for CPU count/compare)
1992 + *
1993 + * So, for example, with a PLL multiplier of 5, we have
1994 + *
1995 + * cpu_freq = 200MHz
1996 + * sys_freq = 50MHz
1997 + * cnt_freq = 100MHz
1998 + *
1999 + * We compute the CPU frequency, based on PLL settings.
2000 + */
2001 +
2002 + clock_ctl1 = ar231x_read_reg(AR5312_CLOCKCTL1);
2003 + predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
2004 + predivisor = clockctl1_predivide_table[predivide_select];
2005 + multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
2006 +
2007 + if (clock_ctl1 & doubler_mask)
2008 + multiplier = multiplier << 1;
2009 +
2010 + return (40000000 / predivisor) * multiplier;
2011 +}
2012 +
2013 +static inline int
2014 +ar5312_sys_frequency(void)
2015 +{
2016 + return ar5312_cpu_frequency() / 4;
2017 +}
2018 +
2019 +void __init
2020 +ar5312_time_init(void)
2021 +{
2022 + if (!is_5312())
2023 + return;
2024 +
2025 + mips_hpt_frequency = ar5312_cpu_frequency() / 2;
2026 +}
2027 +
2028 +static int __init
2029 +ar5312_gpio_init(void)
2030 +{
2031 + int ret = gpiochip_add(&ar5312_gpio_chip);
2032 +
2033 + if (ret) {
2034 + pr_err("%s: failed to add gpiochip\n", ar5312_gpio_chip.label);
2035 + return ret;
2036 + }
2037 + pr_info("%s: registered %d GPIOs\n", ar5312_gpio_chip.label,
2038 + ar5312_gpio_chip.ngpio);
2039 + return ret;
2040 +}
2041 +
2042 +void __init
2043 +ar5312_prom_init(void)
2044 +{
2045 + u32 memsize, memcfg, bank0AC, bank1AC;
2046 + u32 devid;
2047 +
2048 + if (!is_5312())
2049 + return;
2050 +
2051 + /* Detect memory size */
2052 + memcfg = ar231x_read_reg(AR5312_MEM_CFG1);
2053 + bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
2054 + bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
2055 + memsize = (bank0AC ? (1 << (bank0AC+1)) : 0) +
2056 + (bank1AC ? (1 << (bank1AC+1)) : 0);
2057 + memsize <<= 20;
2058 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2059 +
2060 + devid = ar231x_read_reg(AR5312_REV);
2061 + devid >>= AR5312_REV_WMAC_MIN_S;
2062 + devid &= AR5312_REV_CHIP;
2063 + ar231x_board.devid = (u16)devid;
2064 + ar5312_gpio_init();
2065 +}
2066 +
2067 +void __init
2068 +ar5312_plat_setup(void)
2069 +{
2070 + if (!is_5312())
2071 + return;
2072 +
2073 + /* Clear any lingering AHB errors */
2074 + ar231x_read_reg(AR5312_PROCADDR);
2075 + ar231x_read_reg(AR5312_DMAADDR);
2076 + ar231x_write_reg(AR5312_WD_CTRL, AR5312_WD_CTRL_IGNORE_EXPIRATION);
2077 +
2078 + _machine_restart = ar5312_restart;
2079 + ar231x_serial_setup(AR5312_UART0, AR5312_MISC_IRQ_UART0,
2080 + ar5312_sys_frequency());
2081 +}
2082 +
2083 --- /dev/null
2084 +++ b/arch/mips/ar231x/ar2315.c
2085 @@ -0,0 +1,568 @@
2086 +/*
2087 + * This file is subject to the terms and conditions of the GNU General Public
2088 + * License. See the file "COPYING" in the main directory of this archive
2089 + * for more details.
2090 + *
2091 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
2092 + * Copyright (C) 2006 FON Technology, SL.
2093 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
2094 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
2095 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
2096 + */
2097 +
2098 +/*
2099 + * Platform devices for Atheros SoCs
2100 + */
2101 +
2102 +#include <generated/autoconf.h>
2103 +#include <linux/init.h>
2104 +#include <linux/module.h>
2105 +#include <linux/types.h>
2106 +#include <linux/string.h>
2107 +#include <linux/platform_device.h>
2108 +#include <linux/kernel.h>
2109 +#include <linux/reboot.h>
2110 +#include <linux/delay.h>
2111 +#include <linux/leds.h>
2112 +#include <linux/gpio.h>
2113 +#include <asm/bootinfo.h>
2114 +#include <asm/reboot.h>
2115 +#include <asm/time.h>
2116 +#include <linux/irq.h>
2117 +#include <linux/io.h>
2118 +
2119 +#include <ar231x_platform.h>
2120 +#include <ar2315_regs.h>
2121 +#include <ar231x.h>
2122 +#include "devices.h"
2123 +#include "ar2315.h"
2124 +
2125 +static u32 gpiointmask, gpiointval;
2126 +
2127 +static void ar2315_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
2128 +{
2129 + u32 pend;
2130 + int bit = -1;
2131 +
2132 + /* only do one gpio interrupt at a time */
2133 + pend = (ar231x_read_reg(AR2315_GPIO_DI) ^ gpiointval) & gpiointmask;
2134 +
2135 + if (pend) {
2136 + bit = fls(pend) - 1;
2137 + pend &= ~(1 << bit);
2138 + gpiointval ^= (1 << bit);
2139 + }
2140 +
2141 + if (!pend)
2142 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO);
2143 +
2144 + /* Enable interrupt with edge detection */
2145 + if ((ar231x_read_reg(AR2315_GPIO_DIR) & AR2315_GPIO_DIR_M(bit)) !=
2146 + AR2315_GPIO_DIR_I(bit))
2147 + return;
2148 +
2149 + if (bit >= 0)
2150 + do_IRQ(AR231X_GPIO_IRQ_BASE + bit);
2151 +}
2152 +
2153 +static void ar2315_misc_irq_handler(unsigned irq, struct irq_desc *desc)
2154 +{
2155 + unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) &
2156 + ar231x_read_reg(AR2315_IMR);
2157 +
2158 + if (misc_intr & AR2315_ISR_SPI)
2159 + do_IRQ(AR2315_MISC_IRQ_SPI);
2160 + else if (misc_intr & AR2315_ISR_TIMER)
2161 + do_IRQ(AR2315_MISC_IRQ_TIMER);
2162 + else if (misc_intr & AR2315_ISR_AHB)
2163 + do_IRQ(AR2315_MISC_IRQ_AHB);
2164 + else if (misc_intr & AR2315_ISR_GPIO)
2165 + do_IRQ(AR2315_MISC_IRQ_GPIO);
2166 + else if (misc_intr & AR2315_ISR_UART0)
2167 + do_IRQ(AR2315_MISC_IRQ_UART0);
2168 + else if (misc_intr & AR2315_ISR_WD) {
2169 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_WD);
2170 + do_IRQ(AR2315_MISC_IRQ_WATCHDOG);
2171 + } else
2172 + do_IRQ(AR2315_MISC_IRQ_NONE);
2173 +}
2174 +
2175 +/*
2176 + * Called when an interrupt is received, this function
2177 + * determines exactly which interrupt it was, and it
2178 + * invokes the appropriate handler.
2179 + *
2180 + * Implicitly, we also define interrupt priority by
2181 + * choosing which to dispatch first.
2182 + */
2183 +static asmlinkage void
2184 +ar2315_irq_dispatch(void)
2185 +{
2186 + int pending = read_c0_status() & read_c0_cause();
2187 +
2188 + if (pending & CAUSEF_IP3)
2189 + do_IRQ(AR2315_IRQ_WLAN0_INTRS);
2190 + else if (pending & CAUSEF_IP4)
2191 + do_IRQ(AR2315_IRQ_ENET0_INTRS);
2192 + else if (pending & CAUSEF_IP2)
2193 + do_IRQ(AR2315_IRQ_MISC_INTRS);
2194 + else if (pending & CAUSEF_IP7)
2195 + do_IRQ(AR231X_IRQ_CPU_CLOCK);
2196 +}
2197 +
2198 +static void ar2315_set_gpiointmask(int gpio, int level)
2199 +{
2200 + u32 reg;
2201 +
2202 + reg = ar231x_read_reg(AR2315_GPIO_INT);
2203 + reg &= ~(AR2315_GPIO_INT_M | AR2315_GPIO_INT_LVL_M);
2204 + reg |= gpio | AR2315_GPIO_INT_LVL(level);
2205 + ar231x_write_reg(AR2315_GPIO_INT, reg);
2206 +}
2207 +
2208 +static void ar2315_gpio_irq_unmask(struct irq_data *d)
2209 +{
2210 + unsigned int gpio = d->irq - AR231X_GPIO_IRQ_BASE;
2211 +
2212 + /* Enable interrupt with edge detection */
2213 + if ((ar231x_read_reg(AR2315_GPIO_DIR) & AR2315_GPIO_DIR_M(gpio)) !=
2214 + AR2315_GPIO_DIR_I(gpio))
2215 + return;
2216 +
2217 + gpiointmask |= (1 << gpio);
2218 + ar2315_set_gpiointmask(gpio, 3);
2219 +}
2220 +
2221 +static void ar2315_gpio_irq_mask(struct irq_data *d)
2222 +{
2223 + unsigned int gpio = d->irq - AR231X_GPIO_IRQ_BASE;
2224 +
2225 + /* Disable interrupt */
2226 + gpiointmask &= ~(1 << gpio);
2227 + ar2315_set_gpiointmask(gpio, 0);
2228 +}
2229 +
2230 +static struct irq_chip ar2315_gpio_irq_chip = {
2231 + .name = "AR2315-GPIO",
2232 + .irq_unmask = ar2315_gpio_irq_unmask,
2233 + .irq_mask = ar2315_gpio_irq_mask,
2234 +};
2235 +
2236 +static void
2237 +ar2315_misc_irq_unmask(struct irq_data *d)
2238 +{
2239 + unsigned int imr;
2240 +
2241 + imr = ar231x_read_reg(AR2315_IMR);
2242 + imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE - 1);
2243 + ar231x_write_reg(AR2315_IMR, imr);
2244 +}
2245 +
2246 +static void
2247 +ar2315_misc_irq_mask(struct irq_data *d)
2248 +{
2249 + unsigned int imr;
2250 +
2251 + imr = ar231x_read_reg(AR2315_IMR);
2252 + imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE - 1));
2253 + ar231x_write_reg(AR2315_IMR, imr);
2254 +}
2255 +
2256 +static struct irq_chip ar2315_misc_irq_chip = {
2257 + .name = "AR2315-MISC",
2258 + .irq_unmask = ar2315_misc_irq_unmask,
2259 + .irq_mask = ar2315_misc_irq_mask,
2260 +};
2261 +
2262 +static irqreturn_t ar2315_ahb_proc_handler(int cpl, void *dev_id)
2263 +{
2264 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2265 + ar231x_read_reg(AR2315_AHB_ERR1);
2266 +
2267 + pr_emerg("AHB fatal error\n");
2268 + machine_restart("AHB error"); /* Catastrophic failure */
2269 +
2270 + return IRQ_HANDLED;
2271 +}
2272 +
2273 +static struct irqaction ar2315_ahb_proc_interrupt = {
2274 + .handler = ar2315_ahb_proc_handler,
2275 + .name = "ar2315_ahb_proc_interrupt",
2276 +};
2277 +
2278 +void
2279 +ar2315_irq_init(void)
2280 +{
2281 + int i;
2282 +
2283 + if (!is_2315())
2284 + return;
2285 +
2286 + ar231x_irq_dispatch = ar2315_irq_dispatch;
2287 + gpiointval = ar231x_read_reg(AR2315_GPIO_DI);
2288 + for (i = 0; i < AR2315_MISC_IRQ_COUNT; i++) {
2289 + int irq = AR231X_MISC_IRQ_BASE + i;
2290 +
2291 + irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip,
2292 + handle_level_irq);
2293 + }
2294 + for (i = 0; i < AR2315_NUM_GPIO; i++) {
2295 + int irq = AR231X_GPIO_IRQ_BASE + i;
2296 +
2297 + irq_set_chip_and_handler(irq, &ar2315_gpio_irq_chip,
2298 + handle_level_irq);
2299 + }
2300 + irq_set_chained_handler(AR2315_MISC_IRQ_GPIO, ar2315_gpio_irq_handler);
2301 + setup_irq(AR2315_MISC_IRQ_AHB, &ar2315_ahb_proc_interrupt);
2302 + irq_set_chained_handler(AR2315_IRQ_MISC_INTRS, ar2315_misc_irq_handler);
2303 +}
2304 +
2305 +/*
2306 + * gpiolib implementation
2307 + */
2308 +static int
2309 +ar2315_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
2310 +{
2311 + return (ar231x_read_reg(AR2315_GPIO_DI) >> gpio) & 1;
2312 +}
2313 +
2314 +static void
2315 +ar2315_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
2316 +{
2317 + u32 reg = ar231x_read_reg(AR2315_GPIO_DO);
2318 +
2319 + reg = value ? reg | (1 << gpio) : reg & ~(1 << gpio);
2320 + ar231x_write_reg(AR2315_GPIO_DO, reg);
2321 +}
2322 +
2323 +static int
2324 +ar2315_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
2325 +{
2326 + ar231x_mask_reg(AR2315_GPIO_DIR, 1 << gpio, 0);
2327 + return 0;
2328 +}
2329 +
2330 +static int
2331 +ar2315_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
2332 +{
2333 + ar231x_mask_reg(AR2315_GPIO_DIR, 0, 1 << gpio);
2334 + ar2315_gpio_set_value(chip, gpio, value);
2335 + return 0;
2336 +}
2337 +
2338 +static int ar2315_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
2339 +{
2340 + return AR231X_GPIO_IRQ_BASE + gpio;
2341 +}
2342 +
2343 +static struct gpio_chip ar2315_gpio_chip = {
2344 + .label = "ar2315-gpio",
2345 + .direction_input = ar2315_gpio_direction_input,
2346 + .direction_output = ar2315_gpio_direction_output,
2347 + .set = ar2315_gpio_set_value,
2348 + .get = ar2315_gpio_get_value,
2349 + .to_irq = ar2315_gpio_to_irq,
2350 + .base = 0,
2351 + .ngpio = AR2315_NUM_GPIO, /* 22 */
2352 +};
2353 +
2354 +/* end of gpiolib */
2355 +
2356 +static void ar2315_device_reset_set(u32 mask)
2357 +{
2358 + u32 val;
2359 +
2360 + val = ar231x_read_reg(AR2315_RESET);
2361 + ar231x_write_reg(AR2315_RESET, val | mask);
2362 +}
2363 +
2364 +static void ar2315_device_reset_clear(u32 mask)
2365 +{
2366 + u32 val;
2367 +
2368 + val = ar231x_read_reg(AR2315_RESET);
2369 + ar231x_write_reg(AR2315_RESET, val & ~mask);
2370 +}
2371 +
2372 +static struct ar231x_eth ar2315_eth_data = {
2373 + .reset_set = ar2315_device_reset_set,
2374 + .reset_clear = ar2315_device_reset_clear,
2375 + .reset_mac = AR2315_RESET_ENET0,
2376 + .reset_phy = AR2315_RESET_EPHY0,
2377 + .config = &ar231x_board,
2378 +};
2379 +
2380 +static struct resource ar2315_spiflash_res[] = {
2381 + {
2382 + .name = "spiflash_read",
2383 + .flags = IORESOURCE_MEM,
2384 + .start = AR2315_SPI_READ,
2385 + .end = AR2315_SPI_READ + 0x1000000 - 1,
2386 + },
2387 + {
2388 + .name = "spiflash_mmr",
2389 + .flags = IORESOURCE_MEM,
2390 + .start = AR2315_SPI_MMR,
2391 + .end = AR2315_SPI_MMR + 12 - 1,
2392 + },
2393 +};
2394 +
2395 +static struct platform_device ar2315_spiflash = {
2396 + .id = 0,
2397 + .name = "ar2315-spiflash",
2398 + .resource = ar2315_spiflash_res,
2399 + .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
2400 +};
2401 +
2402 +static struct resource ar2315_wdt_res[] = {
2403 + {
2404 + .flags = IORESOURCE_MEM,
2405 + .start = AR2315_WD,
2406 + .end = AR2315_WD + 8 - 1,
2407 + },
2408 + {
2409 + .flags = IORESOURCE_IRQ,
2410 + .start = AR2315_MISC_IRQ_WATCHDOG,
2411 + .end = AR2315_MISC_IRQ_WATCHDOG,
2412 + }
2413 +};
2414 +
2415 +static struct platform_device ar2315_wdt = {
2416 + .id = 0,
2417 + .name = "ar2315-wdt",
2418 + .resource = ar2315_wdt_res,
2419 + .num_resources = ARRAY_SIZE(ar2315_wdt_res)
2420 +};
2421 +
2422 +/*
2423 + * NB: We use mapping size that is larger than the actual flash size,
2424 + * but this shouldn't be a problem here, because the flash will simply
2425 + * be mapped multiple times.
2426 + */
2427 +static u8 __init *ar2315_flash_limit(void)
2428 +{
2429 + return (u8 *)KSEG1ADDR(ar2315_spiflash_res[0].end + 1);
2430 +}
2431 +
2432 +#ifdef CONFIG_LEDS_GPIO
2433 +static struct gpio_led ar2315_leds[6];
2434 +static struct gpio_led_platform_data ar2315_led_data = {
2435 + .leds = (void *)ar2315_leds,
2436 +};
2437 +
2438 +static struct platform_device ar2315_gpio_leds = {
2439 + .name = "leds-gpio",
2440 + .id = -1,
2441 + .dev = {
2442 + .platform_data = (void *)&ar2315_led_data,
2443 + }
2444 +};
2445 +
2446 +static void __init
2447 +ar2315_init_gpio_leds(void)
2448 +{
2449 + static char led_names[6][6];
2450 + int i, led = 0;
2451 +
2452 + ar2315_led_data.num_leds = 0;
2453 + for (i = 1; i < 8; i++) {
2454 + if ((i == AR2315_RESET_GPIO) ||
2455 + (i == ar231x_board.config->reset_config_gpio))
2456 + continue;
2457 +
2458 + if (i == ar231x_board.config->sys_led_gpio)
2459 + strcpy(led_names[led], "wlan");
2460 + else
2461 + sprintf(led_names[led], "gpio%d", i);
2462 +
2463 + ar2315_leds[led].name = led_names[led];
2464 + ar2315_leds[led].gpio = i;
2465 + ar2315_leds[led].active_low = 0;
2466 + led++;
2467 + }
2468 + ar2315_led_data.num_leds = led;
2469 + platform_device_register(&ar2315_gpio_leds);
2470 +}
2471 +#else
2472 +static inline void ar2315_init_gpio_leds(void)
2473 +{
2474 +}
2475 +#endif
2476 +
2477 +int __init
2478 +ar2315_init_devices(void)
2479 +{
2480 + if (!is_2315())
2481 + return 0;
2482 +
2483 + /* Find board configuration */
2484 + ar231x_find_config(ar2315_flash_limit());
2485 + ar2315_eth_data.macaddr = ar231x_board.config->enet0_mac;
2486 +
2487 + ar2315_init_gpio_leds();
2488 + platform_device_register(&ar2315_wdt);
2489 + platform_device_register(&ar2315_spiflash);
2490 + ar231x_add_ethernet(0, AR2315_ENET0, "eth0_mii", AR2315_ENET0_MII,
2491 + AR2315_IRQ_ENET0_INTRS, &ar2315_eth_data);
2492 + ar231x_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS);
2493 +
2494 + return 0;
2495 +}
2496 +
2497 +static void
2498 +ar2315_restart(char *command)
2499 +{
2500 + void (*mips_reset_vec)(void) = (void *)0xbfc00000;
2501 +
2502 + local_irq_disable();
2503 +
2504 + /* try reset the system via reset control */
2505 + ar231x_write_reg(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
2506 +
2507 + /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
2508 + * a workaround. Give it some time to attempt a gpio based hardware
2509 + * reset (atheros reference design workaround) */
2510 + gpio_request_one(AR2315_RESET_GPIO, GPIOF_OUT_INIT_LOW, "Reset");
2511 + mdelay(100);
2512 +
2513 + /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
2514 + * workaround. Attempt to jump to the mips reset location -
2515 + * the boot loader itself might be able to recover the system */
2516 + mips_reset_vec();
2517 +}
2518 +
2519 +/*
2520 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
2521 + * to determine the predevisor value.
2522 + */
2523 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
2524 +static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
2525 +
2526 +static unsigned int __init
2527 +ar2315_sys_clk(unsigned int clock_ctl)
2528 +{
2529 + unsigned int pllc_ctrl, cpu_div;
2530 + unsigned int pllc_out, refdiv, fdiv, divby2;
2531 + unsigned int clk_div;
2532 +
2533 + pllc_ctrl = ar231x_read_reg(AR2315_PLLC_CTL);
2534 + refdiv = (pllc_ctrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
2535 + refdiv = clockctl1_predivide_table[refdiv];
2536 + fdiv = (pllc_ctrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
2537 + divby2 = (pllc_ctrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
2538 + divby2 += 1;
2539 + pllc_out = (40000000/refdiv)*(2*divby2)*fdiv;
2540 +
2541 + /* clkm input selected */
2542 + switch (clock_ctl & CPUCLK_CLK_SEL_M) {
2543 + case 0:
2544 + case 1:
2545 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKM_DIV_M) >>
2546 + PLLC_CLKM_DIV_S];
2547 + break;
2548 + case 2:
2549 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKC_DIV_M) >>
2550 + PLLC_CLKC_DIV_S];
2551 + break;
2552 + default:
2553 + pllc_out = 40000000;
2554 + clk_div = 1;
2555 + break;
2556 + }
2557 +
2558 + cpu_div = (clock_ctl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
2559 + cpu_div = cpu_div * 2 ?: 1;
2560 +
2561 + return pllc_out / (clk_div * cpu_div);
2562 +}
2563 +
2564 +static inline unsigned int
2565 +ar2315_cpu_frequency(void)
2566 +{
2567 + return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK));
2568 +}
2569 +
2570 +static inline unsigned int
2571 +ar2315_apb_frequency(void)
2572 +{
2573 + return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK));
2574 +}
2575 +
2576 +void __init
2577 +ar2315_time_init(void)
2578 +{
2579 + if (!is_2315())
2580 + return;
2581 +
2582 + mips_hpt_frequency = ar2315_cpu_frequency() / 2;
2583 +}
2584 +
2585 +static int __init
2586 +ar2315_gpio_init(void)
2587 +{
2588 + int ret = gpiochip_add(&ar2315_gpio_chip);
2589 +
2590 + if (ret) {
2591 + pr_err("%s: failed to add gpiochip\n", ar2315_gpio_chip.label);
2592 + return ret;
2593 + }
2594 + pr_info("%s: registered %d GPIOs\n", ar2315_gpio_chip.label,
2595 + ar2315_gpio_chip.ngpio);
2596 + return ret;
2597 +}
2598 +
2599 +void __init
2600 +ar2315_prom_init(void)
2601 +{
2602 + u32 memsize, memcfg, devid;
2603 +
2604 + if (!is_2315())
2605 + return;
2606 +
2607 + memcfg = ar231x_read_reg(AR2315_MEM_CFG);
2608 + memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
2609 + memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
2610 + memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
2611 + memsize <<= 3;
2612 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2613 +
2614 + /* Detect the hardware based on the device ID */
2615 + devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP;
2616 + switch (devid) {
2617 + case 0x91: /* Need to check */
2618 + ar231x_devtype = DEV_TYPE_AR2318;
2619 + break;
2620 + case 0x90:
2621 + ar231x_devtype = DEV_TYPE_AR2317;
2622 + break;
2623 + case 0x87:
2624 + ar231x_devtype = DEV_TYPE_AR2316;
2625 + break;
2626 + case 0x86:
2627 + default:
2628 + ar231x_devtype = DEV_TYPE_AR2315;
2629 + break;
2630 + }
2631 + ar2315_gpio_init();
2632 + ar231x_board.devid = devid;
2633 +}
2634 +
2635 +void __init
2636 +ar2315_plat_setup(void)
2637 +{
2638 + u32 config;
2639 +
2640 + if (!is_2315())
2641 + return;
2642 +
2643 + /* Clear any lingering AHB errors */
2644 + config = read_c0_config();
2645 + write_c0_config(config & ~0x3);
2646 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2647 + ar231x_read_reg(AR2315_AHB_ERR1);
2648 + ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION);
2649 +
2650 + _machine_restart = ar2315_restart;
2651 + ar231x_serial_setup(AR2315_UART0, AR2315_MISC_IRQ_UART0,
2652 + ar2315_apb_frequency());
2653 +}
2654 --- /dev/null
2655 +++ b/arch/mips/ar231x/ar2315.h
2656 @@ -0,0 +1,37 @@
2657 +#ifndef __AR2315_H
2658 +#define __AR2315_H
2659 +
2660 +#ifdef CONFIG_SOC_AR2315
2661 +
2662 +void ar2315_irq_init(void);
2663 +int ar2315_init_devices(void);
2664 +void ar2315_prom_init(void);
2665 +void ar2315_plat_setup(void);
2666 +void ar2315_time_init(void);
2667 +
2668 +#else
2669 +
2670 +static inline void ar2315_irq_init(void)
2671 +{
2672 +}
2673 +
2674 +static inline int ar2315_init_devices(void)
2675 +{
2676 + return 0;
2677 +}
2678 +
2679 +static inline void ar2315_prom_init(void)
2680 +{
2681 +}
2682 +
2683 +static inline void ar2315_plat_setup(void)
2684 +{
2685 +}
2686 +
2687 +static inline void ar2315_time_init(void)
2688 +{
2689 +}
2690 +
2691 +#endif
2692 +
2693 +#endif
2694 --- /dev/null
2695 +++ b/arch/mips/ar231x/ar5312.h
2696 @@ -0,0 +1,37 @@
2697 +#ifndef __AR5312_H
2698 +#define __AR5312_H
2699 +
2700 +#ifdef CONFIG_SOC_AR5312
2701 +
2702 +void ar5312_irq_init(void);
2703 +int ar5312_init_devices(void);
2704 +void ar5312_prom_init(void);
2705 +void ar5312_plat_setup(void);
2706 +void ar5312_time_init(void);
2707 +
2708 +#else
2709 +
2710 +static inline void ar5312_irq_init(void)
2711 +{
2712 +}
2713 +
2714 +static inline int ar5312_init_devices(void)
2715 +{
2716 + return 0;
2717 +}
2718 +
2719 +static inline void ar5312_prom_init(void)
2720 +{
2721 +}
2722 +
2723 +static inline void ar5312_plat_setup(void)
2724 +{
2725 +}
2726 +
2727 +static inline void ar5312_time_init(void)
2728 +{
2729 +}
2730 +
2731 +#endif
2732 +
2733 +#endif
2734 --- /dev/null
2735 +++ b/arch/mips/include/asm/mach-ar231x/ar231x.h
2736 @@ -0,0 +1,39 @@
2737 +#ifndef __ASM_MACH_AR231X_H
2738 +#define __ASM_MACH_AR231X_H
2739 +
2740 +#include <linux/types.h>
2741 +#include <linux/io.h>
2742 +
2743 +#define AR231X_MISC_IRQ_BASE 0x20
2744 +#define AR231X_GPIO_IRQ_BASE 0x30
2745 +
2746 +/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
2747 +#define AR231X_IRQ_NONE (MIPS_CPU_IRQ_BASE+0)
2748 +#define AR231X_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE+7) /* C0_CAUSE: 0x8000 */
2749 +
2750 +static inline u32
2751 +ar231x_read_reg(u32 reg)
2752 +{
2753 + return __raw_readl((void __iomem *)KSEG1ADDR(reg));
2754 +}
2755 +
2756 +static inline void
2757 +ar231x_write_reg(u32 reg, u32 val)
2758 +{
2759 + __raw_writel(val, (void __iomem *)KSEG1ADDR(reg));
2760 +}
2761 +
2762 +static inline u32
2763 +ar231x_mask_reg(u32 reg, u32 mask, u32 val)
2764 +{
2765 + u32 ret;
2766 +
2767 + ret = ar231x_read_reg(reg);
2768 + ret &= ~mask;
2769 + ret |= val;
2770 + ar231x_write_reg(reg, ret);
2771 +
2772 + return ret;
2773 +}
2774 +
2775 +#endif /* __ASM_MACH_AR231X_H */
2776 --- /dev/null
2777 +++ b/arch/mips/ar231x/devices.h
2778 @@ -0,0 +1,39 @@
2779 +#ifndef __AR231X_DEVICES_H
2780 +#define __AR231X_DEVICES_H
2781 +
2782 +enum {
2783 + /* handled by ar5312.c */
2784 + DEV_TYPE_AR2312,
2785 + DEV_TYPE_AR2313,
2786 + DEV_TYPE_AR5312,
2787 +
2788 + /* handled by ar2315.c */
2789 + DEV_TYPE_AR2315,
2790 + DEV_TYPE_AR2316,
2791 + DEV_TYPE_AR2317,
2792 + DEV_TYPE_AR2318,
2793 +
2794 + DEV_TYPE_UNKNOWN
2795 +};
2796 +
2797 +extern int ar231x_devtype;
2798 +extern struct ar231x_board_config ar231x_board;
2799 +extern asmlinkage void (*ar231x_irq_dispatch)(void);
2800 +
2801 +int ar231x_find_config(u8 *flash_limit);
2802 +void ar231x_serial_setup(u32 mapbase, int irq, unsigned int uartclk);
2803 +int ar231x_add_wmac(int nr, u32 base, int irq);
2804 +int ar231x_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
2805 + int irq, void *pdata);
2806 +
2807 +static inline bool is_2315(void)
2808 +{
2809 + return (current_cpu_data.cputype == CPU_4KEC);
2810 +}
2811 +
2812 +static inline bool is_5312(void)
2813 +{
2814 + return !is_2315();
2815 +}
2816 +
2817 +#endif
2818 --- /dev/null
2819 +++ b/arch/mips/ar231x/devices.c
2820 @@ -0,0 +1,181 @@
2821 +#include <linux/kernel.h>
2822 +#include <linux/init.h>
2823 +#include <linux/serial.h>
2824 +#include <linux/serial_core.h>
2825 +#include <linux/serial_8250.h>
2826 +#include <linux/platform_device.h>
2827 +#include <asm/bootinfo.h>
2828 +
2829 +#include <ar231x_platform.h>
2830 +#include <ar231x.h>
2831 +#include "devices.h"
2832 +#include "ar5312.h"
2833 +#include "ar2315.h"
2834 +
2835 +struct ar231x_board_config ar231x_board;
2836 +int ar231x_devtype = DEV_TYPE_UNKNOWN;
2837 +
2838 +static struct resource ar231x_eth0_res[] = {
2839 + {
2840 + .name = "eth0_membase",
2841 + .flags = IORESOURCE_MEM,
2842 + },
2843 + {
2844 + .name = "eth0_mii",
2845 + .flags = IORESOURCE_MEM,
2846 + },
2847 + {
2848 + .name = "eth0_irq",
2849 + .flags = IORESOURCE_IRQ,
2850 + }
2851 +};
2852 +
2853 +static struct resource ar231x_eth1_res[] = {
2854 + {
2855 + .name = "eth1_membase",
2856 + .flags = IORESOURCE_MEM,
2857 + },
2858 + {
2859 + .name = "eth1_mii",
2860 + .flags = IORESOURCE_MEM,
2861 + },
2862 + {
2863 + .name = "eth1_irq",
2864 + .flags = IORESOURCE_IRQ,
2865 + }
2866 +};
2867 +
2868 +static struct platform_device ar231x_eth[] = {
2869 + {
2870 + .id = 0,
2871 + .name = "ar231x-eth",
2872 + .resource = ar231x_eth0_res,
2873 + .num_resources = ARRAY_SIZE(ar231x_eth0_res)
2874 + },
2875 + {
2876 + .id = 1,
2877 + .name = "ar231x-eth",
2878 + .resource = ar231x_eth1_res,
2879 + .num_resources = ARRAY_SIZE(ar231x_eth1_res)
2880 + }
2881 +};
2882 +
2883 +static struct resource ar231x_wmac0_res[] = {
2884 + {
2885 + .name = "wmac0_membase",
2886 + .flags = IORESOURCE_MEM,
2887 + },
2888 + {
2889 + .name = "wmac0_irq",
2890 + .flags = IORESOURCE_IRQ,
2891 + }
2892 +};
2893 +
2894 +static struct resource ar231x_wmac1_res[] = {
2895 + {
2896 + .name = "wmac1_membase",
2897 + .flags = IORESOURCE_MEM,
2898 + },
2899 + {
2900 + .name = "wmac1_irq",
2901 + .flags = IORESOURCE_IRQ,
2902 + }
2903 +};
2904 +
2905 +static struct platform_device ar231x_wmac[] = {
2906 + {
2907 + .id = 0,
2908 + .name = "ar231x-wmac",
2909 + .resource = ar231x_wmac0_res,
2910 + .num_resources = ARRAY_SIZE(ar231x_wmac0_res),
2911 + .dev.platform_data = &ar231x_board,
2912 + },
2913 + {
2914 + .id = 1,
2915 + .name = "ar231x-wmac",
2916 + .resource = ar231x_wmac1_res,
2917 + .num_resources = ARRAY_SIZE(ar231x_wmac1_res),
2918 + .dev.platform_data = &ar231x_board,
2919 + },
2920 +};
2921 +
2922 +static const char * const devtype_strings[] = {
2923 + [DEV_TYPE_AR5312] = "Atheros AR5312",
2924 + [DEV_TYPE_AR2312] = "Atheros AR2312",
2925 + [DEV_TYPE_AR2313] = "Atheros AR2313",
2926 + [DEV_TYPE_AR2315] = "Atheros AR2315",
2927 + [DEV_TYPE_AR2316] = "Atheros AR2316",
2928 + [DEV_TYPE_AR2317] = "Atheros AR2317",
2929 + [DEV_TYPE_AR2318] = "Atheros AR2318",
2930 + [DEV_TYPE_UNKNOWN] = "Atheros (unknown)",
2931 +};
2932 +
2933 +const char *get_system_type(void)
2934 +{
2935 + if ((ar231x_devtype >= ARRAY_SIZE(devtype_strings)) ||
2936 + !devtype_strings[ar231x_devtype])
2937 + return devtype_strings[DEV_TYPE_UNKNOWN];
2938 + return devtype_strings[ar231x_devtype];
2939 +}
2940 +
2941 +int __init
2942 +ar231x_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
2943 + int irq, void *pdata)
2944 +{
2945 + struct resource *res;
2946 +
2947 + ar231x_eth[nr].dev.platform_data = pdata;
2948 + res = &ar231x_eth[nr].resource[0];
2949 + res->start = base;
2950 + res->end = base + 0x2000 - 1;
2951 + res++;
2952 + res->name = mii_name;
2953 + res->start = mii_base;
2954 + res->end = mii_base + 8 - 1;
2955 + res++;
2956 + res->start = irq;
2957 + res->end = irq;
2958 + return platform_device_register(&ar231x_eth[nr]);
2959 +}
2960 +
2961 +void __init
2962 +ar231x_serial_setup(u32 mapbase, int irq, unsigned int uartclk)
2963 +{
2964 + struct uart_port s;
2965 +
2966 + memset(&s, 0, sizeof(s));
2967 +
2968 + s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP;
2969 + s.iotype = UPIO_MEM32;
2970 + s.irq = irq;
2971 + s.regshift = 2;
2972 + s.mapbase = mapbase;
2973 + s.uartclk = uartclk;
2974 +
2975 + early_serial_setup(&s);
2976 +}
2977 +
2978 +int __init
2979 +ar231x_add_wmac(int nr, u32 base, int irq)
2980 +{
2981 + struct resource *res;
2982 +
2983 + ar231x_wmac[nr].dev.platform_data = &ar231x_board;
2984 + res = &ar231x_wmac[nr].resource[0];
2985 + res->start = base;
2986 + res->end = base + 0x10000 - 1;
2987 + res++;
2988 + res->start = irq;
2989 + res->end = irq;
2990 + return platform_device_register(&ar231x_wmac[nr]);
2991 +}
2992 +
2993 +static int __init ar231x_register_devices(void)
2994 +{
2995 + ar5312_init_devices();
2996 + ar2315_init_devices();
2997 +
2998 + return 0;
2999 +}
3000 +
3001 +device_initcall(ar231x_register_devices);
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