atheros: remove FSF mailing address
[openwrt/openwrt.git] / target / linux / atheros / patches-3.14 / 105-ar2315_pci.patch
1 --- a/arch/mips/ar231x/Makefile
2 +++ b/arch/mips/ar231x/Makefile
3 @@ -14,3 +14,4 @@ obj-$(CONFIG_EARLY_PRINTK) += early_prin
4
5 obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o
6 obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o
7 +obj-$(CONFIG_ATHEROS_AR2315_PCI) += pci.o
8 --- /dev/null
9 +++ b/arch/mips/ar231x/pci.c
10 @@ -0,0 +1,233 @@
11 +/*
12 + * This program is free software; you can redistribute it and/or
13 + * modify it under the terms of the GNU General Public License
14 + * as published by the Free Software Foundation; either version 2
15 + * of the License, or (at your option) any later version.
16 + *
17 + * This program is distributed in the hope that it will be useful,
18 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 + * GNU General Public License for more details.
21 + *
22 + * You should have received a copy of the GNU General Public License
23 + * along with this program; if not, see <http://www.gnu.org/licenses/>.
24 + */
25 +
26 +#include <linux/types.h>
27 +#include <linux/pci.h>
28 +#include <linux/kernel.h>
29 +#include <linux/init.h>
30 +#include <linux/mm.h>
31 +#include <linux/spinlock.h>
32 +#include <linux/delay.h>
33 +#include <linux/irq.h>
34 +#include <linux/io.h>
35 +#include <asm/paccess.h>
36 +#include <ar231x_platform.h>
37 +#include <ar231x.h>
38 +#include <ar2315_regs.h>
39 +#include "devices.h"
40 +
41 +#define AR2315_MEM_BASE 0x80800000UL
42 +#define AR2315_MEM_SIZE 0x00ffffffUL
43 +#define AR2315_IO_SIZE 0x00007fffUL
44 +
45 +static unsigned long configspace;
46 +
47 +static int config_access(int devfn, int where, int size, u32 *ptr, bool write)
48 +{
49 + unsigned long flags;
50 + int func = PCI_FUNC(devfn);
51 + int dev = PCI_SLOT(devfn);
52 + u32 value = 0;
53 + int err = 0;
54 + u32 addr;
55 +
56 + if (((dev != 0) && (dev != 3)) || (func > 2))
57 + return PCIBIOS_DEVICE_NOT_FOUND;
58 +
59 + /* Select Configuration access */
60 + local_irq_save(flags);
61 + ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, 0, AR2315_PCIMISC_CFG_SEL);
62 + mb();
63 +
64 + addr = (u32) configspace + (1 << (13 + dev)) + (func << 8) + where;
65 + if (size == 1)
66 + addr ^= 0x3;
67 + else if (size == 2)
68 + addr ^= 0x2;
69 +
70 + if (write) {
71 + value = *ptr;
72 + if (size == 1)
73 + err = put_dbe(value, (u8 *)addr);
74 + else if (size == 2)
75 + err = put_dbe(value, (u16 *)addr);
76 + else if (size == 4)
77 + err = put_dbe(value, (u32 *)addr);
78 + } else {
79 + if (size == 1)
80 + err = get_dbe(value, (u8 *)addr);
81 + else if (size == 2)
82 + err = get_dbe(value, (u16 *)addr);
83 + else if (size == 4)
84 + err = get_dbe(value, (u32 *)addr);
85 + if (err)
86 + *ptr = 0xffffffff;
87 + else
88 + *ptr = value;
89 + }
90 +
91 + /* Select Memory access */
92 + ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL, 0);
93 + local_irq_restore(flags);
94 +
95 + return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
96 +}
97 +
98 +static int ar231x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
99 + int size, u32 *value)
100 +{
101 + return config_access(devfn, where, size, value, 0);
102 +}
103 +
104 +static int ar231x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
105 + int size, u32 value)
106 +{
107 + return config_access(devfn, where, size, &value, 1);
108 +}
109 +
110 +static struct pci_ops ar231x_pci_ops = {
111 + .read = ar231x_pci_read,
112 + .write = ar231x_pci_write,
113 +};
114 +
115 +static struct resource ar231x_mem_resource = {
116 + .name = "AR2315 PCI MEM",
117 + .start = AR2315_MEM_BASE,
118 + .end = AR2315_MEM_BASE + AR2315_MEM_SIZE - AR2315_IO_SIZE - 1 +
119 + 0x4000000,
120 + .flags = IORESOURCE_MEM,
121 +};
122 +
123 +static struct resource ar231x_io_resource = {
124 + .name = "AR2315 PCI I/O",
125 + .start = AR2315_MEM_BASE + AR2315_MEM_SIZE - AR2315_IO_SIZE,
126 + .end = AR2315_MEM_BASE + AR2315_MEM_SIZE - 1,
127 + .flags = IORESOURCE_IO,
128 +};
129 +
130 +static struct pci_controller ar231x_pci_controller = {
131 + .pci_ops = &ar231x_pci_ops,
132 + .mem_resource = &ar231x_mem_resource,
133 + .io_resource = &ar231x_io_resource,
134 + .mem_offset = 0x00000000UL,
135 + .io_offset = 0x00000000UL,
136 +};
137 +
138 +int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
139 +{
140 + return AR2315_IRQ_LCBUS_PCI;
141 +}
142 +
143 +int pcibios_plat_dev_init(struct pci_dev *dev)
144 +{
145 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 5);
146 + pci_write_config_word(dev, 0x40, 0);
147 +
148 + /* Clear any pending Abort or external Interrupts
149 + * and enable interrupt processing */
150 + ar231x_mask_reg(AR2315_PCI_INTEN_REG, AR2315_PCI_INT_ENABLE, 0);
151 + ar231x_write_reg(AR2315_PCI_INT_STATUS, (AR2315_PCI_ABORT_INT |
152 + AR2315_PCI_EXT_INT));
153 + ar231x_write_reg(AR2315_PCI_INT_MASK, (AR2315_PCI_ABORT_INT |
154 + AR2315_PCI_EXT_INT));
155 + ar231x_mask_reg(AR2315_PCI_INTEN_REG, 0, AR2315_PCI_INT_ENABLE);
156 +
157 + return 0;
158 +}
159 +
160 +static void
161 +ar2315_pci_fixup(struct pci_dev *dev)
162 +{
163 + unsigned int devfn = dev->devfn;
164 +
165 + if (dev->bus->number != 0)
166 + return;
167 +
168 + /* Only fix up the PCI host settings */
169 + if ((PCI_SLOT(devfn) != 3) || (PCI_FUNC(devfn) != 0))
170 + return;
171 +
172 + /* Fix up MBARs */
173 + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, HOST_PCI_MBAR0);
174 + pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, HOST_PCI_MBAR1);
175 + pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, HOST_PCI_MBAR2);
176 + pci_write_config_dword(dev, PCI_COMMAND, PCI_COMMAND_MEMORY |
177 + PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
178 + PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY |
179 + PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK);
180 +}
181 +DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, ar2315_pci_fixup);
182 +
183 +static int __init
184 +ar2315_pci_init(void)
185 +{
186 + u32 reg;
187 +
188 + if (ar231x_devtype != DEV_TYPE_AR2315)
189 + return -ENODEV;
190 +
191 + /* Remap PCI config space */
192 + configspace = (unsigned long) ioremap_nocache(AR2315_PCIEXT,
193 + 1*1024*1024);
194 + ar231x_pci_controller.io_map_base =
195 + (unsigned long) ioremap_nocache(AR2315_MEM_BASE +
196 + AR2315_MEM_SIZE, AR2315_IO_SIZE);
197 + set_io_port_base(ar231x_pci_controller.io_map_base); /* PCI I/O space*/
198 +
199 + reg = ar231x_mask_reg(AR2315_RESET, 0, AR2315_RESET_PCIDMA);
200 + msleep(20);
201 +
202 + reg &= ~AR2315_RESET_PCIDMA;
203 + ar231x_write_reg(AR2315_RESET, reg);
204 + msleep(20);
205 +
206 + ar231x_mask_reg(AR2315_ENDIAN_CTL, 0,
207 + AR2315_CONFIG_PCIAHB | AR2315_CONFIG_PCIAHB_BRIDGE);
208 +
209 + ar231x_write_reg(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM |
210 + (AR2315_PCICLK_IN_FREQ_DIV_6 << AR2315_PCICLK_DIV_S));
211 + ar231x_mask_reg(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI);
212 + ar231x_mask_reg(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK | AR2315_IF_MASK,
213 + AR2315_IF_PCI | AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR |
214 + (AR2315_IF_PCI_CLK_OUTPUT_CLK << AR2315_IF_PCI_CLK_SHIFT));
215 +
216 + /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */
217 + ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
218 + AR2315_PCIRST_LOW);
219 + msleep(100);
220 +
221 + /* Bring the PCI out of reset */
222 + ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
223 + AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8);
224 +
225 + ar231x_write_reg(AR2315_PCI_UNCACHE_CFG,
226 + 0x1E | /* 1GB uncached */
227 + (1 << 5) | /* Enable uncached */
228 + (0x2 << 30) /* Base: 0x80000000 */
229 + );
230 + ar231x_read_reg(AR2315_PCI_UNCACHE_CFG);
231 +
232 + msleep(500);
233 +
234 + /* dirty hack - anyone with a datasheet that knows the memory map ? */
235 + ioport_resource.start = 0x10000000;
236 + ioport_resource.end = 0xffffffff;
237 +
238 + register_pci_controller(&ar231x_pci_controller);
239 +
240 + return 0;
241 +}
242 +
243 +arch_initcall(ar2315_pci_init);
244 --- a/arch/mips/ar231x/Kconfig
245 +++ b/arch/mips/ar231x/Kconfig
246 @@ -14,3 +14,10 @@ config ATHEROS_AR2315
247 select SYS_SUPPORTS_32BIT_KERNEL
248 select SYS_SUPPORTS_BIG_ENDIAN
249 default y
250 +
251 +config ATHEROS_AR2315_PCI
252 + bool "PCI support"
253 + depends on ATHEROS_AR2315
254 + select HW_HAS_PCI
255 + select PCI
256 + default y
257 --- a/arch/mips/ar231x/ar2315.c
258 +++ b/arch/mips/ar231x/ar2315.c
259 @@ -87,6 +87,28 @@ static void ar2315_misc_irq_handler(unsi
260 do_IRQ(AR2315_MISC_IRQ_NONE);
261 }
262
263 +#ifdef CONFIG_ATHEROS_AR2315_PCI
264 +static inline void pci_abort_irq(void)
265 +{
266 + ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_ABORT_INT);
267 +}
268 +
269 +static inline void pci_ack_irq(void)
270 +{
271 + ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_EXT_INT);
272 +}
273 +
274 +static void ar2315_pci_irq(int irq)
275 +{
276 + if (ar231x_read_reg(AR2315_PCI_INT_STATUS) == AR2315_PCI_ABORT_INT)
277 + pci_abort_irq();
278 + else {
279 + do_IRQ(irq);
280 + pci_ack_irq();
281 + }
282 +}
283 +#endif /* CONFIG_ATHEROS_AR2315_PCI */
284 +
285 /*
286 * Called when an interrupt is received, this function
287 * determines exactly which interrupt it was, and it
288 @@ -104,6 +126,10 @@ ar2315_irq_dispatch(void)
289 do_IRQ(AR2315_IRQ_WLAN0_INTRS);
290 else if (pending & CAUSEF_IP4)
291 do_IRQ(AR2315_IRQ_ENET0_INTRS);
292 +#ifdef CONFIG_ATHEROS_AR2315_PCI
293 + else if (pending & CAUSEF_IP5)
294 + ar2315_pci_irq(AR2315_IRQ_LCBUS_PCI);
295 +#endif
296 else if (pending & CAUSEF_IP2)
297 do_IRQ(AR2315_IRQ_MISC_INTRS);
298 else if (pending & CAUSEF_IP7)