target/linux/atheros/patches-3.14/105-ar2315_pci.patch

   1 --- a/arch/mips/pci/Makefile
   2 +++ b/arch/mips/pci/Makefile
   3 @@ -19,6 +19,7 @@ obj-$(CONFIG_BCM47XX)         += pci-bcm47xx.o
   4  obj-$(CONFIG_BCM63XX)          += pci-bcm63xx.o fixup-bcm63xx.o \
   5                                         ops-bcm63xx.o
   6  obj-$(CONFIG_MIPS_ALCHEMY)     += pci-alchemy.o
   7 +obj-$(CONFIG_PCI_AR2315)       += pci-ar2315.o
   8  obj-$(CONFIG_SOC_AR71XX)       += pci-ar71xx.o
   9  obj-$(CONFIG_PCI_AR724X)       += pci-ar724x.o
  10
  11 --- /dev/null
  12 +++ b/arch/mips/pci/pci-ar2315.c
  13 @@ -0,0 +1,345 @@
  14 +/*
  15 + * This program is free software; you can redistribute it and/or
  16 + * modify it under the terms of the GNU General Public License
  17 + * as published by the Free Software Foundation; either version 2
  18 + * of the License, or (at your option) any later version.
  19 + *
  20 + * This program is distributed in the hope that it will be useful,
  21 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23 + * GNU General Public License for more details.
  24 + *
  25 + * You should have received a copy of the GNU General Public License
  26 + * along with this program; if not, see <http://www.gnu.org/licenses/>.
  27 + */
  28 +
  29 +/**
  30 + * Both AR2315 and AR2316 chips have PCI interface unit, which supports DMA
  31 + * and interrupt. PCI interface supports MMIO access method, but does not
  32 + * seem to support I/O ports.
  33 + *
  34 + * Read/write operation in the region 0x80000000-0xBFFFFFFF causes
  35 + * a memory read/write command on the PCI bus. 30 LSBs of address on
  36 + * the bus are taken from memory read/write request and 2 MSBs are
  37 + * determined by PCI unit configuration.
  38 + *
  39 + * To work with the configuration space instead of memory is necessary set
  40 + * the CFG_SEL bit in the PCI_MISC_CONFIG register.
  41 + *
  42 + * Devices on the bus can perform DMA requests via chip BAR1. PCI host
  43 + * controller BARs are programmend as if an external device is programmed.
  44 + * Which means that during configuration, IDSEL pin of the chip should be
  45 + * asserted.
  46 + *
  47 + * We know (and support) only one board that uses the PCI interface -
  48 + * Fonera 2.0g (FON2202). It has a USB EHCI controller connected to the
  49 + * AR2315 PCI bus. IDSEL pin of USB controller is connected to AD[13] line
  50 + * and IDSEL pin of AR125 is connected to AD[16] line.
  51 + */
  52 +
  53 +#include <linux/types.h>
  54 +#include <linux/pci.h>
  55 +#include <linux/platform_device.h>
  56 +#include <linux/kernel.h>
  57 +#include <linux/init.h>
  58 +#include <linux/mm.h>
  59 +#include <linux/delay.h>
  60 +#include <linux/irq.h>
  61 +#include <linux/io.h>
  62 +#include <asm/paccess.h>
  63 +#include <ar231x_platform.h>
  64 +#include <ar231x.h>
  65 +#include <ar2315_regs.h>
  66 +
  67 +/* Arbitrary size of memory region to access the configuration space */
  68 +#define AR2315_PCI_CFG_SIZE    0x00100000
  69 +
  70 +#define AR2315_PCI_HOST_SLOT   3
  71 +#define AR2315_PCI_HOST_DEVID  ((0xff18 << 16) | PCI_VENDOR_ID_ATHEROS)
  72 +
  73 +static void __iomem *ar2315_pci_cfg_mem;
  74 +
  75 +static int ar2315_pci_cfg_access(int devfn, int where, int size, u32 *ptr,
  76 +                                bool write)
  77 +{
  78 +       int func = PCI_FUNC(devfn);
  79 +       int dev = PCI_SLOT(devfn);
  80 +       u32 addr = (1 << (13 + dev)) | (func << 8) | (where & ~3);
  81 +       u32 mask = 0xffffffff >> 8 * (4 - size);
  82 +       u32 sh = (where & 3) * 8;
  83 +       u32 value, isr;
  84 +
  85 +       /* Prevent access past the remapped area */
  86 +       if (addr >= AR2315_PCI_CFG_SIZE || dev > 18)
  87 +               return PCIBIOS_DEVICE_NOT_FOUND;
  88 +
  89 +       /* Clear pending errors */
  90 +       ar231x_write_reg(AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
  91 +       /* Select Configuration access */
  92 +       ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, 0, AR2315_PCIMISC_CFG_SEL);
  93 +
  94 +       mb();   /* PCI must see space change before we begin */
  95 +
  96 +       value = __raw_readl(ar2315_pci_cfg_mem + addr);
  97 +
  98 +       isr = ar231x_read_reg(AR2315_PCI_ISR);
  99 +       if (isr & AR2315_PCI_INT_ABORT)
 100 +               goto exit_err;
 101 +
 102 +       if (write) {
 103 +               value = (value & ~(mask << sh)) | *ptr << sh;
 104 +               __raw_writel(value, ar2315_pci_cfg_mem + addr);
 105 +               isr = ar231x_read_reg(AR2315_PCI_ISR);
 106 +               if (isr & AR2315_PCI_INT_ABORT)
 107 +                       goto exit_err;
 108 +       } else {
 109 +               *ptr = (value >> sh) & mask;
 110 +       }
 111 +
 112 +       goto exit;
 113 +
 114 +exit_err:
 115 +       ar231x_write_reg(AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
 116 +       if (!write)
 117 +               *ptr = 0xffffffff;
 118 +
 119 +exit:
 120 +       /* Select Memory access */
 121 +       ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL, 0);
 122 +
 123 +       return isr & AR2315_PCI_INT_ABORT ? PCIBIOS_DEVICE_NOT_FOUND :
 124 +                                           PCIBIOS_SUCCESSFUL;
 125 +}
 126 +
 127 +static inline int ar2315_pci_local_cfg_rd(unsigned devfn, int where, u32 *val)
 128 +{
 129 +       return ar2315_pci_cfg_access(devfn, where, sizeof(u32), val, false);
 130 +}
 131 +
 132 +static inline int ar2315_pci_local_cfg_wr(unsigned devfn, int where, u32 val)
 133 +{
 134 +       return ar2315_pci_cfg_access(devfn, where, sizeof(u32), &val, true);
 135 +}
 136 +
 137 +static int ar2315_pci_cfg_read(struct pci_bus *bus, unsigned int devfn,
 138 +                              int where, int size, u32 *value)
 139 +{
 140 +       if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
 141 +               return PCIBIOS_DEVICE_NOT_FOUND;
 142 +
 143 +       return ar2315_pci_cfg_access(devfn, where, size, value, 0);
 144 +}
 145 +
 146 +static int ar2315_pci_cfg_write(struct pci_bus *bus, unsigned int devfn,
 147 +                               int where, int size, u32 value)
 148 +{
 149 +       if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
 150 +               return PCIBIOS_DEVICE_NOT_FOUND;
 151 +
 152 +       return ar2315_pci_cfg_access(devfn, where, size, &value, 1);
 153 +}
 154 +
 155 +static struct pci_ops ar2315_pci_ops = {
 156 +       .read   = ar2315_pci_cfg_read,
 157 +       .write  = ar2315_pci_cfg_write,
 158 +};
 159 +
 160 +static struct resource ar2315_mem_resource = {
 161 +       .name   = "ar2315-pci-mem",
 162 +       .start  = AR2315_PCIEXT,
 163 +       .end    = AR2315_PCIEXT + AR2315_PCIEXT_SZ - 1,
 164 +       .flags  = IORESOURCE_MEM,
 165 +};
 166 +
 167 +/* PCI controller does not support I/O ports */
 168 +static struct resource ar2315_io_resource = {
 169 +       .name   = "ar2315-pci-io",
 170 +       .start  = 0,
 171 +       .end    = 0,
 172 +       .flags  = IORESOURCE_IO,
 173 +};
 174 +
 175 +static struct pci_controller ar2315_pci_controller = {
 176 +       .pci_ops        = &ar2315_pci_ops,
 177 +       .mem_resource   = &ar2315_mem_resource,
 178 +       .io_resource    = &ar2315_io_resource,
 179 +       .mem_offset     = 0x00000000UL,
 180 +       .io_offset      = 0x00000000UL,
 181 +};
 182 +
 183 +static int ar2315_pci_host_setup(void)
 184 +{
 185 +       unsigned devfn = PCI_DEVFN(AR2315_PCI_HOST_SLOT, 0);
 186 +       int res;
 187 +       u32 id;
 188 +
 189 +       res = ar2315_pci_local_cfg_rd(devfn, PCI_VENDOR_ID, &id);
 190 +       if (res != PCIBIOS_SUCCESSFUL || id != AR2315_PCI_HOST_DEVID)
 191 +               return -ENODEV;
 192 +
 193 +       /* Program MBARs */
 194 +       ar2315_pci_local_cfg_wr(devfn, PCI_BASE_ADDRESS_0,
 195 +                               AR2315_PCI_HOST_MBAR0);
 196 +       ar2315_pci_local_cfg_wr(devfn, PCI_BASE_ADDRESS_1,
 197 +                               AR2315_PCI_HOST_MBAR1);
 198 +       ar2315_pci_local_cfg_wr(devfn, PCI_BASE_ADDRESS_2,
 199 +                               AR2315_PCI_HOST_MBAR2);
 200 +
 201 +       /* Run */
 202 +       ar2315_pci_local_cfg_wr(devfn, PCI_COMMAND, PCI_COMMAND_MEMORY |
 203 +                               PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
 204 +                               PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY |
 205 +                               PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK);
 206 +
 207 +       return 0;
 208 +}
 209 +
 210 +static void ar2315_pci_irq_handler(unsigned irq, struct irq_desc *desc)
 211 +{
 212 +       u32 pending = ar231x_read_reg(AR2315_PCI_ISR) &
 213 +                     ar231x_read_reg(AR2315_PCI_IMR);
 214 +
 215 +       if (pending & AR2315_PCI_INT_EXT)
 216 +               generic_handle_irq(AR2315_PCI_IRQ_EXT);
 217 +       else if (pending & AR2315_PCI_INT_ABORT)
 218 +               generic_handle_irq(AR2315_PCI_IRQ_ABORT);
 219 +       else
 220 +               spurious_interrupt();
 221 +}
 222 +
 223 +static void ar2315_pci_irq_mask(struct irq_data *d)
 224 +{
 225 +       u32 m = 1 << (d->irq - AR2315_PCI_IRQ_BASE + AR2315_PCI_IRQ_SHIFT);
 226 +
 227 +       ar231x_mask_reg(AR2315_PCI_IMR, m, 0);
 228 +}
 229 +
 230 +static void ar2315_pci_irq_mask_ack(struct irq_data *d)
 231 +{
 232 +       u32 m = 1 << (d->irq - AR2315_PCI_IRQ_BASE + AR2315_PCI_IRQ_SHIFT);
 233 +
 234 +       ar231x_mask_reg(AR2315_PCI_IMR, m, 0);
 235 +       ar231x_write_reg(AR2315_PCI_ISR, m);
 236 +}
 237 +
 238 +static void ar2315_pci_irq_unmask(struct irq_data *d)
 239 +{
 240 +       u32 m = 1 << (d->irq - AR2315_PCI_IRQ_BASE + AR2315_PCI_IRQ_SHIFT);
 241 +
 242 +       ar231x_mask_reg(AR2315_PCI_IMR, 0, m);
 243 +}
 244 +
 245 +static struct irq_chip ar2315_pci_irq_chip = {
 246 +       .name = "AR2315-PCI",
 247 +       .irq_mask = ar2315_pci_irq_mask,
 248 +       .irq_mask_ack = ar2315_pci_irq_mask_ack,
 249 +       .irq_unmask = ar2315_pci_irq_unmask,
 250 +};
 251 +
 252 +static void ar2315_pci_irq_init(void)
 253 +{
 254 +       int i;
 255 +
 256 +       ar231x_mask_reg(AR2315_PCI_IER, AR2315_PCI_IER_ENABLE, 0);
 257 +       ar231x_mask_reg(AR2315_PCI_IMR, (AR2315_PCI_INT_ABORT |
 258 +                        AR2315_PCI_INT_EXT), 0);
 259 +
 260 +       for (i = 0; i < AR2315_PCI_IRQ_COUNT; ++i) {
 261 +               int irq = AR2315_PCI_IRQ_BASE + i;
 262 +
 263 +               irq_set_chip_and_handler(irq, &ar2315_pci_irq_chip,
 264 +                                        handle_level_irq);
 265 +       }
 266 +
 267 +       irq_set_chained_handler(AR2315_IRQ_LCBUS_PCI, ar2315_pci_irq_handler);
 268 +
 269 +       /* Clear any pending Abort or external Interrupts
 270 +        * and enable interrupt processing */
 271 +       ar231x_write_reg(AR2315_PCI_ISR, (AR2315_PCI_INT_ABORT |
 272 +                        AR2315_PCI_INT_EXT));
 273 +       ar231x_mask_reg(AR2315_PCI_IER, 0, AR2315_PCI_IER_ENABLE);
 274 +}
 275 +
 276 +static int ar2315_pci_probe(struct platform_device *pdev)
 277 +{
 278 +       struct device *dev = &pdev->dev;
 279 +       u32 reg;
 280 +       int res;
 281 +
 282 +       /* Remap PCI config space */
 283 +       ar2315_pci_cfg_mem = devm_ioremap_nocache(dev, AR2315_PCIEXT,
 284 +                                                 AR2315_PCI_CFG_SIZE);
 285 +       if (!ar2315_pci_cfg_mem) {
 286 +               dev_err(dev, "failed to remap PCI config space\n");
 287 +               return -ENOMEM;
 288 +       }
 289 +
 290 +       /* Reset PCI DMA logic */
 291 +       reg = ar231x_mask_reg(AR2315_RESET, 0, AR2315_RESET_PCIDMA);
 292 +       msleep(20);
 293 +       reg &= ~AR2315_RESET_PCIDMA;
 294 +       ar231x_write_reg(AR2315_RESET, reg);
 295 +       msleep(20);
 296 +
 297 +       ar231x_mask_reg(AR2315_ENDIAN_CTL, 0,
 298 +                       AR2315_CONFIG_PCIAHB | AR2315_CONFIG_PCIAHB_BRIDGE);
 299 +
 300 +       ar231x_write_reg(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM |
 301 +                        (AR2315_PCICLK_IN_FREQ_DIV_6 << AR2315_PCICLK_DIV_S));
 302 +       ar231x_mask_reg(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI);
 303 +       ar231x_mask_reg(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK | AR2315_IF_MASK,
 304 +                       AR2315_IF_PCI | AR2315_IF_PCI_HOST |
 305 +                       AR2315_IF_PCI_INTR | (AR2315_IF_PCI_CLK_OUTPUT_CLK <<
 306 +                                             AR2315_IF_PCI_CLK_SHIFT));
 307 +
 308 +       /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */
 309 +       ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
 310 +                       AR2315_PCIRST_LOW);
 311 +       msleep(100);
 312 +
 313 +       /* Bring the PCI out of reset */
 314 +       ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
 315 +                       AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8);
 316 +
 317 +       ar231x_write_reg(AR2315_PCI_UNCACHE_CFG,
 318 +                        0x1E | /* 1GB uncached */
 319 +                        (1 << 5) | /* Enable uncached */
 320 +                        (0x2 << 30) /* Base: 0x80000000 */);
 321 +       ar231x_read_reg(AR2315_PCI_UNCACHE_CFG);
 322 +
 323 +       msleep(500);
 324 +
 325 +       res = ar2315_pci_host_setup();
 326 +       if (res)
 327 +               return res;
 328 +
 329 +       ar2315_pci_irq_init();
 330 +
 331 +       register_pci_controller(&ar2315_pci_controller);
 332 +
 333 +       return 0;
 334 +}
 335 +
 336 +static struct platform_driver ar2315_pci_driver = {
 337 +       .probe = ar2315_pci_probe,
 338 +       .driver = {
 339 +               .name = "ar2315-pci",
 340 +               .owner = THIS_MODULE,
 341 +       },
 342 +};
 343 +
 344 +static int __init ar2315_pci_init(void)
 345 +{
 346 +       return platform_driver_register(&ar2315_pci_driver);
 347 +}
 348 +arch_initcall(ar2315_pci_init);
 349 +
 350 +int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 351 +{
 352 +       return AR2315_PCI_IRQ_EXT;
 353 +}
 354 +
 355 +int pcibios_plat_dev_init(struct pci_dev *dev)
 356 +{
 357 +       return 0;
 358 +}
 359 --- a/arch/mips/ar231x/Kconfig
 360 +++ b/arch/mips/ar231x/Kconfig
 361 @@ -7,3 +7,10 @@ config ATHEROS_AR2315
 362         bool "Atheros 2315+ support"
 363         depends on ATHEROS_AR231X
 364         default y
 365 +
 366 +config PCI_AR2315
 367 +       bool "AR2315 PCI controller support"
 368 +       depends on ATHEROS_AR2315
 369 +       select HW_HAS_PCI
 370 +       select PCI
 371 +       default y
 372 --- a/arch/mips/ar231x/ar2315.c
 373 +++ b/arch/mips/ar231x/ar2315.c
 374 @@ -104,6 +104,10 @@ ar2315_irq_dispatch(void)
 375                 do_IRQ(AR2315_IRQ_WLAN0_INTRS);
 376         else if (pending & CAUSEF_IP4)
 377                 do_IRQ(AR2315_IRQ_ENET0_INTRS);
 378 +#ifdef CONFIG_PCI_AR2315
 379 +       else if (pending & CAUSEF_IP5)
 380 +               do_IRQ(AR2315_IRQ_LCBUS_PCI);
 381 +#endif
 382         else if (pending & CAUSEF_IP2)
 383                 do_IRQ(AR2315_IRQ_MISC_INTRS);
 384         else if (pending & CAUSEF_IP7)
 385 @@ -554,3 +558,18 @@ ar2315_plat_setup(void)
 386         ar231x_serial_setup(AR2315_UART0, AR2315_MISC_IRQ_UART0,
 387                             ar2315_apb_frequency());
 388  }
 389 +
 390 +#ifdef CONFIG_PCI_AR2315
 391 +static int __init ar2315_pci_init(void)
 392 +{
 393 +       struct platform_device *pdev;
 394 +
 395 +       if (!is_2315() || ar231x_devtype != DEV_TYPE_AR2315)
 396 +               return -ENODEV;
 397 +
 398 +       pdev = platform_device_register_simple("ar2315-pci", -1, NULL, 0);
 399 +
 400 +       return pdev ? 0 : -ENODEV;
 401 +}
 402 +arch_initcall(ar2315_pci_init);
 403 +#endif