9bf9abb9984e15cf2e48c16fe3d315c71e9e97d9
[openwrt/openwrt.git] / target / linux / atheros / patches-3.14 / 110-ar2313_ethernet.patch
1 --- a/drivers/net/ethernet/atheros/Makefile
2 +++ b/drivers/net/ethernet/atheros/Makefile
3 @@ -7,3 +7,4 @@ obj-$(CONFIG_ATL2) += atlx/
4 obj-$(CONFIG_ATL1E) += atl1e/
5 obj-$(CONFIG_ATL1C) += atl1c/
6 obj-$(CONFIG_ALX) += alx/
7 +obj-$(CONFIG_NET_AR231X) += ar231x/
8 --- a/drivers/net/ethernet/atheros/Kconfig
9 +++ b/drivers/net/ethernet/atheros/Kconfig
10 @@ -5,7 +5,7 @@
11 config NET_VENDOR_ATHEROS
12 bool "Atheros devices"
13 default y
14 - depends on PCI
15 + depends on (PCI || ATHEROS_AR231X)
16 ---help---
17 If you have a network (Ethernet) card belonging to this class, say Y
18 and read the Ethernet-HOWTO, available from
19 @@ -80,4 +80,10 @@ config ALX
20 To compile this driver as a module, choose M here. The module
21 will be called alx.
22
23 +config NET_AR231X
24 + tristate "Atheros AR231X built-in Ethernet support"
25 + depends on ATHEROS_AR231X
26 + help
27 + Support for the AR231x/531x ethernet controller
28 +
29 endif # NET_VENDOR_ATHEROS
30 --- /dev/null
31 +++ b/drivers/net/ethernet/atheros/ar231x/Makefile
32 @@ -0,0 +1 @@
33 +obj-$(CONFIG_NET_AR231X) += ar231x.o
34 --- /dev/null
35 +++ b/drivers/net/ethernet/atheros/ar231x/ar231x.c
36 @@ -0,0 +1,1250 @@
37 +/*
38 + * ar231x.c: Linux driver for the Atheros AR231x Ethernet device.
39 + *
40 + * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
41 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
42 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
43 + *
44 + * Thanks to Atheros for providing hardware and documentation
45 + * enabling me to write this driver.
46 + *
47 + * This program is free software; you can redistribute it and/or modify
48 + * it under the terms of the GNU General Public License as published by
49 + * the Free Software Foundation; either version 2 of the License, or
50 + * (at your option) any later version.
51 + *
52 + * Additional credits:
53 + * This code is taken from John Taylor's Sibyte driver and then
54 + * modified for the AR2313.
55 + */
56 +
57 +#include <linux/module.h>
58 +#include <linux/version.h>
59 +#include <linux/types.h>
60 +#include <linux/errno.h>
61 +#include <linux/ioport.h>
62 +#include <linux/pci.h>
63 +#include <linux/netdevice.h>
64 +#include <linux/etherdevice.h>
65 +#include <linux/interrupt.h>
66 +#include <linux/hardirq.h>
67 +#include <linux/skbuff.h>
68 +#include <linux/init.h>
69 +#include <linux/delay.h>
70 +#include <linux/mm.h>
71 +#include <linux/highmem.h>
72 +#include <linux/sockios.h>
73 +#include <linux/pkt_sched.h>
74 +#include <linux/mii.h>
75 +#include <linux/phy.h>
76 +#include <linux/ethtool.h>
77 +#include <linux/ctype.h>
78 +#include <linux/platform_device.h>
79 +#include <linux/io.h>
80 +#include <linux/uaccess.h>
81 +
82 +#include <net/sock.h>
83 +#include <net/ip.h>
84 +
85 +#define AR2313_MTU 1692
86 +#define AR2313_PRIOS 1
87 +#define AR2313_QUEUES (2*AR2313_PRIOS)
88 +#define AR2313_DESCR_ENTRIES 64
89 +
90 +
91 +#ifndef min
92 +#define min(a, b) (((a) < (b)) ? (a) : (b))
93 +#endif
94 +
95 +#ifndef SMP_CACHE_BYTES
96 +#define SMP_CACHE_BYTES L1_CACHE_BYTES
97 +#endif
98 +
99 +#define AR2313_MBOX_SET_BIT 0x8
100 +
101 +#include "ar231x.h"
102 +
103 +/**
104 + * New interrupt handler strategy:
105 + *
106 + * An old interrupt handler worked using the traditional method of
107 + * replacing an skbuff with a new one when a packet arrives. However
108 + * the rx rings do not need to contain a static number of buffer
109 + * descriptors, thus it makes sense to move the memory allocation out
110 + * of the main interrupt handler and do it in a bottom half handler
111 + * and only allocate new buffers when the number of buffers in the
112 + * ring is below a certain threshold. In order to avoid starving the
113 + * NIC under heavy load it is however necessary to force allocation
114 + * when hitting a minimum threshold. The strategy for alloction is as
115 + * follows:
116 + *
117 + * RX_LOW_BUF_THRES - allocate buffers in the bottom half
118 + * RX_PANIC_LOW_THRES - we are very low on buffers, allocate
119 + * the buffers in the interrupt handler
120 + * RX_RING_THRES - maximum number of buffers in the rx ring
121 + *
122 + * One advantagous side effect of this allocation approach is that the
123 + * entire rx processing can be done without holding any spin lock
124 + * since the rx rings and registers are totally independent of the tx
125 + * ring and its registers. This of course includes the kmalloc's of
126 + * new skb's. Thus start_xmit can run in parallel with rx processing
127 + * and the memory allocation on SMP systems.
128 + *
129 + * Note that running the skb reallocation in a bottom half opens up
130 + * another can of races which needs to be handled properly. In
131 + * particular it can happen that the interrupt handler tries to run
132 + * the reallocation while the bottom half is either running on another
133 + * CPU or was interrupted on the same CPU. To get around this the
134 + * driver uses bitops to prevent the reallocation routines from being
135 + * reentered.
136 + *
137 + * TX handling can also be done without holding any spin lock, wheee
138 + * this is fun! since tx_csm is only written to by the interrupt
139 + * handler.
140 + */
141 +
142 +/**
143 + * Threshold values for RX buffer allocation - the low water marks for
144 + * when to start refilling the rings are set to 75% of the ring
145 + * sizes. It seems to make sense to refill the rings entirely from the
146 + * intrrupt handler once it gets below the panic threshold, that way
147 + * we don't risk that the refilling is moved to another CPU when the
148 + * one running the interrupt handler just got the slab code hot in its
149 + * cache.
150 + */
151 +#define RX_RING_SIZE AR2313_DESCR_ENTRIES
152 +#define RX_PANIC_THRES (RX_RING_SIZE/4)
153 +#define RX_LOW_THRES ((3*RX_RING_SIZE)/4)
154 +#define CRC_LEN 4
155 +#define RX_OFFSET 2
156 +
157 +#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
158 +#define VLAN_HDR 4
159 +#else
160 +#define VLAN_HDR 0
161 +#endif
162 +
163 +#define AR2313_BUFSIZE (AR2313_MTU + VLAN_HDR + ETH_HLEN + CRC_LEN + \
164 + RX_OFFSET)
165 +
166 +#ifdef MODULE
167 +MODULE_LICENSE("GPL");
168 +MODULE_AUTHOR("Sameer Dekate <sdekate@arubanetworks.com>, Imre Kaloz <kaloz@openwrt.org>, Felix Fietkau <nbd@openwrt.org>");
169 +MODULE_DESCRIPTION("AR231x Ethernet driver");
170 +#endif
171 +
172 +#define virt_to_phys(x) ((u32)(x) & 0x1fffffff)
173 +
174 +/* prototypes */
175 +static void ar231x_halt(struct net_device *dev);
176 +static void rx_tasklet_func(unsigned long data);
177 +static void rx_tasklet_cleanup(struct net_device *dev);
178 +static void ar231x_multicast_list(struct net_device *dev);
179 +static void ar231x_tx_timeout(struct net_device *dev);
180 +
181 +static int ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum);
182 +static int ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
183 + u16 value);
184 +static int ar231x_mdiobus_reset(struct mii_bus *bus);
185 +static int ar231x_mdiobus_probe(struct net_device *dev);
186 +static void ar231x_adjust_link(struct net_device *dev);
187 +
188 +#ifndef ERR
189 +#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
190 +#endif
191 +
192 +#ifdef CONFIG_NET_POLL_CONTROLLER
193 +static void
194 +ar231x_netpoll(struct net_device *dev)
195 +{
196 + unsigned long flags;
197 +
198 + local_irq_save(flags);
199 + ar231x_interrupt(dev->irq, dev);
200 + local_irq_restore(flags);
201 +}
202 +#endif
203 +
204 +static const struct net_device_ops ar231x_ops = {
205 + .ndo_open = ar231x_open,
206 + .ndo_stop = ar231x_close,
207 + .ndo_start_xmit = ar231x_start_xmit,
208 + .ndo_set_rx_mode = ar231x_multicast_list,
209 + .ndo_do_ioctl = ar231x_ioctl,
210 + .ndo_change_mtu = eth_change_mtu,
211 + .ndo_validate_addr = eth_validate_addr,
212 + .ndo_set_mac_address = eth_mac_addr,
213 + .ndo_tx_timeout = ar231x_tx_timeout,
214 +#ifdef CONFIG_NET_POLL_CONTROLLER
215 + .ndo_poll_controller = ar231x_netpoll,
216 +#endif
217 +};
218 +
219 +static int ar231x_probe(struct platform_device *pdev)
220 +{
221 + struct net_device *dev;
222 + struct ar231x_private *sp;
223 + struct resource *res;
224 + unsigned long ar_eth_base;
225 + char buf[64];
226 +
227 + dev = alloc_etherdev(sizeof(struct ar231x_private));
228 +
229 + if (dev == NULL) {
230 + printk(KERN_ERR
231 + "ar231x: Unable to allocate net_device structure!\n");
232 + return -ENOMEM;
233 + }
234 +
235 + platform_set_drvdata(pdev, dev);
236 +
237 + sp = netdev_priv(dev);
238 + sp->dev = dev;
239 + sp->cfg = pdev->dev.platform_data;
240 +
241 + sprintf(buf, "eth%d_membase", pdev->id);
242 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, buf);
243 + if (!res)
244 + return -ENODEV;
245 +
246 + sp->link = 0;
247 + ar_eth_base = res->start;
248 +
249 + sprintf(buf, "eth%d_irq", pdev->id);
250 + dev->irq = platform_get_irq_byname(pdev, buf);
251 +
252 + spin_lock_init(&sp->lock);
253 +
254 + dev->features |= NETIF_F_HIGHDMA;
255 + dev->netdev_ops = &ar231x_ops;
256 +
257 + tasklet_init(&sp->rx_tasklet, rx_tasklet_func, (unsigned long) dev);
258 + tasklet_disable(&sp->rx_tasklet);
259 +
260 + sp->eth_regs = ioremap_nocache(ar_eth_base, sizeof(*sp->eth_regs));
261 + if (!sp->eth_regs) {
262 + printk("Can't remap eth registers\n");
263 + return -ENXIO;
264 + }
265 +
266 + /**
267 + * When there's only one MAC, PHY regs are typically on ENET0,
268 + * even though the MAC might be on ENET1.
269 + * So remap PHY regs separately.
270 + */
271 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "eth0_mii");
272 + if (!res) {
273 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
274 + "eth1_mii");
275 + if (!res)
276 + return -ENODEV;
277 + }
278 + sp->phy_regs = ioremap_nocache(res->start, resource_size(res));
279 + if (!sp->phy_regs) {
280 + printk("Can't remap phy registers\n");
281 + return -ENXIO;
282 + }
283 +
284 + sp->dma_regs = ioremap_nocache(ar_eth_base + 0x1000,
285 + sizeof(*sp->dma_regs));
286 + if (!sp->dma_regs) {
287 + printk("Can't remap DMA registers\n");
288 + return -ENXIO;
289 + }
290 + dev->base_addr = ar_eth_base + 0x1000;
291 +
292 + strncpy(sp->name, "Atheros AR231x", sizeof(sp->name) - 1);
293 + sp->name[sizeof(sp->name) - 1] = '\0';
294 + memcpy(dev->dev_addr, sp->cfg->macaddr, 6);
295 +
296 + if (ar231x_init(dev)) {
297 + /* ar231x_init() calls ar231x_init_cleanup() on error */
298 + kfree(dev);
299 + return -ENODEV;
300 + }
301 +
302 + if (register_netdev(dev)) {
303 + printk("%s: register_netdev failed\n", __func__);
304 + return -1;
305 + }
306 +
307 + printk("%s: %s: %pM, irq %d\n", dev->name, sp->name, dev->dev_addr,
308 + dev->irq);
309 +
310 + sp->mii_bus = mdiobus_alloc();
311 + if (sp->mii_bus == NULL)
312 + return -1;
313 +
314 + sp->mii_bus->priv = dev;
315 + sp->mii_bus->read = ar231x_mdiobus_read;
316 + sp->mii_bus->write = ar231x_mdiobus_write;
317 + sp->mii_bus->reset = ar231x_mdiobus_reset;
318 + sp->mii_bus->name = "ar231x_eth_mii";
319 + snprintf(sp->mii_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
320 + sp->mii_bus->irq = kmalloc(sizeof(int), GFP_KERNEL);
321 + *sp->mii_bus->irq = PHY_POLL;
322 +
323 + mdiobus_register(sp->mii_bus);
324 +
325 + if (ar231x_mdiobus_probe(dev) != 0) {
326 + printk(KERN_ERR "%s: mdiobus_probe failed\n", dev->name);
327 + rx_tasklet_cleanup(dev);
328 + ar231x_init_cleanup(dev);
329 + unregister_netdev(dev);
330 + kfree(dev);
331 + return -ENODEV;
332 + }
333 +
334 + /* start link poll timer */
335 + ar231x_setup_timer(dev);
336 +
337 + return 0;
338 +}
339 +
340 +
341 +static void ar231x_multicast_list(struct net_device *dev)
342 +{
343 + struct ar231x_private *sp = netdev_priv(dev);
344 + unsigned int filter;
345 +
346 + filter = sp->eth_regs->mac_control;
347 +
348 + if (dev->flags & IFF_PROMISC)
349 + filter |= MAC_CONTROL_PR;
350 + else
351 + filter &= ~MAC_CONTROL_PR;
352 + if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 0))
353 + filter |= MAC_CONTROL_PM;
354 + else
355 + filter &= ~MAC_CONTROL_PM;
356 +
357 + sp->eth_regs->mac_control = filter;
358 +}
359 +
360 +static void rx_tasklet_cleanup(struct net_device *dev)
361 +{
362 + struct ar231x_private *sp = netdev_priv(dev);
363 +
364 + /**
365 + * Tasklet may be scheduled. Need to get it removed from the list
366 + * since we're about to free the struct.
367 + */
368 +
369 + sp->unloading = 1;
370 + tasklet_enable(&sp->rx_tasklet);
371 + tasklet_kill(&sp->rx_tasklet);
372 +}
373 +
374 +static int ar231x_remove(struct platform_device *pdev)
375 +{
376 + struct net_device *dev = platform_get_drvdata(pdev);
377 + struct ar231x_private *sp = netdev_priv(dev);
378 +
379 + rx_tasklet_cleanup(dev);
380 + ar231x_init_cleanup(dev);
381 + unregister_netdev(dev);
382 + mdiobus_unregister(sp->mii_bus);
383 + mdiobus_free(sp->mii_bus);
384 + kfree(dev);
385 + return 0;
386 +}
387 +
388 +
389 +/**
390 + * Restart the AR2313 ethernet controller.
391 + */
392 +static int ar231x_restart(struct net_device *dev)
393 +{
394 + /* disable interrupts */
395 + disable_irq(dev->irq);
396 +
397 + /* stop mac */
398 + ar231x_halt(dev);
399 +
400 + /* initialize */
401 + ar231x_init(dev);
402 +
403 + /* enable interrupts */
404 + enable_irq(dev->irq);
405 +
406 + return 0;
407 +}
408 +
409 +static struct platform_driver ar231x_driver = {
410 + .driver.name = "ar231x-eth",
411 + .probe = ar231x_probe,
412 + .remove = ar231x_remove,
413 +};
414 +
415 +module_platform_driver(ar231x_driver);
416 +
417 +static void ar231x_free_descriptors(struct net_device *dev)
418 +{
419 + struct ar231x_private *sp = netdev_priv(dev);
420 +
421 + if (sp->rx_ring != NULL) {
422 + kfree((void *)KSEG0ADDR(sp->rx_ring));
423 + sp->rx_ring = NULL;
424 + sp->tx_ring = NULL;
425 + }
426 +}
427 +
428 +
429 +static int ar231x_allocate_descriptors(struct net_device *dev)
430 +{
431 + struct ar231x_private *sp = netdev_priv(dev);
432 + int size;
433 + int j;
434 + ar231x_descr_t *space;
435 +
436 + if (sp->rx_ring != NULL) {
437 + printk("%s: already done.\n", __func__);
438 + return 0;
439 + }
440 +
441 + size = sizeof(ar231x_descr_t) * (AR2313_DESCR_ENTRIES * AR2313_QUEUES);
442 + space = kmalloc(size, GFP_KERNEL);
443 + if (space == NULL)
444 + return 1;
445 +
446 + /* invalidate caches */
447 + dma_cache_inv((unsigned int) space, size);
448 +
449 + /* now convert pointer to KSEG1 */
450 + space = (ar231x_descr_t *)KSEG1ADDR(space);
451 +
452 + memset((void *)space, 0, size);
453 +
454 + sp->rx_ring = space;
455 + space += AR2313_DESCR_ENTRIES;
456 +
457 + sp->tx_ring = space;
458 + space += AR2313_DESCR_ENTRIES;
459 +
460 + /* Initialize the transmit Descriptors */
461 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
462 + ar231x_descr_t *td = &sp->tx_ring[j];
463 +
464 + td->status = 0;
465 + td->devcs = DMA_TX1_CHAINED;
466 + td->addr = 0;
467 + td->descr = virt_to_phys(&sp->tx_ring[DSC_NEXT(j)]);
468 + }
469 +
470 + return 0;
471 +}
472 +
473 +
474 +/**
475 + * Generic cleanup handling data allocated during init. Used when the
476 + * module is unloaded or if an error occurs during initialization
477 + */
478 +static void ar231x_init_cleanup(struct net_device *dev)
479 +{
480 + struct ar231x_private *sp = netdev_priv(dev);
481 + struct sk_buff *skb;
482 + int j;
483 +
484 + ar231x_free_descriptors(dev);
485 +
486 + if (sp->eth_regs)
487 + iounmap((void *)sp->eth_regs);
488 + if (sp->dma_regs)
489 + iounmap((void *)sp->dma_regs);
490 + if (sp->phy_regs)
491 + iounmap((void *)sp->phy_regs);
492 +
493 + if (sp->rx_skb) {
494 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
495 + skb = sp->rx_skb[j];
496 + if (skb) {
497 + sp->rx_skb[j] = NULL;
498 + dev_kfree_skb(skb);
499 + }
500 + }
501 + kfree(sp->rx_skb);
502 + sp->rx_skb = NULL;
503 + }
504 +
505 + if (sp->tx_skb) {
506 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
507 + skb = sp->tx_skb[j];
508 + if (skb) {
509 + sp->tx_skb[j] = NULL;
510 + dev_kfree_skb(skb);
511 + }
512 + }
513 + kfree(sp->tx_skb);
514 + sp->tx_skb = NULL;
515 + }
516 +}
517 +
518 +static int ar231x_setup_timer(struct net_device *dev)
519 +{
520 + struct ar231x_private *sp = netdev_priv(dev);
521 +
522 + init_timer(&sp->link_timer);
523 +
524 + sp->link_timer.function = ar231x_link_timer_fn;
525 + sp->link_timer.data = (int) dev;
526 + sp->link_timer.expires = jiffies + HZ;
527 +
528 + add_timer(&sp->link_timer);
529 + return 0;
530 +}
531 +
532 +static void ar231x_link_timer_fn(unsigned long data)
533 +{
534 + struct net_device *dev = (struct net_device *)data;
535 + struct ar231x_private *sp = netdev_priv(dev);
536 +
537 + /**
538 + * See if the link status changed.
539 + * This was needed to make sure we set the PHY to the
540 + * autonegotiated value of half or full duplex.
541 + */
542 + ar231x_check_link(dev);
543 +
544 + /**
545 + * Loop faster when we don't have link.
546 + * This was needed to speed up the AP bootstrap time.
547 + */
548 + if (sp->link == 0)
549 + mod_timer(&sp->link_timer, jiffies + HZ / 2);
550 + else
551 + mod_timer(&sp->link_timer, jiffies + LINK_TIMER);
552 +}
553 +
554 +static void ar231x_check_link(struct net_device *dev)
555 +{
556 + struct ar231x_private *sp = netdev_priv(dev);
557 + u16 phy_data;
558 +
559 + phy_data = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMSR);
560 + if (sp->phy_data != phy_data) {
561 + if (phy_data & BMSR_LSTATUS) {
562 + /**
563 + * Link is present, ready link partner ability to
564 + * deterine duplexity.
565 + */
566 + int duplex = 0;
567 + u16 reg;
568 +
569 + sp->link = 1;
570 + reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy,
571 + MII_BMCR);
572 + if (reg & BMCR_ANENABLE) {
573 + /* auto neg enabled */
574 + reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy,
575 + MII_LPA);
576 + duplex = reg & (LPA_100FULL | LPA_10FULL) ?
577 + 1 : 0;
578 + } else {
579 + /* no auto neg, just read duplex config */
580 + duplex = (reg & BMCR_FULLDPLX) ? 1 : 0;
581 + }
582 +
583 + printk(KERN_INFO "%s: Configuring MAC for %s duplex\n",
584 + dev->name, (duplex) ? "full" : "half");
585 +
586 + if (duplex) {
587 + /* full duplex */
588 + sp->eth_regs->mac_control =
589 + (sp->eth_regs->mac_control |
590 + MAC_CONTROL_F) & ~MAC_CONTROL_DRO;
591 + } else {
592 + /* half duplex */
593 + sp->eth_regs->mac_control =
594 + (sp->eth_regs->mac_control |
595 + MAC_CONTROL_DRO) & ~MAC_CONTROL_F;
596 + }
597 + } else {
598 + /* no link */
599 + sp->link = 0;
600 + }
601 + sp->phy_data = phy_data;
602 + }
603 +}
604 +
605 +static int ar231x_reset_reg(struct net_device *dev)
606 +{
607 + struct ar231x_private *sp = netdev_priv(dev);
608 + unsigned int ethsal, ethsah;
609 + unsigned int flags;
610 +
611 + sp->cfg->reset_set(sp->cfg->reset_mac);
612 + mdelay(10);
613 + sp->cfg->reset_clear(sp->cfg->reset_mac);
614 + mdelay(10);
615 + sp->cfg->reset_set(sp->cfg->reset_phy);
616 + mdelay(10);
617 + sp->cfg->reset_clear(sp->cfg->reset_phy);
618 + mdelay(10);
619 +
620 + sp->dma_regs->bus_mode = (DMA_BUS_MODE_SWR);
621 + mdelay(10);
622 + sp->dma_regs->bus_mode =
623 + ((32 << DMA_BUS_MODE_PBL_SHIFT) | DMA_BUS_MODE_BLE);
624 +
625 + /* enable interrupts */
626 + sp->dma_regs->intr_ena = DMA_STATUS_AIS | DMA_STATUS_NIS |
627 + DMA_STATUS_RI | DMA_STATUS_TI |
628 + DMA_STATUS_FBE;
629 + sp->dma_regs->xmt_base = virt_to_phys(sp->tx_ring);
630 + sp->dma_regs->rcv_base = virt_to_phys(sp->rx_ring);
631 + sp->dma_regs->control =
632 + (DMA_CONTROL_SR | DMA_CONTROL_ST | DMA_CONTROL_SF);
633 +
634 + sp->eth_regs->flow_control = (FLOW_CONTROL_FCE);
635 + sp->eth_regs->vlan_tag = (0x8100);
636 +
637 + /* Enable Ethernet Interface */
638 + flags = (MAC_CONTROL_TE | /* transmit enable */
639 + MAC_CONTROL_PM | /* pass mcast */
640 + MAC_CONTROL_F | /* full duplex */
641 + MAC_CONTROL_HBD); /* heart beat disabled */
642 +
643 + if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
644 + flags |= MAC_CONTROL_PR;
645 + }
646 + sp->eth_regs->mac_control = flags;
647 +
648 + /* Set all Ethernet station address registers to their initial values */
649 + ethsah = (((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
650 + (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF);
651 +
652 + ethsal = (((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
653 + (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
654 + (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
655 + (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF);
656 +
657 + sp->eth_regs->mac_addr[0] = ethsah;
658 + sp->eth_regs->mac_addr[1] = ethsal;
659 +
660 + mdelay(10);
661 +
662 + return 0;
663 +}
664 +
665 +
666 +static int ar231x_init(struct net_device *dev)
667 +{
668 + struct ar231x_private *sp = netdev_priv(dev);
669 + int ecode = 0;
670 +
671 + /* Allocate descriptors */
672 + if (ar231x_allocate_descriptors(dev)) {
673 + printk("%s: %s: ar231x_allocate_descriptors failed\n",
674 + dev->name, __func__);
675 + ecode = -EAGAIN;
676 + goto init_error;
677 + }
678 +
679 + /* Get the memory for the skb rings */
680 + if (sp->rx_skb == NULL) {
681 + sp->rx_skb =
682 + kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
683 + GFP_KERNEL);
684 + if (!(sp->rx_skb)) {
685 + printk("%s: %s: rx_skb kmalloc failed\n",
686 + dev->name, __func__);
687 + ecode = -EAGAIN;
688 + goto init_error;
689 + }
690 + }
691 + memset(sp->rx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
692 +
693 + if (sp->tx_skb == NULL) {
694 + sp->tx_skb =
695 + kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
696 + GFP_KERNEL);
697 + if (!(sp->tx_skb)) {
698 + printk("%s: %s: tx_skb kmalloc failed\n",
699 + dev->name, __func__);
700 + ecode = -EAGAIN;
701 + goto init_error;
702 + }
703 + }
704 + memset(sp->tx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
705 +
706 + /**
707 + * Set tx_csm before we start receiving interrupts, otherwise
708 + * the interrupt handler might think it is supposed to process
709 + * tx ints before we are up and running, which may cause a null
710 + * pointer access in the int handler.
711 + */
712 + sp->rx_skbprd = 0;
713 + sp->cur_rx = 0;
714 + sp->tx_prd = 0;
715 + sp->tx_csm = 0;
716 +
717 + /* Zero the stats before starting the interface */
718 + memset(&dev->stats, 0, sizeof(dev->stats));
719 +
720 + /**
721 + * We load the ring here as there seem to be no way to tell the
722 + * firmware to wipe the ring without re-initializing it.
723 + */
724 + ar231x_load_rx_ring(dev, RX_RING_SIZE);
725 +
726 + /* Init hardware */
727 + ar231x_reset_reg(dev);
728 +
729 + /* Get the IRQ */
730 + ecode =
731 + request_irq(dev->irq, &ar231x_interrupt,
732 + IRQF_DISABLED,
733 + dev->name, dev);
734 + if (ecode) {
735 + printk(KERN_WARNING "%s: %s: Requested IRQ %d is busy\n",
736 + dev->name, __func__, dev->irq);
737 + goto init_error;
738 + }
739 +
740 +
741 + tasklet_enable(&sp->rx_tasklet);
742 +
743 + return 0;
744 +
745 +init_error:
746 + ar231x_init_cleanup(dev);
747 + return ecode;
748 +}
749 +
750 +/**
751 + * Load the rx ring.
752 + *
753 + * Loading rings is safe without holding the spin lock since this is
754 + * done only before the device is enabled, thus no interrupts are
755 + * generated and by the interrupt handler/tasklet handler.
756 + */
757 +static void ar231x_load_rx_ring(struct net_device *dev, int nr_bufs)
758 +{
759 + struct ar231x_private *sp = netdev_priv(dev);
760 + short i, idx;
761 +
762 + idx = sp->rx_skbprd;
763 +
764 + for (i = 0; i < nr_bufs; i++) {
765 + struct sk_buff *skb;
766 + ar231x_descr_t *rd;
767 +
768 + if (sp->rx_skb[idx])
769 + break;
770 +
771 + skb = netdev_alloc_skb_ip_align(dev, AR2313_BUFSIZE);
772 + if (!skb) {
773 + printk("\n\n\n\n %s: No memory in system\n\n\n\n",
774 + __func__);
775 + break;
776 + }
777 +
778 + /* Make sure IP header starts on a fresh cache line */
779 + skb->dev = dev;
780 + sp->rx_skb[idx] = skb;
781 +
782 + rd = (ar231x_descr_t *)&sp->rx_ring[idx];
783 +
784 + /* initialize dma descriptor */
785 + rd->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
786 + DMA_RX1_CHAINED);
787 + rd->addr = virt_to_phys(skb->data);
788 + rd->descr = virt_to_phys(&sp->rx_ring[DSC_NEXT(idx)]);
789 + rd->status = DMA_RX_OWN;
790 +
791 + idx = DSC_NEXT(idx);
792 + }
793 +
794 + if (i)
795 + sp->rx_skbprd = idx;
796 +}
797 +
798 +#define AR2313_MAX_PKTS_PER_CALL 64
799 +
800 +static int ar231x_rx_int(struct net_device *dev)
801 +{
802 + struct ar231x_private *sp = netdev_priv(dev);
803 + struct sk_buff *skb, *skb_new;
804 + ar231x_descr_t *rxdesc;
805 + unsigned int status;
806 + u32 idx;
807 + int pkts = 0;
808 + int rval;
809 +
810 + idx = sp->cur_rx;
811 +
812 + /* process at most the entire ring and then wait for another int */
813 + while (1) {
814 + rxdesc = &sp->rx_ring[idx];
815 + status = rxdesc->status;
816 +
817 + if (status & DMA_RX_OWN) {
818 + /* SiByte owns descriptor or descr not yet filled in */
819 + rval = 0;
820 + break;
821 + }
822 +
823 + if (++pkts > AR2313_MAX_PKTS_PER_CALL) {
824 + rval = 1;
825 + break;
826 + }
827 +
828 + if ((status & DMA_RX_ERROR) && !(status & DMA_RX_LONG)) {
829 + dev->stats.rx_errors++;
830 + dev->stats.rx_dropped++;
831 +
832 + /* add statistics counters */
833 + if (status & DMA_RX_ERR_CRC)
834 + dev->stats.rx_crc_errors++;
835 + if (status & DMA_RX_ERR_COL)
836 + dev->stats.rx_over_errors++;
837 + if (status & DMA_RX_ERR_LENGTH)
838 + dev->stats.rx_length_errors++;
839 + if (status & DMA_RX_ERR_RUNT)
840 + dev->stats.rx_over_errors++;
841 + if (status & DMA_RX_ERR_DESC)
842 + dev->stats.rx_over_errors++;
843 +
844 + } else {
845 + /* alloc new buffer. */
846 + skb_new = netdev_alloc_skb_ip_align(dev,
847 + AR2313_BUFSIZE);
848 + if (skb_new != NULL) {
849 + skb = sp->rx_skb[idx];
850 + /* set skb */
851 + skb_put(skb, ((status >> DMA_RX_LEN_SHIFT) &
852 + 0x3fff) - CRC_LEN);
853 +
854 + dev->stats.rx_bytes += skb->len;
855 + skb->protocol = eth_type_trans(skb, dev);
856 + /* pass the packet to upper layers */
857 + netif_rx(skb);
858 +
859 + skb_new->dev = dev;
860 + /* reset descriptor's curr_addr */
861 + rxdesc->addr = virt_to_phys(skb_new->data);
862 +
863 + dev->stats.rx_packets++;
864 + sp->rx_skb[idx] = skb_new;
865 + } else {
866 + dev->stats.rx_dropped++;
867 + }
868 + }
869 +
870 + rxdesc->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
871 + DMA_RX1_CHAINED);
872 + rxdesc->status = DMA_RX_OWN;
873 +
874 + idx = DSC_NEXT(idx);
875 + }
876 +
877 + sp->cur_rx = idx;
878 +
879 + return rval;
880 +}
881 +
882 +
883 +static void ar231x_tx_int(struct net_device *dev)
884 +{
885 + struct ar231x_private *sp = netdev_priv(dev);
886 + u32 idx;
887 + struct sk_buff *skb;
888 + ar231x_descr_t *txdesc;
889 + unsigned int status = 0;
890 +
891 + idx = sp->tx_csm;
892 +
893 + while (idx != sp->tx_prd) {
894 + txdesc = &sp->tx_ring[idx];
895 + status = txdesc->status;
896 +
897 + if (status & DMA_TX_OWN) {
898 + /* ar231x dma still owns descr */
899 + break;
900 + }
901 + /* done with this descriptor */
902 + dma_unmap_single(NULL, txdesc->addr,
903 + txdesc->devcs & DMA_TX1_BSIZE_MASK,
904 + DMA_TO_DEVICE);
905 + txdesc->status = 0;
906 +
907 + if (status & DMA_TX_ERROR) {
908 + dev->stats.tx_errors++;
909 + dev->stats.tx_dropped++;
910 + if (status & DMA_TX_ERR_UNDER)
911 + dev->stats.tx_fifo_errors++;
912 + if (status & DMA_TX_ERR_HB)
913 + dev->stats.tx_heartbeat_errors++;
914 + if (status & (DMA_TX_ERR_LOSS | DMA_TX_ERR_LINK))
915 + dev->stats.tx_carrier_errors++;
916 + if (status & (DMA_TX_ERR_LATE | DMA_TX_ERR_COL |
917 + DMA_TX_ERR_JABBER | DMA_TX_ERR_DEFER))
918 + dev->stats.tx_aborted_errors++;
919 + } else {
920 + /* transmit OK */
921 + dev->stats.tx_packets++;
922 + }
923 +
924 + skb = sp->tx_skb[idx];
925 + sp->tx_skb[idx] = NULL;
926 + idx = DSC_NEXT(idx);
927 + dev->stats.tx_bytes += skb->len;
928 + dev_kfree_skb_irq(skb);
929 + }
930 +
931 + sp->tx_csm = idx;
932 +}
933 +
934 +
935 +static void rx_tasklet_func(unsigned long data)
936 +{
937 + struct net_device *dev = (struct net_device *)data;
938 + struct ar231x_private *sp = netdev_priv(dev);
939 +
940 + if (sp->unloading)
941 + return;
942 +
943 + if (ar231x_rx_int(dev)) {
944 + tasklet_hi_schedule(&sp->rx_tasklet);
945 + } else {
946 + unsigned long flags;
947 +
948 + spin_lock_irqsave(&sp->lock, flags);
949 + sp->dma_regs->intr_ena |= DMA_STATUS_RI;
950 + spin_unlock_irqrestore(&sp->lock, flags);
951 + }
952 +}
953 +
954 +static void rx_schedule(struct net_device *dev)
955 +{
956 + struct ar231x_private *sp = netdev_priv(dev);
957 +
958 + sp->dma_regs->intr_ena &= ~DMA_STATUS_RI;
959 +
960 + tasklet_hi_schedule(&sp->rx_tasklet);
961 +}
962 +
963 +static irqreturn_t ar231x_interrupt(int irq, void *dev_id)
964 +{
965 + struct net_device *dev = (struct net_device *)dev_id;
966 + struct ar231x_private *sp = netdev_priv(dev);
967 + unsigned int status, enabled;
968 +
969 + /* clear interrupt */
970 + /* Don't clear RI bit if currently disabled */
971 + status = sp->dma_regs->status;
972 + enabled = sp->dma_regs->intr_ena;
973 + sp->dma_regs->status = status & enabled;
974 +
975 + if (status & DMA_STATUS_NIS) {
976 + /* normal status */
977 + /**
978 + * Don't schedule rx processing if interrupt
979 + * is already disabled.
980 + */
981 + if (status & enabled & DMA_STATUS_RI) {
982 + /* receive interrupt */
983 + rx_schedule(dev);
984 + }
985 + if (status & DMA_STATUS_TI) {
986 + /* transmit interrupt */
987 + ar231x_tx_int(dev);
988 + }
989 + }
990 +
991 + /* abnormal status */
992 + if (status & (DMA_STATUS_FBE | DMA_STATUS_TPS))
993 + ar231x_restart(dev);
994 +
995 + return IRQ_HANDLED;
996 +}
997 +
998 +
999 +static int ar231x_open(struct net_device *dev)
1000 +{
1001 + struct ar231x_private *sp = netdev_priv(dev);
1002 + unsigned int ethsal, ethsah;
1003 +
1004 + /* reset the hardware, in case the MAC address changed */
1005 + ethsah = (((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
1006 + (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF);
1007 +
1008 + ethsal = (((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
1009 + (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
1010 + (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
1011 + (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF);
1012 +
1013 + sp->eth_regs->mac_addr[0] = ethsah;
1014 + sp->eth_regs->mac_addr[1] = ethsal;
1015 +
1016 + mdelay(10);
1017 +
1018 + dev->mtu = 1500;
1019 + netif_start_queue(dev);
1020 +
1021 + sp->eth_regs->mac_control |= MAC_CONTROL_RE;
1022 +
1023 + return 0;
1024 +}
1025 +
1026 +static void ar231x_tx_timeout(struct net_device *dev)
1027 +{
1028 + struct ar231x_private *sp = netdev_priv(dev);
1029 + unsigned long flags;
1030 +
1031 + spin_lock_irqsave(&sp->lock, flags);
1032 + ar231x_restart(dev);
1033 + spin_unlock_irqrestore(&sp->lock, flags);
1034 +}
1035 +
1036 +static void ar231x_halt(struct net_device *dev)
1037 +{
1038 + struct ar231x_private *sp = netdev_priv(dev);
1039 + int j;
1040 +
1041 + tasklet_disable(&sp->rx_tasklet);
1042 +
1043 + /* kill the MAC */
1044 + sp->eth_regs->mac_control &= ~(MAC_CONTROL_RE | /* disable Receives */
1045 + MAC_CONTROL_TE); /* disable Transmits */
1046 + /* stop dma */
1047 + sp->dma_regs->control = 0;
1048 + sp->dma_regs->bus_mode = DMA_BUS_MODE_SWR;
1049 +
1050 + /* place phy and MAC in reset */
1051 + sp->cfg->reset_set(sp->cfg->reset_mac);
1052 + sp->cfg->reset_set(sp->cfg->reset_phy);
1053 +
1054 + /* free buffers on tx ring */
1055 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
1056 + struct sk_buff *skb;
1057 + ar231x_descr_t *txdesc;
1058 +
1059 + txdesc = &sp->tx_ring[j];
1060 + txdesc->descr = 0;
1061 +
1062 + skb = sp->tx_skb[j];
1063 + if (skb) {
1064 + dev_kfree_skb(skb);
1065 + sp->tx_skb[j] = NULL;
1066 + }
1067 + }
1068 +}
1069 +
1070 +/**
1071 + * close should do nothing. Here's why. It's called when
1072 + * 'ifconfig bond0 down' is run. If it calls free_irq then
1073 + * the irq is gone forever ! When bond0 is made 'up' again,
1074 + * the ar231x_open () does not call request_irq (). Worse,
1075 + * the call to ar231x_halt() generates a WDOG reset due to
1076 + * the write to reset register and the box reboots.
1077 + * Commenting this out is good since it allows the
1078 + * system to resume when bond0 is made up again.
1079 + */
1080 +static int ar231x_close(struct net_device *dev)
1081 +{
1082 +#if 0
1083 + /* Disable interrupts */
1084 + disable_irq(dev->irq);
1085 +
1086 + /**
1087 + * Without (or before) releasing irq and stopping hardware, this
1088 + * is an absolute non-sense, by the way. It will be reset instantly
1089 + * by the first irq.
1090 + */
1091 + netif_stop_queue(dev);
1092 +
1093 + /* stop the MAC and DMA engines */
1094 + ar231x_halt(dev);
1095 +
1096 + /* release the interrupt */
1097 + free_irq(dev->irq, dev);
1098 +
1099 +#endif
1100 + return 0;
1101 +}
1102 +
1103 +static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev)
1104 +{
1105 + struct ar231x_private *sp = netdev_priv(dev);
1106 + ar231x_descr_t *td;
1107 + u32 idx;
1108 +
1109 + idx = sp->tx_prd;
1110 + td = &sp->tx_ring[idx];
1111 +
1112 + if (td->status & DMA_TX_OWN) {
1113 + /* free skbuf and lie to the caller that we sent it out */
1114 + dev->stats.tx_dropped++;
1115 + dev_kfree_skb(skb);
1116 +
1117 + /* restart transmitter in case locked */
1118 + sp->dma_regs->xmt_poll = 0;
1119 + return 0;
1120 + }
1121 +
1122 + /* Setup the transmit descriptor. */
1123 + td->devcs = ((skb->len << DMA_TX1_BSIZE_SHIFT) |
1124 + (DMA_TX1_LS | DMA_TX1_IC | DMA_TX1_CHAINED));
1125 + td->addr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
1126 + td->status = DMA_TX_OWN;
1127 +
1128 + /* kick transmitter last */
1129 + sp->dma_regs->xmt_poll = 0;
1130 +
1131 + sp->tx_skb[idx] = skb;
1132 + idx = DSC_NEXT(idx);
1133 + sp->tx_prd = idx;
1134 +
1135 + return 0;
1136 +}
1137 +
1138 +static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1139 +{
1140 + struct ar231x_private *sp = netdev_priv(dev);
1141 + int ret;
1142 +
1143 + switch (cmd) {
1144 + case SIOCETHTOOL:
1145 + spin_lock_irq(&sp->lock);
1146 + ret = phy_ethtool_ioctl(sp->phy_dev, (void *)ifr->ifr_data);
1147 + spin_unlock_irq(&sp->lock);
1148 + return ret;
1149 +
1150 + case SIOCSIFHWADDR:
1151 + if (copy_from_user
1152 + (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
1153 + return -EFAULT;
1154 + return 0;
1155 +
1156 + case SIOCGIFHWADDR:
1157 + if (copy_to_user
1158 + (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
1159 + return -EFAULT;
1160 + return 0;
1161 +
1162 + case SIOCGMIIPHY:
1163 + case SIOCGMIIREG:
1164 + case SIOCSMIIREG:
1165 + return phy_mii_ioctl(sp->phy_dev, ifr, cmd);
1166 +
1167 + default:
1168 + break;
1169 + }
1170 +
1171 + return -EOPNOTSUPP;
1172 +}
1173 +
1174 +static void ar231x_adjust_link(struct net_device *dev)
1175 +{
1176 + struct ar231x_private *sp = netdev_priv(dev);
1177 + unsigned int mc;
1178 +
1179 + if (!sp->phy_dev->link)
1180 + return;
1181 +
1182 + if (sp->phy_dev->duplex != sp->oldduplex) {
1183 + mc = readl(&sp->eth_regs->mac_control);
1184 + mc &= ~(MAC_CONTROL_F | MAC_CONTROL_DRO);
1185 + if (sp->phy_dev->duplex)
1186 + mc |= MAC_CONTROL_F;
1187 + else
1188 + mc |= MAC_CONTROL_DRO;
1189 + writel(mc, &sp->eth_regs->mac_control);
1190 + sp->oldduplex = sp->phy_dev->duplex;
1191 + }
1192 +}
1193 +
1194 +#define MII_ADDR(phy, reg) \
1195 + ((reg << MII_ADDR_REG_SHIFT) | (phy << MII_ADDR_PHY_SHIFT))
1196 +
1197 +static int
1198 +ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
1199 +{
1200 + struct net_device *const dev = bus->priv;
1201 + struct ar231x_private *sp = netdev_priv(dev);
1202 + volatile MII *ethernet = sp->phy_regs;
1203 +
1204 + ethernet->mii_addr = MII_ADDR(phy_addr, regnum);
1205 + while (ethernet->mii_addr & MII_ADDR_BUSY)
1206 + ;
1207 + return ethernet->mii_data >> MII_DATA_SHIFT;
1208 +}
1209 +
1210 +static int
1211 +ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value)
1212 +{
1213 + struct net_device *const dev = bus->priv;
1214 + struct ar231x_private *sp = netdev_priv(dev);
1215 + volatile MII *ethernet = sp->phy_regs;
1216 +
1217 + while (ethernet->mii_addr & MII_ADDR_BUSY)
1218 + ;
1219 + ethernet->mii_data = value << MII_DATA_SHIFT;
1220 + ethernet->mii_addr = MII_ADDR(phy_addr, regnum) | MII_ADDR_WRITE;
1221 +
1222 + return 0;
1223 +}
1224 +
1225 +static int ar231x_mdiobus_reset(struct mii_bus *bus)
1226 +{
1227 + struct net_device *const dev = bus->priv;
1228 +
1229 + ar231x_reset_reg(dev);
1230 +
1231 + return 0;
1232 +}
1233 +
1234 +static int ar231x_mdiobus_probe(struct net_device *dev)
1235 +{
1236 + struct ar231x_private *const sp = netdev_priv(dev);
1237 + struct phy_device *phydev = NULL;
1238 + int phy_addr;
1239 +
1240 + /* find the first (lowest address) PHY on the current MAC's MII bus */
1241 + for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
1242 + if (sp->mii_bus->phy_map[phy_addr]) {
1243 + phydev = sp->mii_bus->phy_map[phy_addr];
1244 + sp->phy = phy_addr;
1245 + break; /* break out with first one found */
1246 + }
1247 +
1248 + if (!phydev) {
1249 + printk(KERN_ERR "ar231x: %s: no PHY found\n", dev->name);
1250 + return -1;
1251 + }
1252 +
1253 + /* now we are supposed to have a proper phydev, to attach to... */
1254 + BUG_ON(!phydev);
1255 + BUG_ON(phydev->attached_dev);
1256 +
1257 + phydev = phy_connect(dev, dev_name(&phydev->dev), &ar231x_adjust_link,
1258 + PHY_INTERFACE_MODE_MII);
1259 +
1260 + if (IS_ERR(phydev)) {
1261 + printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
1262 + return PTR_ERR(phydev);
1263 + }
1264 +
1265 + /* mask with MAC supported features */
1266 + phydev->supported &= (SUPPORTED_10baseT_Half
1267 + | SUPPORTED_10baseT_Full
1268 + | SUPPORTED_100baseT_Half
1269 + | SUPPORTED_100baseT_Full
1270 + | SUPPORTED_Autoneg
1271 + /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
1272 + | SUPPORTED_MII
1273 + | SUPPORTED_TP);
1274 +
1275 + phydev->advertising = phydev->supported;
1276 +
1277 + sp->oldduplex = -1;
1278 + sp->phy_dev = phydev;
1279 +
1280 + printk(KERN_INFO "%s: attached PHY driver [%s] "
1281 + "(mii_bus:phy_addr=%s)\n",
1282 + dev->name, phydev->drv->name, dev_name(&phydev->dev));
1283 +
1284 + return 0;
1285 +}
1286 +
1287 --- /dev/null
1288 +++ b/drivers/net/ethernet/atheros/ar231x/ar231x.h
1289 @@ -0,0 +1,295 @@
1290 +/*
1291 + * ar231x.h: Linux driver for the Atheros AR231x Ethernet device.
1292 + *
1293 + * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
1294 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1295 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1296 + *
1297 + * Thanks to Atheros for providing hardware and documentation
1298 + * enabling me to write this driver.
1299 + *
1300 + * This program is free software; you can redistribute it and/or modify
1301 + * it under the terms of the GNU General Public License as published by
1302 + * the Free Software Foundation; either version 2 of the License, or
1303 + * (at your option) any later version.
1304 + */
1305 +
1306 +#ifndef _AR2313_H_
1307 +#define _AR2313_H_
1308 +
1309 +#include <linux/interrupt.h>
1310 +#include <generated/autoconf.h>
1311 +#include <linux/bitops.h>
1312 +#include <ar231x_platform.h>
1313 +
1314 +/* probe link timer - 5 secs */
1315 +#define LINK_TIMER (5*HZ)
1316 +
1317 +#define IS_DMA_TX_INT(X) (((X) & (DMA_STATUS_TI)) != 0)
1318 +#define IS_DMA_RX_INT(X) (((X) & (DMA_STATUS_RI)) != 0)
1319 +#define IS_DRIVER_OWNED(X) (((X) & (DMA_TX_OWN)) == 0)
1320 +
1321 +#define AR2313_TX_TIMEOUT (HZ/4)
1322 +
1323 +/* Rings */
1324 +#define DSC_RING_ENTRIES_SIZE (AR2313_DESCR_ENTRIES * sizeof(struct desc))
1325 +#define DSC_NEXT(idx) ((idx + 1) & (AR2313_DESCR_ENTRIES - 1))
1326 +
1327 +#define AR2313_MBGET 2
1328 +#define AR2313_MBSET 3
1329 +#define AR2313_PCI_RECONFIG 4
1330 +#define AR2313_PCI_DUMP 5
1331 +#define AR2313_TEST_PANIC 6
1332 +#define AR2313_TEST_NULLPTR 7
1333 +#define AR2313_READ_DATA 8
1334 +#define AR2313_WRITE_DATA 9
1335 +#define AR2313_GET_VERSION 10
1336 +#define AR2313_TEST_HANG 11
1337 +#define AR2313_SYNC 12
1338 +
1339 +#define DMA_RX_ERR_CRC BIT(1)
1340 +#define DMA_RX_ERR_DRIB BIT(2)
1341 +#define DMA_RX_ERR_MII BIT(3)
1342 +#define DMA_RX_EV2 BIT(5)
1343 +#define DMA_RX_ERR_COL BIT(6)
1344 +#define DMA_RX_LONG BIT(7)
1345 +#define DMA_RX_LS BIT(8) /* last descriptor */
1346 +#define DMA_RX_FS BIT(9) /* first descriptor */
1347 +#define DMA_RX_MF BIT(10) /* multicast frame */
1348 +#define DMA_RX_ERR_RUNT BIT(11) /* runt frame */
1349 +#define DMA_RX_ERR_LENGTH BIT(12) /* length error */
1350 +#define DMA_RX_ERR_DESC BIT(14) /* descriptor error */
1351 +#define DMA_RX_ERROR BIT(15) /* error summary */
1352 +#define DMA_RX_LEN_MASK 0x3fff0000
1353 +#define DMA_RX_LEN_SHIFT 16
1354 +#define DMA_RX_FILT BIT(30)
1355 +#define DMA_RX_OWN BIT(31) /* desc owned by DMA controller */
1356 +
1357 +#define DMA_RX1_BSIZE_MASK 0x000007ff
1358 +#define DMA_RX1_BSIZE_SHIFT 0
1359 +#define DMA_RX1_CHAINED BIT(24)
1360 +#define DMA_RX1_RER BIT(25)
1361 +
1362 +#define DMA_TX_ERR_UNDER BIT(1) /* underflow error */
1363 +#define DMA_TX_ERR_DEFER BIT(2) /* excessive deferral */
1364 +#define DMA_TX_COL_MASK 0x78
1365 +#define DMA_TX_COL_SHIFT 3
1366 +#define DMA_TX_ERR_HB BIT(7) /* hearbeat failure */
1367 +#define DMA_TX_ERR_COL BIT(8) /* excessive collisions */
1368 +#define DMA_TX_ERR_LATE BIT(9) /* late collision */
1369 +#define DMA_TX_ERR_LINK BIT(10) /* no carrier */
1370 +#define DMA_TX_ERR_LOSS BIT(11) /* loss of carrier */
1371 +#define DMA_TX_ERR_JABBER BIT(14) /* transmit jabber timeout */
1372 +#define DMA_TX_ERROR BIT(15) /* frame aborted */
1373 +#define DMA_TX_OWN BIT(31) /* descr owned by DMA controller */
1374 +
1375 +#define DMA_TX1_BSIZE_MASK 0x000007ff
1376 +#define DMA_TX1_BSIZE_SHIFT 0
1377 +#define DMA_TX1_CHAINED BIT(24) /* chained descriptors */
1378 +#define DMA_TX1_TER BIT(25) /* transmit end of ring */
1379 +#define DMA_TX1_FS BIT(29) /* first segment */
1380 +#define DMA_TX1_LS BIT(30) /* last segment */
1381 +#define DMA_TX1_IC BIT(31) /* interrupt on completion */
1382 +
1383 +#define RCVPKT_LENGTH(X) (X >> 16) /* Received pkt Length */
1384 +
1385 +#define MAC_CONTROL_RE BIT(2) /* receive enable */
1386 +#define MAC_CONTROL_TE BIT(3) /* transmit enable */
1387 +#define MAC_CONTROL_DC BIT(5) /* Deferral check */
1388 +#define MAC_CONTROL_ASTP BIT(8) /* Auto pad strip */
1389 +#define MAC_CONTROL_DRTY BIT(10) /* Disable retry */
1390 +#define MAC_CONTROL_DBF BIT(11) /* Disable bcast frames */
1391 +#define MAC_CONTROL_LCC BIT(12) /* late collision ctrl */
1392 +#define MAC_CONTROL_HP BIT(13) /* Hash Perfect filtering */
1393 +#define MAC_CONTROL_HASH BIT(14) /* Unicast hash filtering */
1394 +#define MAC_CONTROL_HO BIT(15) /* Hash only filtering */
1395 +#define MAC_CONTROL_PB BIT(16) /* Pass Bad frames */
1396 +#define MAC_CONTROL_IF BIT(17) /* Inverse filtering */
1397 +#define MAC_CONTROL_PR BIT(18) /* promis mode (valid frames only) */
1398 +#define MAC_CONTROL_PM BIT(19) /* pass multicast */
1399 +#define MAC_CONTROL_F BIT(20) /* full-duplex */
1400 +#define MAC_CONTROL_DRO BIT(23) /* Disable Receive Own */
1401 +#define MAC_CONTROL_HBD BIT(28) /* heart-beat disabled (MUST BE SET) */
1402 +#define MAC_CONTROL_BLE BIT(30) /* big endian mode */
1403 +#define MAC_CONTROL_RA BIT(31) /* rcv all (valid and invalid frames) */
1404 +
1405 +#define MII_ADDR_BUSY BIT(0)
1406 +#define MII_ADDR_WRITE BIT(1)
1407 +#define MII_ADDR_REG_SHIFT 6
1408 +#define MII_ADDR_PHY_SHIFT 11
1409 +#define MII_DATA_SHIFT 0
1410 +
1411 +#define FLOW_CONTROL_FCE BIT(1)
1412 +
1413 +#define DMA_BUS_MODE_SWR BIT(0) /* software reset */
1414 +#define DMA_BUS_MODE_BLE BIT(7) /* big endian mode */
1415 +#define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */
1416 +#define DMA_BUS_MODE_DBO BIT(20) /* big-endian descriptors */
1417 +
1418 +#define DMA_STATUS_TI BIT(0) /* transmit interrupt */
1419 +#define DMA_STATUS_TPS BIT(1) /* transmit process stopped */
1420 +#define DMA_STATUS_TU BIT(2) /* transmit buffer unavailable */
1421 +#define DMA_STATUS_TJT BIT(3) /* transmit buffer timeout */
1422 +#define DMA_STATUS_UNF BIT(5) /* transmit underflow */
1423 +#define DMA_STATUS_RI BIT(6) /* receive interrupt */
1424 +#define DMA_STATUS_RU BIT(7) /* receive buffer unavailable */
1425 +#define DMA_STATUS_RPS BIT(8) /* receive process stopped */
1426 +#define DMA_STATUS_ETI BIT(10) /* early transmit interrupt */
1427 +#define DMA_STATUS_FBE BIT(13) /* fatal bus interrupt */
1428 +#define DMA_STATUS_ERI BIT(14) /* early receive interrupt */
1429 +#define DMA_STATUS_AIS BIT(15) /* abnormal interrupt summary */
1430 +#define DMA_STATUS_NIS BIT(16) /* normal interrupt summary */
1431 +#define DMA_STATUS_RS_SHIFT 17 /* receive process state */
1432 +#define DMA_STATUS_TS_SHIFT 20 /* transmit process state */
1433 +#define DMA_STATUS_EB_SHIFT 23 /* error bits */
1434 +
1435 +#define DMA_CONTROL_SR BIT(1) /* start receive */
1436 +#define DMA_CONTROL_ST BIT(13) /* start transmit */
1437 +#define DMA_CONTROL_SF BIT(21) /* store and forward */
1438 +
1439 +
1440 +typedef struct {
1441 + volatile unsigned int status; /* OWN, Device control and status. */
1442 + volatile unsigned int devcs; /* pkt Control bits + Length */
1443 + volatile unsigned int addr; /* Current Address. */
1444 + volatile unsigned int descr; /* Next descriptor in chain. */
1445 +} ar231x_descr_t;
1446 +
1447 +
1448 +
1449 +/**
1450 + * New Combo structure for Both Eth0 AND eth1
1451 + *
1452 + * Don't directly access MII related regs since phy chip could be actually
1453 + * connected to another ethernet block.
1454 + */
1455 +typedef struct {
1456 + volatile unsigned int mac_control; /* 0x00 */
1457 + volatile unsigned int mac_addr[2]; /* 0x04 - 0x08 */
1458 + volatile unsigned int mcast_table[2]; /* 0x0c - 0x10 */
1459 + volatile unsigned int __mii_addr; /* 0x14 */
1460 + volatile unsigned int __mii_data; /* 0x18 */
1461 + volatile unsigned int flow_control; /* 0x1c */
1462 + volatile unsigned int vlan_tag; /* 0x20 */
1463 + volatile unsigned int pad[7]; /* 0x24 - 0x3c */
1464 + volatile unsigned int ucast_table[8]; /* 0x40-0x5c */
1465 +
1466 +} ETHERNET_STRUCT;
1467 +
1468 +typedef struct {
1469 + volatile unsigned int mii_addr;
1470 + volatile unsigned int mii_data;
1471 +} MII;
1472 +
1473 +/********************************************************************
1474 + * Interrupt controller
1475 + ********************************************************************/
1476 +
1477 +typedef struct {
1478 + volatile unsigned int wdog_control; /* 0x08 */
1479 + volatile unsigned int wdog_timer; /* 0x0c */
1480 + volatile unsigned int misc_status; /* 0x10 */
1481 + volatile unsigned int misc_mask; /* 0x14 */
1482 + volatile unsigned int global_status; /* 0x18 */
1483 + volatile unsigned int reserved; /* 0x1c */
1484 + volatile unsigned int reset_control; /* 0x20 */
1485 +} INTERRUPT;
1486 +
1487 +/********************************************************************
1488 + * DMA controller
1489 + ********************************************************************/
1490 +typedef struct {
1491 + volatile unsigned int bus_mode; /* 0x00 (CSR0) */
1492 + volatile unsigned int xmt_poll; /* 0x04 (CSR1) */
1493 + volatile unsigned int rcv_poll; /* 0x08 (CSR2) */
1494 + volatile unsigned int rcv_base; /* 0x0c (CSR3) */
1495 + volatile unsigned int xmt_base; /* 0x10 (CSR4) */
1496 + volatile unsigned int status; /* 0x14 (CSR5) */
1497 + volatile unsigned int control; /* 0x18 (CSR6) */
1498 + volatile unsigned int intr_ena; /* 0x1c (CSR7) */
1499 + volatile unsigned int rcv_missed; /* 0x20 (CSR8) */
1500 + volatile unsigned int reserved[11]; /* 0x24-0x4c (CSR9-19) */
1501 + volatile unsigned int cur_tx_buf_addr; /* 0x50 (CSR20) */
1502 + volatile unsigned int cur_rx_buf_addr; /* 0x50 (CSR21) */
1503 +} DMA;
1504 +
1505 +/**
1506 + * Struct private for the Sibyte.
1507 + *
1508 + * Elements are grouped so variables used by the tx handling goes
1509 + * together, and will go into the same cache lines etc. in order to
1510 + * avoid cache line contention between the rx and tx handling on SMP.
1511 + *
1512 + * Frequently accessed variables are put at the beginning of the
1513 + * struct to help the compiler generate better/shorter code.
1514 + */
1515 +struct ar231x_private {
1516 + struct net_device *dev;
1517 + int version;
1518 + u32 mb[2];
1519 +
1520 + volatile MII *phy_regs;
1521 + volatile ETHERNET_STRUCT *eth_regs;
1522 + volatile DMA *dma_regs;
1523 + struct ar231x_eth *cfg;
1524 +
1525 + spinlock_t lock; /* Serialise access to device */
1526 +
1527 + /* RX and TX descriptors, must be adjacent */
1528 + ar231x_descr_t *rx_ring;
1529 + ar231x_descr_t *tx_ring;
1530 +
1531 +
1532 + struct sk_buff **rx_skb;
1533 + struct sk_buff **tx_skb;
1534 +
1535 + /* RX elements */
1536 + u32 rx_skbprd;
1537 + u32 cur_rx;
1538 +
1539 + /* TX elements */
1540 + u32 tx_prd;
1541 + u32 tx_csm;
1542 +
1543 + /* Misc elements */
1544 + char name[48];
1545 + struct {
1546 + u32 address;
1547 + u32 length;
1548 + char *mapping;
1549 + } desc;
1550 +
1551 +
1552 + struct timer_list link_timer;
1553 + unsigned short phy; /* merlot phy = 1, samsung phy = 0x1f */
1554 + unsigned short mac;
1555 + unsigned short link; /* 0 - link down, 1 - link up */
1556 + u16 phy_data;
1557 +
1558 + struct tasklet_struct rx_tasklet;
1559 + int unloading;
1560 +
1561 + struct phy_device *phy_dev;
1562 + struct mii_bus *mii_bus;
1563 + int oldduplex;
1564 +};
1565 +
1566 +
1567 +/* Prototypes */
1568 +static int ar231x_init(struct net_device *dev);
1569 +#ifdef TX_TIMEOUT
1570 +static void ar231x_tx_timeout(struct net_device *dev);
1571 +#endif
1572 +static int ar231x_restart(struct net_device *dev);
1573 +static void ar231x_load_rx_ring(struct net_device *dev, int bufs);
1574 +static irqreturn_t ar231x_interrupt(int irq, void *dev_id);
1575 +static int ar231x_open(struct net_device *dev);
1576 +static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev);
1577 +static int ar231x_close(struct net_device *dev);
1578 +static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr,
1579 + int cmd);
1580 +static void ar231x_init_cleanup(struct net_device *dev);
1581 +static int ar231x_setup_timer(struct net_device *dev);
1582 +static void ar231x_link_timer_fn(unsigned long data);
1583 +static void ar231x_check_link(struct net_device *dev);
1584 +#endif /* _AR2313_H_ */