160b39b9cd19e2f8bebf1755d6707698fb4ed161
[openwrt/openwrt.git] / target / linux / bcm27xx / patches-5.4 / 950-0355-clk-bcm2835-Disable-v3d-clock.patch
1 From 6c37f43308f29a59bc67d4ed010f8fbbf076ec79 Mon Sep 17 00:00:00 2001
2 From: popcornmix <popcornmix@gmail.com>
3 Date: Tue, 3 Sep 2019 20:28:00 +0100
4 Subject: [PATCH] clk-bcm2835: Disable v3d clock
5
6 This is controlled by firmware, see clk-raspberrypi.c
7
8 Signed-off-by: popcornmix <popcornmix@gmail.com>
9 ---
10 drivers/clk/bcm/clk-bcm2835.c | 30 ++++++++++++------------------
11 1 file changed, 12 insertions(+), 18 deletions(-)
12
13 --- a/drivers/clk/bcm/clk-bcm2835.c
14 +++ b/drivers/clk/bcm/clk-bcm2835.c
15 @@ -1716,16 +1716,12 @@ static const struct bcm2835_clk_desc clk
16 .hold_mask = CM_PLLA_HOLDCORE,
17 .fixed_divider = 1,
18 .flags = CLK_SET_RATE_PARENT),
19 - [BCM2835_PLLA_PER] = REGISTER_PLL_DIV(
20 - SOC_ALL,
21 - .name = "plla_per",
22 - .source_pll = "plla",
23 - .cm_reg = CM_PLLA,
24 - .a2w_reg = A2W_PLLA_PER,
25 - .load_mask = CM_PLLA_LOADPER,
26 - .hold_mask = CM_PLLA_HOLDPER,
27 - .fixed_divider = 1,
28 - .flags = CLK_SET_RATE_PARENT),
29 +
30 + /*
31 + * PLLA_PER is used for gpu clocks. Controlled by firmware, see
32 + * clk-raspberrypi.c.
33 + */
34 +
35 [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV(
36 SOC_ALL,
37 .name = "plla_dsi0",
38 @@ -2003,14 +1999,12 @@ static const struct bcm2835_clk_desc clk
39 .int_bits = 6,
40 .frac_bits = 0,
41 .tcnt_mux = 3),
42 - [BCM2835_CLOCK_V3D] = REGISTER_VPU_CLK(
43 - SOC_ALL,
44 - .name = "v3d",
45 - .ctl_reg = CM_V3DCTL,
46 - .div_reg = CM_V3DDIV,
47 - .int_bits = 4,
48 - .frac_bits = 8,
49 - .tcnt_mux = 4),
50 +
51 + /*
52 + * CLOCK_V3D is used for v3d clock. Controlled by firmware, see
53 + * clk-raspberrypi.c.
54 + */
55 +
56 /*
57 * VPU clock. This doesn't have an enable bit, since it drives
58 * the bus for everything else, and is special so it doesn't need