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bcm27xx-gpu-fw: update to latest version
[openwrt/openwrt.git] / target / linux / bcm27xx / patches-5.4 / 950-0421-ARM-dts-Clean-out-downstream-BCM2711-2838-files.patch
1 From 134e06abd2d002edfdac3561656ab9e8161b29a3 Mon Sep 17 00:00:00 2001
2 From: Phil Elwell <phil@raspberrypi.com>
3 Date: Fri, 31 Jan 2020 16:53:13 +0000
4 Subject: [PATCH] ARM: dts: Clean out downstream BCM2711/2838 files
5
6 Signed-off-by: Phil Elwell <phil@raspberrypi.com>
7 ---
8 arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 157 -----
9 arch/arm/boot/dts/bcm2711-rpi.dtsi | 7 -
10 arch/arm/boot/dts/bcm2711.dtsi | 890 --------------------------
11 arch/arm/boot/dts/bcm2838-rpi.dtsi | 25 -
12 arch/arm/boot/dts/bcm2838.dtsi | 733 ---------------------
13 5 files changed, 1812 deletions(-)
14 delete mode 100644 arch/arm/boot/dts/bcm2711-rpi-4-b.dts
15 delete mode 100644 arch/arm/boot/dts/bcm2711-rpi.dtsi
16 delete mode 100644 arch/arm/boot/dts/bcm2711.dtsi
17 delete mode 100644 arch/arm/boot/dts/bcm2838-rpi.dtsi
18 delete mode 100644 arch/arm/boot/dts/bcm2838.dtsi
19
20 --- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
21 +++ /dev/null
22 @@ -1,157 +0,0 @@
23 -// SPDX-License-Identifier: GPL-2.0
24 -/dts-v1/;
25 -#include "bcm2711.dtsi"
26 -#include "bcm2835-rpi.dtsi"
27 -#include "bcm283x-rpi-usb-peripheral.dtsi"
28 -
29 -/ {
30 - compatible = "raspberrypi,4-model-b", "brcm,bcm2711";
31 - model = "Raspberry Pi 4 Model B";
32 -
33 - chosen {
34 - /* 8250 auxiliary UART instead of pl011 */
35 - stdout-path = "serial1:115200n8";
36 - };
37 -
38 - /* Will be filled by the bootloader */
39 - memory@0 {
40 - device_type = "memory";
41 - reg = <0 0 0>;
42 - };
43 -
44 - aliases {
45 - ethernet0 = &genet;
46 - };
47 -
48 - leds {
49 - act {
50 - gpios = <&gpio 42 GPIO_ACTIVE_HIGH>;
51 - };
52 -
53 - pwr {
54 - label = "PWR";
55 - gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
56 - };
57 - };
58 -
59 - wifi_pwrseq: wifi-pwrseq {
60 - compatible = "mmc-pwrseq-simple";
61 - reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
62 - };
63 -
64 - sd_io_1v8_reg: sd_io_1v8_reg {
65 - compatible = "regulator-gpio";
66 - regulator-name = "vdd-sd-io";
67 - regulator-min-microvolt = <1800000>;
68 - regulator-max-microvolt = <3300000>;
69 - regulator-boot-on;
70 - regulator-always-on;
71 - regulator-settling-time-us = <5000>;
72 - gpios = <&expgpio 4 GPIO_ACTIVE_HIGH>;
73 - states = <1800000 0x1
74 - 3300000 0x0>;
75 - status = "okay";
76 - };
77 -};
78 -
79 -&firmware {
80 - expgpio: gpio {
81 - compatible = "raspberrypi,firmware-gpio";
82 - gpio-controller;
83 - #gpio-cells = <2>;
84 - gpio-line-names = "BT_ON",
85 - "WL_ON",
86 - "PWR_LED_OFF",
87 - "GLOBAL_RESET",
88 - "VDD_SD_IO_SEL",
89 - "CAM_GPIO",
90 - "",
91 - "";
92 - status = "okay";
93 - };
94 -};
95 -
96 -&pwm1 {
97 - pinctrl-names = "default";
98 - pinctrl-0 = <&pwm1_0_gpio40 &pwm1_1_gpio41>;
99 - status = "okay";
100 -};
101 -
102 -/* SDHCI is used to control the SDIO for wireless */
103 -&sdhci {
104 - #address-cells = <1>;
105 - #size-cells = <0>;
106 - pinctrl-names = "default";
107 - pinctrl-0 = <&emmc_gpio34>;
108 - bus-width = <4>;
109 - non-removable;
110 - mmc-pwrseq = <&wifi_pwrseq>;
111 - status = "okay";
112 -
113 - brcmf: wifi@1 {
114 - reg = <1>;
115 - compatible = "brcm,bcm4329-fmac";
116 - };
117 -};
118 -
119 -/* EMMC2 is used to drive the SD card */
120 -&emmc2 {
121 - vqmmc-supply = <&sd_io_1v8_reg>;
122 - broken-cd;
123 - status = "okay";
124 -};
125 -
126 -&genet {
127 - phy-handle = <&phy1>;
128 - phy-mode = "rgmii-rxid";
129 - status = "okay";
130 -};
131 -
132 -&genet_mdio {
133 - phy1: ethernet-phy@1 {
134 - /* No PHY interrupt */
135 - reg = <0x1>;
136 - };
137 -};
138 -
139 -/* uart0 communicates with the BT module */
140 -&uart0 {
141 - pinctrl-names = "default";
142 - pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32>;
143 - uart-has-rtscts;
144 - status = "okay";
145 -
146 - bluetooth {
147 - compatible = "brcm,bcm43438-bt";
148 - max-speed = <2000000>;
149 - shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
150 - };
151 -};
152 -
153 -/* uart1 is mapped to the pin header */
154 -&uart1 {
155 - pinctrl-names = "default";
156 - pinctrl-0 = <&uart1_gpio14>;
157 - status = "okay";
158 -};
159 -
160 -&vchiq {
161 - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
162 -};
163 -
164 -/ {
165 - __overrides__ {
166 - act_led_gpio = <&act_led>,"gpios:4";
167 - act_led_activelow = <&act_led>,"gpios:8";
168 - act_led_trigger = <&act_led>,"linux,default-trigger";
169 -
170 - pwr_led_gpio = <&pwr_led>,"gpios:4";
171 - pwr_led_activelow = <&pwr_led>,"gpios:8";
172 - pwr_led_trigger = <&pwr_led>,"linux,default-trigger";
173 -
174 - eth_led0 = <&phy1>,"led-modes:0";
175 - eth_led1 = <&phy1>,"led-modes:4";
176 -
177 - sd_poll_once = <&emmc2>, "non-removable?";
178 - };
179 -};
180 --- a/arch/arm/boot/dts/bcm2711-rpi.dtsi
181 +++ /dev/null
182 @@ -1,7 +0,0 @@
183 -#include "bcm2708-rpi.dtsi"
184 -#include "bcm2838-rpi.dtsi"
185 -
186 -&v3d {
187 - /* Undo the overwriting by bcm270x.dtsi */
188 - power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>;
189 -};
190 --- a/arch/arm/boot/dts/bcm2711.dtsi
191 +++ /dev/null
192 @@ -1,890 +0,0 @@
193 -// SPDX-License-Identifier: GPL-2.0
194 -#include "bcm283x.dtsi"
195 -
196 -#include <dt-bindings/interrupt-controller/arm-gic.h>
197 -#include <dt-bindings/soc/bcm2835-pm.h>
198 -
199 -/ {
200 - compatible = "brcm,bcm2711";
201 -
202 - #address-cells = <2>;
203 - #size-cells = <1>;
204 -
205 - interrupt-parent = <&gicv2>;
206 -
207 - reserved-memory {
208 - #address-cells = <2>;
209 - #size-cells = <1>;
210 - ranges;
211 -
212 - /*
213 - * arm64 reserves the CMA by default somewhere in ZONE_DMA32,
214 - * that's not good enough for the BCM2711 as some devices can
215 - * only address the lower 1G of memory (ZONE_DMA).
216 - */
217 - linux,cma {
218 - compatible = "shared-dma-pool";
219 - size = <0x2000000>; /* 32MB */
220 - alloc-ranges = <0x0 0x00000000 0x40000000>;
221 - reusable;
222 - linux,cma-default;
223 - };
224 - };
225 -
226 -
227 - soc {
228 - /*
229 - * Defined ranges:
230 - * Common BCM283x peripherals
231 - * BCM2711-specific peripherals
232 - * ARM-local peripherals
233 - */
234 - ranges = <0x7e000000 0x0 0xfe000000 0x01800000>,
235 - <0x7c000000 0x0 0xfc000000 0x02000000>,
236 - <0x40000000 0x0 0xff800000 0x00800000>;
237 - /* Emulate a contiguous 30-bit address range for DMA */
238 - dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>;
239 -
240 - /*
241 - * This node is the provider for the enable-method for
242 - * bringing up secondary cores.
243 - */
244 - local_intc: local_intc@40000000 {
245 - compatible = "brcm,bcm2836-l1-intc";
246 - reg = <0x40000000 0x100>;
247 - };
248 -
249 - gicv2: interrupt-controller@40041000 {
250 - interrupt-controller;
251 - #interrupt-cells = <3>;
252 - compatible = "arm,gic-400";
253 - reg = <0x40041000 0x1000>,
254 - <0x40042000 0x2000>,
255 - <0x40044000 0x2000>,
256 - <0x40046000 0x2000>;
257 - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
258 - IRQ_TYPE_LEVEL_HIGH)>;
259 - };
260 -
261 - dma: dma@7e007000 {
262 - compatible = "brcm,bcm2835-dma";
263 - reg = <0x7e007000 0xb00>;
264 - interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
265 - <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
266 - <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
267 - <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
268 - <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
269 - <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
270 - <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
271 - /* DMA lite 7 - 10 */
272 - <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
273 - <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
274 - <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
275 - <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
276 - interrupt-names = "dma0",
277 - "dma1",
278 - "dma2",
279 - "dma3",
280 - "dma4",
281 - "dma5",
282 - "dma6",
283 - "dma7",
284 - "dma8",
285 - "dma9",
286 - "dma10";
287 - #dma-cells = <1>;
288 - brcm,dma-channel-mask = <0x07f5>;
289 - };
290 -
291 - pm: watchdog@7e100000 {
292 - compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
293 - #power-domain-cells = <1>;
294 - #reset-cells = <1>;
295 - reg = <0x7e100000 0x114>,
296 - <0x7e00a000 0x24>,
297 - <0x7ec11000 0x20>;
298 - clocks = <&clocks BCM2835_CLOCK_V3D>,
299 - <&clocks BCM2835_CLOCK_PERI_IMAGE>,
300 - <&clocks BCM2835_CLOCK_H264>,
301 - <&clocks BCM2835_CLOCK_ISP>;
302 - clock-names = "v3d", "peri_image", "h264", "isp";
303 - system-power-controller;
304 - };
305 -
306 - rng@7e104000 {
307 - interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
308 -
309 - /* RNG is incompatible with brcm,bcm2835-rng */
310 - status = "disabled";
311 - };
312 -
313 - uart2: serial@7e201400 {
314 - compatible = "arm,pl011", "arm,primecell";
315 - reg = <0x7e201400 0x200>;
316 - interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
317 - clocks = <&clocks BCM2835_CLOCK_UART>,
318 - <&clocks BCM2835_CLOCK_VPU>;
319 - clock-names = "uartclk", "apb_pclk";
320 - arm,primecell-periphid = <0x00241011>;
321 - status = "disabled";
322 - };
323 -
324 - uart3: serial@7e201600 {
325 - compatible = "arm,pl011", "arm,primecell";
326 - reg = <0x7e201600 0x200>;
327 - interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
328 - clocks = <&clocks BCM2835_CLOCK_UART>,
329 - <&clocks BCM2835_CLOCK_VPU>;
330 - clock-names = "uartclk", "apb_pclk";
331 - arm,primecell-periphid = <0x00241011>;
332 - status = "disabled";
333 - };
334 -
335 - uart4: serial@7e201800 {
336 - compatible = "arm,pl011", "arm,primecell";
337 - reg = <0x7e201800 0x200>;
338 - interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
339 - clocks = <&clocks BCM2835_CLOCK_UART>,
340 - <&clocks BCM2835_CLOCK_VPU>;
341 - clock-names = "uartclk", "apb_pclk";
342 - arm,primecell-periphid = <0x00241011>;
343 - status = "disabled";
344 - };
345 -
346 - uart5: serial@7e201a00 {
347 - compatible = "arm,pl011", "arm,primecell";
348 - reg = <0x7e201a00 0x200>;
349 - interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
350 - clocks = <&clocks BCM2835_CLOCK_UART>,
351 - <&clocks BCM2835_CLOCK_VPU>;
352 - clock-names = "uartclk", "apb_pclk";
353 - arm,primecell-periphid = <0x00241011>;
354 - status = "disabled";
355 - };
356 -
357 - spi3: spi@7e204600 {
358 - compatible = "brcm,bcm2835-spi";
359 - reg = <0x7e204600 0x0200>;
360 - interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
361 - clocks = <&clocks BCM2835_CLOCK_VPU>;
362 - #address-cells = <1>;
363 - #size-cells = <0>;
364 - status = "disabled";
365 - };
366 -
367 - spi4: spi@7e204800 {
368 - compatible = "brcm,bcm2835-spi";
369 - reg = <0x7e204800 0x0200>;
370 - interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
371 - clocks = <&clocks BCM2835_CLOCK_VPU>;
372 - #address-cells = <1>;
373 - #size-cells = <0>;
374 - status = "disabled";
375 - };
376 -
377 - spi5: spi@7e204a00 {
378 - compatible = "brcm,bcm2835-spi";
379 - reg = <0x7e204a00 0x0200>;
380 - interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
381 - clocks = <&clocks BCM2835_CLOCK_VPU>;
382 - #address-cells = <1>;
383 - #size-cells = <0>;
384 - status = "disabled";
385 - };
386 -
387 - spi6: spi@7e204c00 {
388 - compatible = "brcm,bcm2835-spi";
389 - reg = <0x7e204c00 0x0200>;
390 - interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
391 - clocks = <&clocks BCM2835_CLOCK_VPU>;
392 - #address-cells = <1>;
393 - #size-cells = <0>;
394 - status = "disabled";
395 - };
396 -
397 - i2c3: i2c@7e205600 {
398 - compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
399 - reg = <0x7e205600 0x200>;
400 - interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
401 - clocks = <&clocks BCM2835_CLOCK_VPU>;
402 - #address-cells = <1>;
403 - #size-cells = <0>;
404 - status = "disabled";
405 - };
406 -
407 - i2c4: i2c@7e205800 {
408 - compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
409 - reg = <0x7e205800 0x200>;
410 - interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
411 - clocks = <&clocks BCM2835_CLOCK_VPU>;
412 - #address-cells = <1>;
413 - #size-cells = <0>;
414 - status = "disabled";
415 - };
416 -
417 - i2c5: i2c@7e205a00 {
418 - compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
419 - reg = <0x7e205a00 0x200>;
420 - interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
421 - clocks = <&clocks BCM2835_CLOCK_VPU>;
422 - #address-cells = <1>;
423 - #size-cells = <0>;
424 - status = "disabled";
425 - };
426 -
427 - i2c6: i2c@7e205c00 {
428 - compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
429 - reg = <0x7e205c00 0x200>;
430 - interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
431 - clocks = <&clocks BCM2835_CLOCK_VPU>;
432 - #address-cells = <1>;
433 - #size-cells = <0>;
434 - status = "disabled";
435 - };
436 -
437 - pwm1: pwm@7e20c800 {
438 - compatible = "brcm,bcm2835-pwm";
439 - reg = <0x7e20c800 0x28>;
440 - clocks = <&clocks BCM2835_CLOCK_PWM>;
441 - assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
442 - assigned-clock-rates = <10000000>;
443 - #pwm-cells = <2>;
444 - status = "disabled";
445 - };
446 -
447 - emmc2: emmc2@7e340000 {
448 - compatible = "brcm,bcm2711-emmc2";
449 - reg = <0x7e340000 0x100>;
450 - interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
451 - clocks = <&clocks BCM2711_CLOCK_EMMC2>;
452 - status = "disabled";
453 - };
454 -
455 - hvs@7e400000 {
456 - interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
457 - };
458 - };
459 -
460 - arm-pmu {
461 - compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3";
462 - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
463 - <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
464 - <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
465 - <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
466 - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
467 - };
468 -
469 - timer {
470 - compatible = "arm,armv8-timer";
471 - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
472 - IRQ_TYPE_LEVEL_LOW)>,
473 - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
474 - IRQ_TYPE_LEVEL_LOW)>,
475 - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
476 - IRQ_TYPE_LEVEL_LOW)>,
477 - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
478 - IRQ_TYPE_LEVEL_LOW)>;
479 - /* This only applies to the ARMv7 stub */
480 - arm,cpu-registers-not-fw-configured;
481 - };
482 -
483 - cpus: cpus {
484 - #address-cells = <1>;
485 - #size-cells = <0>;
486 - enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
487 -
488 - cpu0: cpu@0 {
489 - device_type = "cpu";
490 - compatible = "arm,cortex-a72";
491 - reg = <0>;
492 - enable-method = "spin-table";
493 - cpu-release-addr = <0x0 0x000000d8>;
494 - };
495 -
496 - cpu1: cpu@1 {
497 - device_type = "cpu";
498 - compatible = "arm,cortex-a72";
499 - reg = <1>;
500 - enable-method = "spin-table";
501 - cpu-release-addr = <0x0 0x000000e0>;
502 - };
503 -
504 - cpu2: cpu@2 {
505 - device_type = "cpu";
506 - compatible = "arm,cortex-a72";
507 - reg = <2>;
508 - enable-method = "spin-table";
509 - cpu-release-addr = <0x0 0x000000e8>;
510 - };
511 -
512 - cpu3: cpu@3 {
513 - device_type = "cpu";
514 - compatible = "arm,cortex-a72";
515 - reg = <3>;
516 - enable-method = "spin-table";
517 - cpu-release-addr = <0x0 0x000000f0>;
518 - };
519 - };
520 -
521 - scb {
522 - compatible = "simple-bus";
523 - #address-cells = <2>;
524 - #size-cells = <1>;
525 -
526 - ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>;
527 -
528 - genet: ethernet@7d580000 {
529 - compatible = "brcm,bcm2711-genet-v5";
530 - reg = <0x0 0x7d580000 0x10000>;
531 - #address-cells = <0x1>;
532 - #size-cells = <0x1>;
533 - interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
534 - <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
535 - status = "disabled";
536 -
537 - genet_mdio: mdio@e14 {
538 - compatible = "brcm,genet-mdio-v5";
539 - reg = <0xe14 0x8>;
540 - reg-names = "mdio";
541 - #address-cells = <0x0>;
542 - #size-cells = <0x1>;
543 - };
544 - };
545 - };
546 -};
547 -
548 -&clk_osc {
549 - clock-frequency = <54000000>;
550 -};
551 -
552 -&clocks {
553 - compatible = "brcm,bcm2711-cprman";
554 -};
555 -
556 -&cpu_thermal {
557 - coefficients = <(-487) 410040>;
558 -};
559 -
560 -&dsi0 {
561 - interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
562 -};
563 -
564 -&dsi1 {
565 - interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
566 -};
567 -
568 -&gpio {
569 - compatible = "brcm,bcm2711-gpio";
570 - interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
571 - <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
572 - <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
573 - <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
574 -
575 - gpclk0_gpio49: gpclk0_gpio49 {
576 - pin-gpclk {
577 - pins = "gpio49";
578 - function = "alt1";
579 - bias-disable;
580 - };
581 - };
582 - gpclk1_gpio50: gpclk1_gpio50 {
583 - pin-gpclk {
584 - pins = "gpio50";
585 - function = "alt1";
586 - bias-disable;
587 - };
588 - };
589 - gpclk2_gpio51: gpclk2_gpio51 {
590 - pin-gpclk {
591 - pins = "gpio51";
592 - function = "alt1";
593 - bias-disable;
594 - };
595 - };
596 -
597 - i2c0_gpio46: i2c0_gpio46 {
598 - pin-sda {
599 - function = "alt0";
600 - pins = "gpio46";
601 - bias-pull-up;
602 - };
603 - pin-scl {
604 - function = "alt0";
605 - pins = "gpio47";
606 - bias-disable;
607 - };
608 - };
609 - i2c1_gpio46: i2c1_gpio46 {
610 - pin-sda {
611 - function = "alt1";
612 - pins = "gpio46";
613 - bias-pull-up;
614 - };
615 - pin-scl {
616 - function = "alt1";
617 - pins = "gpio47";
618 - bias-disable;
619 - };
620 - };
621 - i2c3_gpio2: i2c3_gpio2 {
622 - pin-sda {
623 - function = "alt5";
624 - pins = "gpio2";
625 - bias-pull-up;
626 - };
627 - pin-scl {
628 - function = "alt5";
629 - pins = "gpio3";
630 - bias-disable;
631 - };
632 - };
633 - i2c3_gpio4: i2c3_gpio4 {
634 - pin-sda {
635 - function = "alt5";
636 - pins = "gpio4";
637 - bias-pull-up;
638 - };
639 - pin-scl {
640 - function = "alt5";
641 - pins = "gpio5";
642 - bias-disable;
643 - };
644 - };
645 - i2c4_gpio6: i2c4_gpio6 {
646 - pin-sda {
647 - function = "alt5";
648 - pins = "gpio6";
649 - bias-pull-up;
650 - };
651 - pin-scl {
652 - function = "alt5";
653 - pins = "gpio7";
654 - bias-disable;
655 - };
656 - };
657 - i2c4_gpio8: i2c4_gpio8 {
658 - pin-sda {
659 - function = "alt5";
660 - pins = "gpio8";
661 - bias-pull-up;
662 - };
663 - pin-scl {
664 - function = "alt5";
665 - pins = "gpio9";
666 - bias-disable;
667 - };
668 - };
669 - i2c5_gpio10: i2c5_gpio10 {
670 - pin-sda {
671 - function = "alt5";
672 - pins = "gpio10";
673 - bias-pull-up;
674 - };
675 - pin-scl {
676 - function = "alt5";
677 - pins = "gpio11";
678 - bias-disable;
679 - };
680 - };
681 - i2c5_gpio12: i2c5_gpio12 {
682 - pin-sda {
683 - function = "alt5";
684 - pins = "gpio12";
685 - bias-pull-up;
686 - };
687 - pin-scl {
688 - function = "alt5";
689 - pins = "gpio13";
690 - bias-disable;
691 - };
692 - };
693 - i2c6_gpio0: i2c6_gpio0 {
694 - pin-sda {
695 - function = "alt5";
696 - pins = "gpio0";
697 - bias-pull-up;
698 - };
699 - pin-scl {
700 - function = "alt5";
701 - pins = "gpio1";
702 - bias-disable;
703 - };
704 - };
705 - i2c6_gpio22: i2c6_gpio22 {
706 - pin-sda {
707 - function = "alt5";
708 - pins = "gpio22";
709 - bias-pull-up;
710 - };
711 - pin-scl {
712 - function = "alt5";
713 - pins = "gpio23";
714 - bias-disable;
715 - };
716 - };
717 - i2c_slave_gpio8: i2c_slave_gpio8 {
718 - pins-i2c-slave {
719 - pins = "gpio8",
720 - "gpio9",
721 - "gpio10",
722 - "gpio11";
723 - function = "alt3";
724 - };
725 - };
726 -
727 - jtag_gpio48: jtag_gpio48 {
728 - pins-jtag {
729 - pins = "gpio48",
730 - "gpio49",
731 - "gpio50",
732 - "gpio51",
733 - "gpio52",
734 - "gpio53";
735 - function = "alt4";
736 - };
737 - };
738 -
739 - mii_gpio28: mii_gpio28 {
740 - pins-mii {
741 - pins = "gpio28",
742 - "gpio29",
743 - "gpio30",
744 - "gpio31";
745 - function = "alt4";
746 - };
747 - };
748 - mii_gpio36: mii_gpio36 {
749 - pins-mii {
750 - pins = "gpio36",
751 - "gpio37",
752 - "gpio38",
753 - "gpio39";
754 - function = "alt5";
755 - };
756 - };
757 -
758 - pcm_gpio50: pcm_gpio50 {
759 - pins-pcm {
760 - pins = "gpio50",
761 - "gpio51",
762 - "gpio52",
763 - "gpio53";
764 - function = "alt2";
765 - };
766 - };
767 -
768 - pwm0_0_gpio12: pwm0_0_gpio12 {
769 - pin-pwm {
770 - pins = "gpio12";
771 - function = "alt0";
772 - bias-disable;
773 - };
774 - };
775 - pwm0_0_gpio18: pwm0_0_gpio18 {
776 - pin-pwm {
777 - pins = "gpio18";
778 - function = "alt5";
779 - bias-disable;
780 - };
781 - };
782 - pwm1_0_gpio40: pwm1_0_gpio40 {
783 - pin-pwm {
784 - pins = "gpio40";
785 - function = "alt0";
786 - bias-disable;
787 - };
788 - };
789 - pwm0_1_gpio13: pwm0_1_gpio13 {
790 - pin-pwm {
791 - pins = "gpio13";
792 - function = "alt0";
793 - bias-disable;
794 - };
795 - };
796 - pwm0_1_gpio19: pwm0_1_gpio19 {
797 - pin-pwm {
798 - pins = "gpio19";
799 - function = "alt5";
800 - bias-disable;
801 - };
802 - };
803 - pwm1_1_gpio41: pwm1_1_gpio41 {
804 - pin-pwm {
805 - pins = "gpio41";
806 - function = "alt0";
807 - bias-disable;
808 - };
809 - };
810 - pwm0_1_gpio45: pwm0_1_gpio45 {
811 - pin-pwm {
812 - pins = "gpio45";
813 - function = "alt0";
814 - bias-disable;
815 - };
816 - };
817 - pwm0_0_gpio52: pwm0_0_gpio52 {
818 - pin-pwm {
819 - pins = "gpio52";
820 - function = "alt1";
821 - bias-disable;
822 - };
823 - };
824 - pwm0_1_gpio53: pwm0_1_gpio53 {
825 - pin-pwm {
826 - pins = "gpio53";
827 - function = "alt1";
828 - bias-disable;
829 - };
830 - };
831 -
832 - rgmii_gpio35: rgmii_gpio35 {
833 - pin-start-stop {
834 - pins = "gpio35";
835 - function = "alt4";
836 - };
837 - pin-rx-ok {
838 - pins = "gpio36";
839 - function = "alt4";
840 - };
841 - };
842 - rgmii_irq_gpio34: rgmii_irq_gpio34 {
843 - pin-irq {
844 - pins = "gpio34";
845 - function = "alt5";
846 - };
847 - };
848 - rgmii_irq_gpio39: rgmii_irq_gpio39 {
849 - pin-irq {
850 - pins = "gpio39";
851 - function = "alt4";
852 - };
853 - };
854 - rgmii_mdio_gpio28: rgmii_mdio_gpio28 {
855 - pins-mdio {
856 - pins = "gpio28",
857 - "gpio29";
858 - function = "alt5";
859 - };
860 - };
861 - rgmii_mdio_gpio37: rgmii_mdio_gpio37 {
862 - pins-mdio {
863 - pins = "gpio37",
864 - "gpio38";
865 - function = "alt4";
866 - };
867 - };
868 -
869 - spi0_gpio46: spi0_gpio46 {
870 - pins-spi {
871 - pins = "gpio46",
872 - "gpio47",
873 - "gpio48",
874 - "gpio49";
875 - function = "alt2";
876 - };
877 - };
878 - spi2_gpio46: spi2_gpio46 {
879 - pins-spi {
880 - pins = "gpio46",
881 - "gpio47",
882 - "gpio48",
883 - "gpio49",
884 - "gpio50";
885 - function = "alt5";
886 - };
887 - };
888 - spi3_gpio0: spi3_gpio0 {
889 - pins-spi {
890 - pins = "gpio0",
891 - "gpio1",
892 - "gpio2",
893 - "gpio3";
894 - function = "alt3";
895 - };
896 - };
897 - spi4_gpio4: spi4_gpio4 {
898 - pins-spi {
899 - pins = "gpio4",
900 - "gpio5",
901 - "gpio6",
902 - "gpio7";
903 - function = "alt3";
904 - };
905 - };
906 - spi5_gpio12: spi5_gpio12 {
907 - pins-spi {
908 - pins = "gpio12",
909 - "gpio13",
910 - "gpio14",
911 - "gpio15";
912 - function = "alt3";
913 - };
914 - };
915 - spi6_gpio18: spi6_gpio18 {
916 - pins-spi {
917 - pins = "gpio18",
918 - "gpio19",
919 - "gpio20",
920 - "gpio21";
921 - function = "alt3";
922 - };
923 - };
924 -
925 - uart2_gpio0: uart2_gpio0 {
926 - pin-tx {
927 - pins = "gpio0";
928 - function = "alt4";
929 - bias-disable;
930 - };
931 - pin-rx {
932 - pins = "gpio1";
933 - function = "alt4";
934 - bias-pull-up;
935 - };
936 - };
937 - uart2_ctsrts_gpio2: uart2_ctsrts_gpio2 {
938 - pin-cts {
939 - pins = "gpio2";
940 - function = "alt4";
941 - bias-pull-up;
942 - };
943 - pin-rts {
944 - pins = "gpio3";
945 - function = "alt4";
946 - bias-disable;
947 - };
948 - };
949 - uart3_gpio4: uart3_gpio4 {
950 - pin-tx {
951 - pins = "gpio4";
952 - function = "alt4";
953 - bias-disable;
954 - };
955 - pin-rx {
956 - pins = "gpio5";
957 - function = "alt4";
958 - bias-pull-up;
959 - };
960 - };
961 - uart3_ctsrts_gpio6: uart3_ctsrts_gpio6 {
962 - pin-cts {
963 - pins = "gpio6";
964 - function = "alt4";
965 - bias-pull-up;
966 - };
967 - pin-rts {
968 - pins = "gpio7";
969 - function = "alt4";
970 - bias-disable;
971 - };
972 - };
973 - uart4_gpio8: uart4_gpio8 {
974 - pin-tx {
975 - pins = "gpio8";
976 - function = "alt4";
977 - bias-disable;
978 - };
979 - pin-rx {
980 - pins = "gpio9";
981 - function = "alt4";
982 - bias-pull-up;
983 - };
984 - };
985 - uart4_ctsrts_gpio10: uart4_ctsrts_gpio10 {
986 - pin-cts {
987 - pins = "gpio10";
988 - function = "alt4";
989 - bias-pull-up;
990 - };
991 - pin-rts {
992 - pins = "gpio11";
993 - function = "alt4";
994 - bias-disable;
995 - };
996 - };
997 - uart5_gpio12: uart5_gpio12 {
998 - pin-tx {
999 - pins = "gpio12";
1000 - function = "alt4";
1001 - bias-disable;
1002 - };
1003 - pin-rx {
1004 - pins = "gpio13";
1005 - function = "alt4";
1006 - bias-pull-up;
1007 - };
1008 - };
1009 - uart5_ctsrts_gpio14: uart5_ctsrts_gpio14 {
1010 - pin-cts {
1011 - pins = "gpio14";
1012 - function = "alt4";
1013 - bias-pull-up;
1014 - };
1015 - pin-rts {
1016 - pins = "gpio15";
1017 - function = "alt4";
1018 - bias-disable;
1019 - };
1020 - };
1021 -};
1022 -
1023 -&i2c0 {
1024 - compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
1025 - interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1026 -};
1027 -
1028 -&i2c1 {
1029 - compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
1030 - interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1031 -};
1032 -
1033 -&mailbox {
1034 - interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1035 -};
1036 -
1037 -&sdhci {
1038 - interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
1039 -};
1040 -
1041 -&sdhost {
1042 - interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1043 -};
1044 -
1045 -&spi {
1046 - interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1047 -};
1048 -
1049 -&spi1 {
1050 - interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1051 -};
1052 -
1053 -&spi2 {
1054 - interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1055 -};
1056 -
1057 -&system_timer {
1058 - interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
1059 - <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1060 - <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
1061 - <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1062 -};
1063 -
1064 -&txp {
1065 - interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1066 -};
1067 -
1068 -&uart0 {
1069 - interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1070 -};
1071 -
1072 -&uart1 {
1073 - interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1074 -};
1075 -
1076 -&usb {
1077 - interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1078 -};
1079 -
1080 -&vec {
1081 - interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1082 -};
1083 --- a/arch/arm/boot/dts/bcm2838-rpi.dtsi
1084 +++ /dev/null
1085 @@ -1,25 +0,0 @@
1086 -// SPDX-License-Identifier: GPL-2.0
1087 -
1088 -/ {
1089 - soc {
1090 - /delete-node/ mailbox@7e00b840;
1091 - };
1092 -};
1093 -
1094 -&scb {
1095 - vchiq: mailbox@7e00b840 {
1096 - compatible = "brcm,bcm2838-vchiq";
1097 - reg = <0 0x7e00b840 0x3c>;
1098 - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
1099 - };
1100 -};
1101 -
1102 -&dma {
1103 - /* The VPU firmware uses DMA channel 11 for VCHIQ */
1104 - brcm,dma-channel-mask = <0x1f5>;
1105 -};
1106 -
1107 -&dma40 {
1108 - /* The VPU firmware DMA channel 11 for VCHIQ */
1109 - brcm,dma-channel-mask = <0x7000>;
1110 -};
1111 --- a/arch/arm/boot/dts/bcm2838.dtsi
1112 +++ /dev/null
1113 @@ -1,733 +0,0 @@
1114 -// SPDX-License-Identifier: GPL-2.0
1115 -#include "bcm283x.dtsi"
1116 -
1117 -#include <dt-bindings/interrupt-controller/arm-gic.h>
1118 -#include <dt-bindings/soc/bcm2835-pm.h>
1119 -
1120 -/ {
1121 - compatible = "brcm,bcm2838";
1122 -
1123 - #address-cells = <2>;
1124 - #size-cells = <1>;
1125 -
1126 - interrupt-parent = <&gicv2>;
1127 -
1128 - soc {
1129 - ranges = <0x7e000000 0x0 0xfe000000 0x01800000>,
1130 - <0x7c000000 0x0 0xfc000000 0x02000000>,
1131 - <0x40000000 0x0 0xff800000 0x00800000>;
1132 - /* Emulate a contiguous 30-bit address range for DMA */
1133 - dma-ranges = <0xc0000000 0x0 0x00000000 0x3c000000>;
1134 -
1135 - /delete-node/ interrupt-controller@7e00f300;
1136 - /delete-node/ v3d@7ec00000;
1137 -
1138 - local_intc: local_intc@40000000 {
1139 - compatible = "brcm,bcm2836-l1-intc";
1140 - reg = <0x40000000 0x100>;
1141 - };
1142 -
1143 - gicv2: interrupt-controller@40041000 {
1144 - interrupt-controller;
1145 - #interrupt-cells = <3>;
1146 - compatible = "arm,gic-400";
1147 - reg = <0x40041000 0x1000>,
1148 - <0x40042000 0x2000>,
1149 - <0x40044000 0x2000>,
1150 - <0x40046000 0x2000>;
1151 - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
1152 - IRQ_TYPE_LEVEL_HIGH)>;
1153 - };
1154 -
1155 - thermal: thermal@7d5d2200 {
1156 - compatible = "brcm,avs-tmon-bcm2838";
1157 - reg = <0x7d5d2200 0x2c>;
1158 - interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
1159 - interrupt-names = "tmon";
1160 - clocks = <&clocks BCM2835_CLOCK_TSENS>;
1161 - #thermal-sensor-cells = <0>;
1162 - status = "okay";
1163 - };
1164 -
1165 - pm: watchdog@7e100000 {
1166 - reg = <0x7e100000 0x114>,
1167 - <0x7e00a000 0x24>,
1168 - <0x7ec11000 0x20>;
1169 - };
1170 -
1171 - rng@7e104000 {
1172 - interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
1173 - };
1174 -
1175 - uart2: serial@7e201400 {
1176 - compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
1177 - reg = <0x7e201400 0x200>;
1178 - interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1179 - clocks = <&clocks BCM2835_CLOCK_UART>,
1180 - <&clocks BCM2835_CLOCK_VPU>;
1181 - clock-names = "uartclk", "apb_pclk";
1182 - arm,primecell-periphid = <0x00241011>;
1183 - status = "disabled";
1184 - };
1185 -
1186 - uart3: serial@7e201600 {
1187 - compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
1188 - reg = <0x7e201600 0x200>;
1189 - interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1190 - clocks = <&clocks BCM2835_CLOCK_UART>,
1191 - <&clocks BCM2835_CLOCK_VPU>;
1192 - clock-names = "uartclk", "apb_pclk";
1193 - arm,primecell-periphid = <0x00241011>;
1194 - status = "disabled";
1195 - };
1196 -
1197 - uart4: serial@7e201800 {
1198 - compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
1199 - reg = <0x7e201800 0x200>;
1200 - interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1201 - clocks = <&clocks BCM2835_CLOCK_UART>,
1202 - <&clocks BCM2835_CLOCK_VPU>;
1203 - clock-names = "uartclk", "apb_pclk";
1204 - arm,primecell-periphid = <0x00241011>;
1205 - status = "disabled";
1206 - };
1207 -
1208 - uart5: serial@7e201a00 {
1209 - compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
1210 - reg = <0x7e201a00 0x200>;
1211 - interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1212 - clocks = <&clocks BCM2835_CLOCK_UART>,
1213 - <&clocks BCM2835_CLOCK_VPU>;
1214 - clock-names = "uartclk", "apb_pclk";
1215 - arm,primecell-periphid = <0x00241011>;
1216 - status = "disabled";
1217 - };
1218 -
1219 - spi@7e204000 {
1220 - reg = <0x7e204000 0x0200>;
1221 - interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1222 - };
1223 -
1224 - spi3: spi@7e204600 {
1225 - compatible = "brcm,bcm2835-spi";
1226 - reg = <0x7e204600 0x0200>;
1227 - interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1228 - clocks = <&clocks BCM2835_CLOCK_VPU>;
1229 - #address-cells = <1>;
1230 - #size-cells = <0>;
1231 - status = "disabled";
1232 - };
1233 -
1234 - spi4: spi@7e204800 {
1235 - compatible = "brcm,bcm2835-spi";
1236 - reg = <0x7e204800 0x0200>;
1237 - interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1238 - clocks = <&clocks BCM2835_CLOCK_VPU>;
1239 - #address-cells = <1>;
1240 - #size-cells = <0>;
1241 - status = "disabled";
1242 - };
1243 -
1244 - spi5: spi@7e204a00 {
1245 - compatible = "brcm,bcm2835-spi";
1246 - reg = <0x7e204a00 0x0200>;
1247 - interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1248 - clocks = <&clocks BCM2835_CLOCK_VPU>;
1249 - #address-cells = <1>;
1250 - #size-cells = <0>;
1251 - status = "disabled";
1252 - };
1253 -
1254 - spi6: spi@7e204c00 {
1255 - compatible = "brcm,bcm2835-spi";
1256 - reg = <0x7e204c00 0x0200>;
1257 - interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1258 - clocks = <&clocks BCM2835_CLOCK_VPU>;
1259 - #address-cells = <1>;
1260 - #size-cells = <0>;
1261 - status = "disabled";
1262 - };
1263 -
1264 - i2c3: i2c@7e205600 {
1265 - compatible = "brcm,bcm2835-i2c";
1266 - reg = <0x7e205600 0x200>;
1267 - interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1268 - clocks = <&clocks BCM2835_CLOCK_VPU>;
1269 - #address-cells = <1>;
1270 - #size-cells = <0>;
1271 - status = "disabled";
1272 - };
1273 -
1274 - i2c4: i2c@7e205800 {
1275 - compatible = "brcm,bcm2835-i2c";
1276 - reg = <0x7e205800 0x200>;
1277 - interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1278 - clocks = <&clocks BCM2835_CLOCK_VPU>;
1279 - #address-cells = <1>;
1280 - #size-cells = <0>;
1281 - status = "disabled";
1282 - };
1283 -
1284 - i2c5: i2c@7e205a00 {
1285 - compatible = "brcm,bcm2835-i2c";
1286 - reg = <0x7e205a00 0x200>;
1287 - interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1288 - clocks = <&clocks BCM2835_CLOCK_VPU>;
1289 - #address-cells = <1>;
1290 - #size-cells = <0>;
1291 - status = "disabled";
1292 - };
1293 -
1294 - i2c6: i2c@7e205c00 {
1295 - compatible = "brcm,bcm2835-i2c";
1296 - reg = <0x7e205c00 0x200>;
1297 - interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1298 - clocks = <&clocks BCM2835_CLOCK_VPU>;
1299 - #address-cells = <1>;
1300 - #size-cells = <0>;
1301 - status = "disabled";
1302 - };
1303 -
1304 - pwm1: pwm@7e20c800 {
1305 - compatible = "brcm,bcm2835-pwm";
1306 - reg = <0x7e20c800 0x28>;
1307 - clocks = <&clocks BCM2835_CLOCK_PWM>;
1308 - assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
1309 - assigned-clock-rates = <10000000>;
1310 - #pwm-cells = <2>;
1311 - status = "disabled";
1312 - };
1313 -
1314 - emmc2: emmc2@7e340000 {
1315 - compatible = "brcm,bcm2711-emmc2";
1316 - status = "okay";
1317 - interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
1318 - clocks = <&clocks BCM2711_CLOCK_EMMC2>;
1319 - reg = <0x7e340000 0x100>;
1320 - };
1321 -
1322 - hvs@7e400000 {
1323 - interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1324 - };
1325 - };
1326 -
1327 - arm-pmu {
1328 - compatible = "arm,cortex-a72-pmu";
1329 - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
1330 - <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
1331 - <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
1332 - <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1333 - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
1334 - };
1335 -
1336 - timer {
1337 - compatible = "arm,armv7-timer";
1338 - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
1339 - IRQ_TYPE_LEVEL_LOW)>,
1340 - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
1341 - IRQ_TYPE_LEVEL_LOW)>,
1342 - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
1343 - IRQ_TYPE_LEVEL_LOW)>,
1344 - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
1345 - IRQ_TYPE_LEVEL_LOW)>;
1346 - arm,cpu-registers-not-fw-configured;
1347 - };
1348 -
1349 - cpus: cpus {
1350 - #address-cells = <1>;
1351 - #size-cells = <0>;
1352 - enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
1353 -
1354 - cpu0: cpu@0 {
1355 - device_type = "cpu";
1356 - compatible = "arm,cortex-a72";
1357 - reg = <0>;
1358 - enable-method = "spin-table";
1359 - cpu-release-addr = <0x0 0x000000d8>;
1360 - };
1361 -
1362 - cpu1: cpu@1 {
1363 - device_type = "cpu";
1364 - compatible = "arm,cortex-a72";
1365 - reg = <1>;
1366 - enable-method = "spin-table";
1367 - cpu-release-addr = <0x0 0x000000e0>;
1368 - };
1369 -
1370 - cpu2: cpu@2 {
1371 - device_type = "cpu";
1372 - compatible = "arm,cortex-a72";
1373 - reg = <2>;
1374 - enable-method = "spin-table";
1375 - cpu-release-addr = <0x0 0x000000e8>;
1376 - };
1377 -
1378 - cpu3: cpu@3 {
1379 - device_type = "cpu";
1380 - compatible = "arm,cortex-a72";
1381 - reg = <3>;
1382 - enable-method = "spin-table";
1383 - cpu-release-addr = <0x0 0x000000f0>;
1384 - };
1385 - };
1386 -
1387 - v3dbus {
1388 - compatible = "simple-bus";
1389 - #address-cells = <1>;
1390 - #size-cells = <2>;
1391 - ranges = <0x7c500000 0x0 0xfc500000 0x0 0x03300000>,
1392 - <0x40000000 0x0 0xff800000 0x0 0x00800000>;
1393 - dma-ranges = <0x00000000 0x0 0x00000000 0x4 0x00000000>;
1394 -
1395 - v3d: v3d@7ec04000 {
1396 - compatible = "brcm,2711-v3d";
1397 - reg =
1398 - <0x7ec00000 0x0 0x4000>,
1399 - <0x7ec04000 0x0 0x4000>;
1400 - reg-names = "hub", "core0";
1401 -
1402 - power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>;
1403 - resets = <&pm BCM2835_RESET_V3D>;
1404 - clocks = <&clocks BCM2835_CLOCK_V3D>;
1405 - interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1406 - status = "okay";
1407 - };
1408 - };
1409 -
1410 - scb: scb {
1411 - compatible = "simple-bus";
1412 - #address-cells = <2>;
1413 - #size-cells = <1>;
1414 -
1415 - ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>,
1416 - <0x0 0x40000000 0x0 0xff800000 0x00800000>,
1417 - <0x6 0x00000000 0x6 0x00000000 0x40000000>,
1418 - <0x0 0x00000000 0x0 0x00000000 0xfc000000>;
1419 - dma-ranges = <0x0 0x00000000 0x0 0x00000000 0xfc000000>;
1420 -
1421 - pcie_0: pcie@7d500000 {
1422 - reg = <0x0 0x7d500000 0x9310>,
1423 - <0x0 0x7e00f300 0x20>;
1424 - msi-controller;
1425 - msi-parent = <&pcie_0>;
1426 - #address-cells = <3>;
1427 - #interrupt-cells = <1>;
1428 - #size-cells = <2>;
1429 - bus-range = <0x0 0x01>;
1430 - compatible = "brcm,bcm2711b0-pcie", // Safe value
1431 - "brcm,bcm2711-pcie",
1432 - "brcm,pci-plat-dev";
1433 - max-link-speed = <2>;
1434 - tot-num-pcie = <1>;
1435 - linux,pci-domain = <0>;
1436 - interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
1437 - <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1438 - interrupt-names = "pcie", "msi";
1439 - interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1440 - interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
1441 - IRQ_TYPE_LEVEL_HIGH
1442 - 0 0 0 2 &gicv2 GIC_SPI 144
1443 - IRQ_TYPE_LEVEL_HIGH
1444 - 0 0 0 3 &gicv2 GIC_SPI 145
1445 - IRQ_TYPE_LEVEL_HIGH
1446 - 0 0 0 4 &gicv2 GIC_SPI 146
1447 - IRQ_TYPE_LEVEL_HIGH>;
1448 -
1449 - /* Map outbound accesses from scb:0x6_00000000-03ffffff
1450 - * to pci:0x0_f8000000-fbffffff
1451 - */
1452 - ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000
1453 - 0x0 0x04000000>;
1454 - /* Map inbound accesses from pci:0x0_00000000..ffffffff
1455 - * to scb:0x0_00000000-ffffffff
1456 - */
1457 - dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
1458 - 0x1 0x00000000>;
1459 - status = "okay";
1460 - };
1461 -
1462 - genet: ethernet@7d580000 {
1463 - compatible = "brcm,bcm2711-genet-v5", "brcm,genet-v5";
1464 - reg = <0x0 0x7d580000 0x10000>;
1465 - #address-cells = <0x1>;
1466 - #size-cells = <0x1>;
1467 - interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
1468 - <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1469 - status = "disabled";
1470 -
1471 - genet_mdio: mdio@e14 {
1472 - #address-cells = <0x0>;
1473 - #size-cells = <0x1>;
1474 - compatible = "brcm,genet-mdio-v5";
1475 - reg = <0xe14 0x8>;
1476 - reg-names = "mdio";
1477 - };
1478 - };
1479 -
1480 - dma40: dma@7e007b00 {
1481 - compatible = "brcm,bcm2838-dma";
1482 - reg = <0x0 0x7e007b00 0x400>;
1483 - interrupts =
1484 - <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, /* dma4 11 */
1485 - <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, /* dma4 12 */
1486 - <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, /* dma4 13 */
1487 - <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; /* dma4 14 */
1488 - interrupt-names = "dma11",
1489 - "dma12",
1490 - "dma13",
1491 - "dma14";
1492 - #dma-cells = <1>;
1493 - brcm,dma-channel-mask = <0x7800>;
1494 - };
1495 - /* DMA4 - 40 bit DMA engines */
1496 -
1497 - xhci: xhci@7e9c0000 {
1498 - compatible = "generic-xhci";
1499 - status = "disabled";
1500 - reg = <0x0 0x7e9c0000 0x100000>;
1501 - interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
1502 - };
1503 -
1504 - hevc-decoder@7eb00000 {
1505 - compatible = "raspberrypi,rpivid-hevc-decoder";
1506 - reg = <0x0 0x7eb00000 0x10000>;
1507 - status = "okay";
1508 - };
1509 -
1510 - rpivid-local-intc@7eb10000 {
1511 - compatible = "raspberrypi,rpivid-local-intc";
1512 - reg = <0x0 0x7eb10000 0x1000>;
1513 - status = "okay";
1514 - interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1515 - };
1516 -
1517 - h264-decoder@7eb20000 {
1518 - compatible = "raspberrypi,rpivid-h264-decoder";
1519 - reg = <0x0 0x7eb20000 0x10000>;
1520 - status = "okay";
1521 - };
1522 -
1523 - vp9-decoder@7eb30000 {
1524 - compatible = "raspberrypi,rpivid-vp9-decoder";
1525 - reg = <0x0 0x7eb30000 0x10000>;
1526 - status = "okay";
1527 - };
1528 - };
1529 -};
1530 -
1531 -&clk_osc {
1532 - clock-frequency = <54000000>;
1533 -};
1534 -
1535 -&clocks {
1536 - compatible = "brcm,bcm2711-cprman";
1537 -};
1538 -
1539 -&cpu_thermal {
1540 - coefficients = <(-487) 410040>;
1541 -};
1542 -
1543 -&dsi0 {
1544 - interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1545 -};
1546 -
1547 -&dsi1 {
1548 - interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1549 -};
1550 -
1551 -&gpio {
1552 - compatible = "brcm,bcm2711-gpio", "brcm,bcm2835-gpio";
1553 -
1554 - gpclk0_gpio49: gpclk0_gpio49 {
1555 - brcm,pins = <49>;
1556 - brcm,function = <BCM2835_FSEL_ALT1>;
1557 - brcm,pull = <BCM2835_PUD_OFF>;
1558 - };
1559 - gpclk1_gpio50: gpclk1_gpio50 {
1560 - brcm,pins = <50>;
1561 - brcm,function = <BCM2835_FSEL_ALT1>;
1562 - brcm,pull = <BCM2835_PUD_OFF>;
1563 - };
1564 - gpclk2_gpio51: gpclk2_gpio51 {
1565 - brcm,pins = <51>;
1566 - brcm,function = <BCM2835_FSEL_ALT1>;
1567 - brcm,pull = <BCM2835_PUD_OFF>;
1568 - };
1569 -
1570 - i2c0_gpio46: i2c0_gpio46 {
1571 - brcm,pins = <46 47>;
1572 - brcm,function = <BCM2835_FSEL_ALT0>;
1573 - };
1574 - i2c1_gpio46: i2c1_gpio46 {
1575 - brcm,pins = <46 47>;
1576 - brcm,function = <BCM2835_FSEL_ALT1>;
1577 - };
1578 - i2c3_gpio2: i2c3_gpio2 {
1579 - brcm,pins = <2 3>;
1580 - brcm,function = <BCM2835_FSEL_ALT5>;
1581 - };
1582 - i2c3_gpio4: i2c3_gpio4 {
1583 - brcm,pins = <4 5>;
1584 - brcm,function = <BCM2835_FSEL_ALT5>;
1585 - };
1586 - i2c4_gpio6: i2c4_gpio6 {
1587 - brcm,pins = <6 7>;
1588 - brcm,function = <BCM2835_FSEL_ALT5>;
1589 - };
1590 - i2c4_gpio8: i2c4_gpio8 {
1591 - brcm,pins = <8 9>;
1592 - brcm,function = <BCM2835_FSEL_ALT5>;
1593 - };
1594 - i2c5_gpio10: i2c5_gpio10 {
1595 - brcm,pins = <10 11>;
1596 - brcm,function = <BCM2835_FSEL_ALT5>;
1597 - };
1598 - i2c5_gpio12: i2c5_gpio12 {
1599 - brcm,pins = <12 13>;
1600 - brcm,function = <BCM2835_FSEL_ALT5>;
1601 - };
1602 - i2c6_gpio0: i2c6_gpio0 {
1603 - brcm,pins = <0 1>;
1604 - brcm,function = <BCM2835_FSEL_ALT5>;
1605 - };
1606 - i2c6_gpio22: i2c6_gpio22 {
1607 - brcm,pins = <22 23>;
1608 - brcm,function = <BCM2835_FSEL_ALT5>;
1609 - };
1610 - i2c_slave_gpio8: i2c_slave_gpio8 {
1611 - brcm,pins = <8 9 10 11>;
1612 - brcm,function = <BCM2835_FSEL_ALT3>;
1613 - };
1614 -
1615 - jtag_gpio48: jtag_gpio48 {
1616 - brcm,pins = <48 49 50 51 52 53>;
1617 - brcm,function = <BCM2835_FSEL_ALT4>;
1618 - };
1619 -
1620 - mii_gpio28: mii_gpio28 {
1621 - brcm,pins = <28 29 30 31>;
1622 - brcm,function = <BCM2835_FSEL_ALT4>;
1623 - };
1624 - mii_gpio36: mii_gpio36 {
1625 - brcm,pins = <36 37 38 39>;
1626 - brcm,function = <BCM2835_FSEL_ALT5>;
1627 - };
1628 -
1629 - pcm_gpio50: pcm_gpio50 {
1630 - brcm,pins = <50 51 52 53>;
1631 - brcm,function = <BCM2835_FSEL_ALT2>;
1632 - };
1633 -
1634 - pwm0_gpio52: pwm0_gpio52 {
1635 - brcm,pins = <52>;
1636 - brcm,function = <BCM2835_FSEL_ALT1>;
1637 - brcm,pull = <BCM2835_PUD_OFF>;
1638 - };
1639 - pwm1_gpio53: pwm1_gpio53 {
1640 - brcm,pins = <53>;
1641 - brcm,function = <BCM2835_FSEL_ALT1>;
1642 - brcm,pull = <BCM2835_PUD_OFF>;
1643 - };
1644 -
1645 - /* The following group consists of:
1646 - * RGMII_START_STOP
1647 - * RGMII_RX_OK
1648 - */
1649 - rgmii_gpio35: rgmii_gpio35 {
1650 - brcm,pins = <35 36>;
1651 - brcm,function = <BCM2835_FSEL_ALT4>;
1652 - };
1653 - rgmii_irq_gpio34: rgmii_irq_gpio34 {
1654 - brcm,pins = <34>;
1655 - brcm,function = <BCM2835_FSEL_ALT5>;
1656 - };
1657 - rgmii_irq_gpio39: rgmii_irq_gpio39 {
1658 - brcm,pins = <39>;
1659 - brcm,function = <BCM2835_FSEL_ALT4>;
1660 - };
1661 - rgmii_mdio_gpio28: rgmii_mdio_gpio28 {
1662 - brcm,pins = <28 29>;
1663 - brcm,function = <BCM2835_FSEL_ALT5>;
1664 - };
1665 - rgmii_mdio_gpio37: rgmii_mdio_gpio37 {
1666 - brcm,pins = <37 38>;
1667 - brcm,function = <BCM2835_FSEL_ALT4>;
1668 - };
1669 -
1670 - spi0_gpio46: spi0_gpio46 {
1671 - brcm,pins = <46 47 48 49>;
1672 - brcm,function = <BCM2835_FSEL_ALT2>;
1673 - };
1674 - spi2_gpio46: spi2_gpio46 {
1675 - brcm,pins = <46 47 48 49 50>;
1676 - brcm,function = <BCM2835_FSEL_ALT5>;
1677 - };
1678 - spi3_gpio0: spi3_gpio0 {
1679 - brcm,pins = <0 1 2 3>;
1680 - brcm,function = <BCM2835_FSEL_ALT3>;
1681 - };
1682 - spi4_gpio4: spi4_gpio4 {
1683 - brcm,pins = <4 5 6 7>;
1684 - brcm,function = <BCM2835_FSEL_ALT3>;
1685 - };
1686 - spi5_gpio12: spi5_gpio12 {
1687 - brcm,pins = <12 13 14 15>;
1688 - brcm,function = <BCM2835_FSEL_ALT3>;
1689 - };
1690 - spi6_gpio18: spi6_gpio18 {
1691 - brcm,pins = <18 19 20 21>;
1692 - brcm,function = <BCM2835_FSEL_ALT3>;
1693 - };
1694 -
1695 - uart2_gpio0: uart2_gpio0 {
1696 - brcm,pins = <0 1>;
1697 - brcm,function = <BCM2835_FSEL_ALT4>;
1698 - brcm,pull = <BCM2835_PUD_OFF BCM2835_PUD_UP>;
1699 - };
1700 - uart2_ctsrts_gpio2: uart2_ctsrts_gpio2 {
1701 - brcm,pins = <2 3>;
1702 - brcm,function = <BCM2835_FSEL_ALT4>;
1703 - brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_OFF>;
1704 - };
1705 - uart3_gpio4: uart3_gpio4 {
1706 - brcm,pins = <4 5>;
1707 - brcm,function = <BCM2835_FSEL_ALT4>;
1708 - brcm,pull = <BCM2835_PUD_OFF BCM2835_PUD_UP>;
1709 - };
1710 - uart3_ctsrts_gpio6: uart3_ctsrts_gpio6 {
1711 - brcm,pins = <6 7>;
1712 - brcm,function = <BCM2835_FSEL_ALT4>;
1713 - brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_OFF>;
1714 - };
1715 - uart4_gpio8: uart4_gpio8 {
1716 - brcm,pins = <8 9>;
1717 - brcm,function = <BCM2835_FSEL_ALT4>;
1718 - brcm,pull = <BCM2835_PUD_OFF BCM2835_PUD_UP>;
1719 - };
1720 - uart4_ctsrts_gpio10: uart4_ctsrts_gpio10 {
1721 - brcm,pins = <10 11>;
1722 - brcm,function = <BCM2835_FSEL_ALT4>;
1723 - brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_OFF>;
1724 - };
1725 - uart5_gpio12: uart5_gpio12 {
1726 - brcm,pins = <12 13>;
1727 - brcm,function = <BCM2835_FSEL_ALT4>;
1728 - brcm,pull = <BCM2835_PUD_OFF BCM2835_PUD_UP>;
1729 - };
1730 - uart5_ctsrts_gpio14: uart5_ctsrts_gpio14 {
1731 - brcm,pins = <14 15>;
1732 - brcm,function = <BCM2835_FSEL_ALT4>;
1733 - brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_OFF>;
1734 - };
1735 -};
1736 -
1737 -&vec {
1738 - interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1739 -};
1740 -
1741 -&usb {
1742 - interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1743 - status = "disabled";
1744 -};
1745 -
1746 -&hdmi {
1747 - interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1748 - <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1749 -};
1750 -
1751 -&uart1 {
1752 - interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1753 -};
1754 -
1755 -&spi1 {
1756 - interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1757 -};
1758 -
1759 -&spi2 {
1760 - interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1761 -};
1762 -
1763 -&csi0 {
1764 - interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1765 -};
1766 -
1767 -&csi1 {
1768 - interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1769 -};
1770 -
1771 -&sdhci {
1772 - interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
1773 -};
1774 -
1775 -&i2c0 {
1776 - interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1777 -};
1778 -
1779 -&i2c1 {
1780 - interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1781 -};
1782 -
1783 -&i2c2 {
1784 - interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1785 -};
1786 -
1787 -&gpio {
1788 - interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1789 - <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1790 - <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1791 - <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1792 -};
1793 -
1794 -&mailbox {
1795 - interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1796 -};
1797 -
1798 -&rng {
1799 - compatible = "brcm,bcm2711-rng200", "brcm,bcm2838-rng200";
1800 -};
1801 -
1802 -&sdhost {
1803 - interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1804 -};
1805 -
1806 -&system_timer {
1807 - interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
1808 - <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1809 - <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
1810 - <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1811 -};
1812 -
1813 -&uart0 {
1814 - interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1815 -};
1816 -
1817 -&dma {
1818 - reg = <0x7e007000 0xb00>;
1819 - interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
1820 - <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1821 - <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
1822 - <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
1823 - <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
1824 - <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
1825 - <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
1826 - <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, /* dmalite 7 */
1827 - <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, /* dmalite 8 */
1828 - <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, /* dmalite 9 */
1829 - <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; /* dmalite 10 */
1830 - interrupt-names = "dma0",
1831 - "dma1",
1832 - "dma2",
1833 - "dma3",
1834 - "dma4",
1835 - "dma5",
1836 - "dma6",
1837 - "dma7",
1838 - "dma8",
1839 - "dma9",
1840 - "dma10";
1841 - brcm,dma-channel-mask = <0x07f5>;
1842 -};
1843 -
1844 -&txp {
1845 - interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1846 -};
OpenWrt Source Repository