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bcm27xx: update patches from RPi foundation
[openwrt/openwrt.git] / target / linux / bcm27xx / patches-5.4 / 950-0472-Add-support-for-merus-amp-soundcard-and-ma120x0p-cod.patch
1 From 76e0edf9676388c58bb5f0d7dda8eb8029926c6d Mon Sep 17 00:00:00 2001
2 From: AMuszkat <ariel.muszkat@gmail.com>
3 Date: Mon, 24 Feb 2020 22:56:59 +0100
4 Subject: [PATCH] Add support for merus-amp soundcard and ma120x0p
5 codec
6
7 correct checkpatch warnings and errors
8
9 Signed-off-by: AMuszkat <ariel.muszkat@gmail.com>
10 ---
11 arch/arm/boot/dts/overlays/Makefile | 1 +
12 arch/arm/boot/dts/overlays/README | 6 +
13 .../boot/dts/overlays/merus-amp-overlay.dts | 60 +
14 sound/soc/bcm/rpi-simple-soundcard.c | 28 +
15 sound/soc/codecs/Kconfig | 8 +
16 sound/soc/codecs/Makefile | 2 +
17 sound/soc/codecs/ma120x0p.c | 1384 +++++++++++++++++
18 7 files changed, 1489 insertions(+)
19 create mode 100644 arch/arm/boot/dts/overlays/merus-amp-overlay.dts
20 create mode 100644 sound/soc/codecs/ma120x0p.c
21
22 --- a/arch/arm/boot/dts/overlays/Makefile
23 +++ b/arch/arm/boot/dts/overlays/Makefile
24 @@ -103,6 +103,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
25 mcp3202.dtbo \
26 mcp342x.dtbo \
27 media-center.dtbo \
28 + merus-amp.dtbo \
29 midi-uart0.dtbo \
30 midi-uart1.dtbo \
31 miniuart-bt.dtbo \
32 --- a/arch/arm/boot/dts/overlays/README
33 +++ b/arch/arm/boot/dts/overlays/README
34 @@ -1662,6 +1662,12 @@ Params: speed Display
35 (default "off")
36
37
38 +Name: merus-amp
39 +Info: Configures the merus-amp audio card
40 +Load: dtoverlay=merus-amp
41 +Params: <None>
42 +
43 +
44 Name: midi-uart0
45 Info: Configures UART0 (ttyAMA0) so that a requested 38.4kbaud actually gets
46 31.25kbaud, the frequency required for MIDI
47 --- /dev/null
48 +++ b/arch/arm/boot/dts/overlays/merus-amp-overlay.dts
49 @@ -0,0 +1,60 @@
50 +// SPDX-License-Identifier: GPL-2.0-only
51 +// Definitions for Infineon Merus-Amp
52 +/dts-v1/;
53 +/plugin/;
54 +#include <dt-bindings/pinctrl/bcm2835.h>
55 +#include <dt-bindings/gpio/gpio.h>
56 +
57 +
58 +/ {
59 + compatible = "brcm,bcm2835";
60 +
61 + fragment@0 {
62 + target = <&i2s>;
63 + __overlay__ {
64 + status = "okay";
65 + };
66 + };
67 +
68 + fragment@1 {
69 + target = <&gpio>;
70 + __overlay__ {
71 + merus_amp_pins: merus_amp_pins {
72 + brcm,pins = <23>;
73 + brcm,function = <0>; /* in */
74 + brcm,pull = <2>; /* up */
75 + };
76 + };
77 + };
78 +
79 + fragment@2 {
80 + target = <&i2c1>;
81 + __overlay__ {
82 + #address-cells = <1>;
83 + #size-cells = <0>;
84 + status = "okay";
85 +
86 + merus_amp: ma120x0p@20 {
87 + #sound-dai-cells = <0>;
88 + compatible = "ma,ma120x0p";
89 + reg = <0x20>;
90 + status = "okay";
91 + pinctrl-names = "default";
92 + pinctrl-0 = <&merus_amp_pins>;
93 + enable_gp-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
94 + mute_gp-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
95 + booster_gp-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
96 + error_gp-gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
97 + };
98 + };
99 + };
100 +
101 + fragment@3 {
102 + target = <&sound>;
103 + __overlay__ {
104 + compatible = "merus,merus-amp";
105 + i2s-controller = <&i2s>;
106 + status = "okay";
107 + };
108 + };
109 +};
110 --- a/sound/soc/bcm/rpi-simple-soundcard.c
111 +++ b/sound/soc/bcm/rpi-simple-soundcard.c
112 @@ -16,6 +16,10 @@
113 * adau1977-adc.c
114 * by Andrey Grodzovsky <andrey2805@gmail.com>
115 *
116 + * merus-amp.c
117 + * by Ariel Muszkat <ariel.muszkat@gmail.com>
118 + * Jorgen Kragh Jakobsen <jorgen.kraghjakobsen@infineon.com>
119 + *
120 * This program is free software; you can redistribute it and/or
121 * modify it under the terms of the GNU General Public License
122 * version 2 as published by the Free Software Foundation.
123 @@ -229,6 +233,28 @@ static struct snd_rpi_simple_drvdata drv
124 .fixed_bclk_ratio = 64,
125 };
126
127 +SND_SOC_DAILINK_DEFS(merus_amp,
128 + DAILINK_COMP_ARRAY(COMP_EMPTY()),
129 + DAILINK_COMP_ARRAY(COMP_CODEC("ma120x0p-amp", "ma120x0p.1-0020")),
130 + DAILINK_COMP_ARRAY(COMP_EMPTY()));
131 +
132 +static struct snd_soc_dai_link snd_merus_amp_dai[] = {
133 + {
134 + .name = "MerusAmp",
135 + .stream_name = "Merus Audio Amp",
136 + .dai_fmt = SND_SOC_DAIFMT_I2S |
137 + SND_SOC_DAIFMT_NB_NF |
138 + SND_SOC_DAIFMT_CBS_CFS,
139 + SND_SOC_DAILINK_REG(merus_amp),
140 + },
141 +};
142 +
143 +static struct snd_rpi_simple_drvdata drvdata_merus_amp = {
144 + .card_name = "snd_rpi_merus_amp",
145 + .dai = snd_merus_amp_dai,
146 + .fixed_bclk_ratio = 64,
147 +};
148 +
149 static const struct of_device_id snd_rpi_simple_of_match[] = {
150 { .compatible = "adi,adau1977-adc",
151 .data = (void *) &drvdata_adau1977 },
152 @@ -241,6 +267,8 @@ static const struct of_device_id snd_rpi
153 { .compatible = "hifiberry,hifiberry-dac",
154 .data = (void *) &drvdata_hifiberry_dac },
155 { .compatible = "rpi,rpi-dac", &drvdata_rpi_dac},
156 + { .compatible = "merus,merus-amp",
157 + .data = (void *) &drvdata_merus_amp },
158 {},
159 };
160
161 --- a/sound/soc/codecs/Kconfig
162 +++ b/sound/soc/codecs/Kconfig
163 @@ -103,6 +103,7 @@ config SND_SOC_ALL_CODECS
164 select SND_SOC_LM4857 if I2C
165 select SND_SOC_LM49453 if I2C
166 select SND_SOC_LOCHNAGAR_SC if MFD_LOCHNAGAR
167 + select SND_SOC_MA120X0P if I2C
168 select SND_SOC_MAX98088 if I2C
169 select SND_SOC_MAX98090 if I2C
170 select SND_SOC_MAX98095 if I2C
171 @@ -732,6 +733,13 @@ config SND_SOC_LOCHNAGAR_SC
172 This driver support the sound card functionality of the Cirrus
173 Logic Lochnagar audio development board.
174
175 +config SND_SOC_MA120X0P
176 + tristate "Infineon Merus(TM) MA120X0P Multilevel Class-D Audio amplifiers"
177 + depends on I2C
178 + help
179 + Enable support for Infineon MA120X0P Multilevel Class-D audio power
180 + amplifiers.
181 +
182 config SND_SOC_MADERA
183 tristate
184 default y if SND_SOC_CS47L15=y
185 --- a/sound/soc/codecs/Makefile
186 +++ b/sound/soc/codecs/Makefile
187 @@ -99,6 +99,7 @@ snd-soc-l3-objs := l3.o
188 snd-soc-lm4857-objs := lm4857.o
189 snd-soc-lm49453-objs := lm49453.o
190 snd-soc-lochnagar-sc-objs := lochnagar-sc.o
191 +snd-soc-ma120x0p-objs := ma120x0p.o
192 snd-soc-madera-objs := madera.o
193 snd-soc-max9759-objs := max9759.o
194 snd-soc-max9768-objs := max9768.o
195 @@ -386,6 +387,7 @@ obj-$(CONFIG_SND_SOC_L3) += snd-soc-l3.o
196 obj-$(CONFIG_SND_SOC_LM4857) += snd-soc-lm4857.o
197 obj-$(CONFIG_SND_SOC_LM49453) += snd-soc-lm49453.o
198 obj-$(CONFIG_SND_SOC_LOCHNAGAR_SC) += snd-soc-lochnagar-sc.o
199 +obj-$(CONFIG_SND_SOC_MA120X0P) += snd-soc-ma120x0p.o
200 obj-$(CONFIG_SND_SOC_MADERA) += snd-soc-madera.o
201 obj-$(CONFIG_SND_SOC_MAX9759) += snd-soc-max9759.o
202 obj-$(CONFIG_SND_SOC_MAX9768) += snd-soc-max9768.o
203 --- /dev/null
204 +++ b/sound/soc/codecs/ma120x0p.c
205 @@ -0,0 +1,1384 @@
206 +// SPDX-License-Identifier: GPL-2.0-or-later
207 +/*
208 + * ASoC Driver for Infineon Merus(TM) ma120x0p multi-level class-D amplifier
209 + *
210 + * Authors: Ariel Muszkat <ariel.muszkat@gmail.com>
211 + * Jorgen Kragh Jakobsen <jorgen.kraghjakobsen@infineon.com>
212 + *
213 + * Copyright (C) 2019 Infineon Technologies AG
214 + *
215 + */
216 +#include <linux/module.h>
217 +#include <linux/moduleparam.h>
218 +#include <linux/init.h>
219 +#include <linux/delay.h>
220 +#include <linux/pm_runtime.h>
221 +#include <linux/i2c.h>
222 +#include <linux/of_device.h>
223 +#include <linux/spi/spi.h>
224 +#include <linux/regmap.h>
225 +#include <linux/regulator/consumer.h>
226 +#include <linux/slab.h>
227 +#include <linux/gpio/consumer.h>
228 +#include <linux/gpio.h>
229 +#include <sound/core.h>
230 +#include <sound/pcm.h>
231 +#include <sound/pcm_params.h>
232 +#include <sound/soc.h>
233 +#include <sound/soc-dapm.h>
234 +#include <sound/initval.h>
235 +#include <sound/tlv.h>
236 +#include <linux/interrupt.h>
237 +
238 +#include <linux/kernel.h>
239 +#include <linux/string.h>
240 +#include <linux/fs.h>
241 +#include <linux/uaccess.h>
242 +
243 +#ifndef _MA120X0P_
244 +#define _MA120X0P_
245 +//------------------------------------------------------------------manualPM---
246 +// Select Manual PowerMode control
247 +#define ma_manualpm__a 0
248 +#define ma_manualpm__len 1
249 +#define ma_manualpm__mask 0x40
250 +#define ma_manualpm__shift 0x06
251 +#define ma_manualpm__reset 0x00
252 +//--------------------------------------------------------------------pm_man---
253 +// manual selected power mode
254 +#define ma_pm_man__a 0
255 +#define ma_pm_man__len 2
256 +#define ma_pm_man__mask 0x30
257 +#define ma_pm_man__shift 0x04
258 +#define ma_pm_man__reset 0x03
259 +//------------------------------------------ ----------------------mthr_1to2---
260 +// mod. index threshold value for pm1=>pm2 change.
261 +#define ma_mthr_1to2__a 1
262 +#define ma_mthr_1to2__len 8
263 +#define ma_mthr_1to2__mask 0xff
264 +#define ma_mthr_1to2__shift 0x00
265 +#define ma_mthr_1to2__reset 0x3c
266 +//-----------------------------------------------------------------mthr_2to1---
267 +// mod. index threshold value for pm2=>pm1 change.
268 +#define ma_mthr_2to1__a 2
269 +#define ma_mthr_2to1__len 8
270 +#define ma_mthr_2to1__mask 0xff
271 +#define ma_mthr_2to1__shift 0x00
272 +#define ma_mthr_2to1__reset 0x32
273 +//-----------------------------------------------------------------mthr_2to3---
274 +// mod. index threshold value for pm2=>pm3 change.
275 +#define ma_mthr_2to3__a 3
276 +#define ma_mthr_2to3__len 8
277 +#define ma_mthr_2to3__mask 0xff
278 +#define ma_mthr_2to3__shift 0x00
279 +#define ma_mthr_2to3__reset 0x5a
280 +//-----------------------------------------------------------------mthr_3to2---
281 +// mod. index threshold value for pm3=>pm2 change.
282 +#define ma_mthr_3to2__a 4
283 +#define ma_mthr_3to2__len 8
284 +#define ma_mthr_3to2__mask 0xff
285 +#define ma_mthr_3to2__shift 0x00
286 +#define ma_mthr_3to2__reset 0x50
287 +//-------------------------------------------------------------pwmclkdiv_nom---
288 +// pwm default clock divider value
289 +#define ma_pwmclkdiv_nom__a 8
290 +#define ma_pwmclkdiv_nom__len 8
291 +#define ma_pwmclkdiv_nom__mask 0xff
292 +#define ma_pwmclkdiv_nom__shift 0x00
293 +#define ma_pwmclkdiv_nom__reset 0x26
294 +//--------- ----------------------------------------------------ocp_latch_en---
295 +// high to use permanently latching level-2 ocp
296 +#define ma_ocp_latch_en__a 10
297 +#define ma_ocp_latch_en__len 1
298 +#define ma_ocp_latch_en__mask 0x02
299 +#define ma_ocp_latch_en__shift 0x01
300 +#define ma_ocp_latch_en__reset 0x00
301 +//---------------------------------------------------------------lf_clamp_en---
302 +// high (default) to enable lf int2+3 clamping on clip
303 +#define ma_lf_clamp_en__a 10
304 +#define ma_lf_clamp_en__len 1
305 +#define ma_lf_clamp_en__mask 0x80
306 +#define ma_lf_clamp_en__shift 0x07
307 +#define ma_lf_clamp_en__reset 0x00
308 +//-------------------------------------------------------pmcfg_btl_b.modtype---
309 +//
310 +#define ma_pmcfg_btl_b__modtype__a 18
311 +#define ma_pmcfg_btl_b__modtype__len 2
312 +#define ma_pmcfg_btl_b__modtype__mask 0x18
313 +#define ma_pmcfg_btl_b__modtype__shift 0x03
314 +#define ma_pmcfg_btl_b__modtype__reset 0x02
315 +//-------------------------------------------------------pmcfg_btl_b.freqdiv---
316 +#define ma_pmcfg_btl_b__freqdiv__a 18
317 +#define ma_pmcfg_btl_b__freqdiv__len 2
318 +#define ma_pmcfg_btl_b__freqdiv__mask 0x06
319 +#define ma_pmcfg_btl_b__freqdiv__shift 0x01
320 +#define ma_pmcfg_btl_b__freqdiv__reset 0x01
321 +//----------------------------------------------------pmcfg_btl_b.lf_gain_ol---
322 +//
323 +#define ma_pmcfg_btl_b__lf_gain_ol__a 18
324 +#define ma_pmcfg_btl_b__lf_gain_ol__len 1
325 +#define ma_pmcfg_btl_b__lf_gain_ol__mask 0x01
326 +#define ma_pmcfg_btl_b__lf_gain_ol__shift 0x00
327 +#define ma_pmcfg_btl_b__lf_gain_ol__reset 0x01
328 +//-------------------------------------------------------pmcfg_btl_c.freqdiv---
329 +//
330 +#define ma_pmcfg_btl_c__freqdiv__a 19
331 +#define ma_pmcfg_btl_c__freqdiv__len 2
332 +#define ma_pmcfg_btl_c__freqdiv__mask 0x06
333 +#define ma_pmcfg_btl_c__freqdiv__shift 0x01
334 +#define ma_pmcfg_btl_c__freqdiv__reset 0x01
335 +//-------------------------------------------------------pmcfg_btl_c.modtype---
336 +//
337 +#define ma_pmcfg_btl_c__modtype__a 19
338 +#define ma_pmcfg_btl_c__modtype__len 2
339 +#define ma_pmcfg_btl_c__modtype__mask 0x18
340 +#define ma_pmcfg_btl_c__modtype__shift 0x03
341 +#define ma_pmcfg_btl_c__modtype__reset 0x01
342 +//----------------------------------------------------pmcfg_btl_c.lf_gain_ol---
343 +//
344 +#define ma_pmcfg_btl_c__lf_gain_ol__a 19
345 +#define ma_pmcfg_btl_c__lf_gain_ol__len 1
346 +#define ma_pmcfg_btl_c__lf_gain_ol__mask 0x01
347 +#define ma_pmcfg_btl_c__lf_gain_ol__shift 0x00
348 +#define ma_pmcfg_btl_c__lf_gain_ol__reset 0x00
349 +//-------------------------------------------------------pmcfg_btl_d.modtype---
350 +//
351 +#define ma_pmcfg_btl_d__modtype__a 20
352 +#define ma_pmcfg_btl_d__modtype__len 2
353 +#define ma_pmcfg_btl_d__modtype__mask 0x18
354 +#define ma_pmcfg_btl_d__modtype__shift 0x03
355 +#define ma_pmcfg_btl_d__modtype__reset 0x02
356 +//-------------------------------------------------------pmcfg_btl_d.freqdiv---
357 +//
358 +#define ma_pmcfg_btl_d__freqdiv__a 20
359 +#define ma_pmcfg_btl_d__freqdiv__len 2
360 +#define ma_pmcfg_btl_d__freqdiv__mask 0x06
361 +#define ma_pmcfg_btl_d__freqdiv__shift 0x01
362 +#define ma_pmcfg_btl_d__freqdiv__reset 0x02
363 +//----------------------------------------------------pmcfg_btl_d.lf_gain_ol---
364 +//
365 +#define ma_pmcfg_btl_d__lf_gain_ol__a 20
366 +#define ma_pmcfg_btl_d__lf_gain_ol__len 1
367 +#define ma_pmcfg_btl_d__lf_gain_ol__mask 0x01
368 +#define ma_pmcfg_btl_d__lf_gain_ol__shift 0x00
369 +#define ma_pmcfg_btl_d__lf_gain_ol__reset 0x00
370 +//------------ -------------------------------------------pmcfg_se_a.modtype---
371 +//
372 +#define ma_pmcfg_se_a__modtype__a 21
373 +#define ma_pmcfg_se_a__modtype__len 2
374 +#define ma_pmcfg_se_a__modtype__mask 0x18
375 +#define ma_pmcfg_se_a__modtype__shift 0x03
376 +#define ma_pmcfg_se_a__modtype__reset 0x01
377 +//--------------------------------------------------------pmcfg_se_a.freqdiv---
378 +//
379 +#define ma_pmcfg_se_a__freqdiv__a 21
380 +#define ma_pmcfg_se_a__freqdiv__len 2
381 +#define ma_pmcfg_se_a__freqdiv__mask 0x06
382 +#define ma_pmcfg_se_a__freqdiv__shift 0x01
383 +#define ma_pmcfg_se_a__freqdiv__reset 0x00
384 +//-----------------------------------------------------pmcfg_se_a.lf_gain_ol---
385 +//
386 +#define ma_pmcfg_se_a__lf_gain_ol__a 21
387 +#define ma_pmcfg_se_a__lf_gain_ol__len 1
388 +#define ma_pmcfg_se_a__lf_gain_ol__mask 0x01
389 +#define ma_pmcfg_se_a__lf_gain_ol__shift 0x00
390 +#define ma_pmcfg_se_a__lf_gain_ol__reset 0x01
391 +//-----------------------------------------------------pmcfg_se_b.lf_gain_ol---
392 +//
393 +#define ma_pmcfg_se_b__lf_gain_ol__a 22
394 +#define ma_pmcfg_se_b__lf_gain_ol__len 1
395 +#define ma_pmcfg_se_b__lf_gain_ol__mask 0x01
396 +#define ma_pmcfg_se_b__lf_gain_ol__shift 0x00
397 +#define ma_pmcfg_se_b__lf_gain_ol__reset 0x00
398 +//--------------------------------------------------------pmcfg_se_b.freqdiv---
399 +//
400 +#define ma_pmcfg_se_b__freqdiv__a 22
401 +#define ma_pmcfg_se_b__freqdiv__len 2
402 +#define ma_pmcfg_se_b__freqdiv__mask 0x06
403 +#define ma_pmcfg_se_b__freqdiv__shift 0x01
404 +#define ma_pmcfg_se_b__freqdiv__reset 0x01
405 +//--------------------------------------------------------pmcfg_se_b.modtype---
406 +//
407 +#define ma_pmcfg_se_b__modtype__a 22
408 +#define ma_pmcfg_se_b__modtype__len 2
409 +#define ma_pmcfg_se_b__modtype__mask 0x18
410 +#define ma_pmcfg_se_b__modtype__shift 0x03
411 +#define ma_pmcfg_se_b__modtype__reset 0x01
412 +//----------------------------------------------------------balwaitcount_pm1---
413 +// pm1 balancing period.
414 +#define ma_balwaitcount_pm1__a 23
415 +#define ma_balwaitcount_pm1__len 8
416 +#define ma_balwaitcount_pm1__mask 0xff
417 +#define ma_balwaitcount_pm1__shift 0x00
418 +#define ma_balwaitcount_pm1__reset 0x14
419 +//----------------------------------------------------------balwaitcount_pm2---
420 +// pm2 balancing period.
421 +#define ma_balwaitcount_pm2__a 24
422 +#define ma_balwaitcount_pm2__len 8
423 +#define ma_balwaitcount_pm2__mask 0xff
424 +#define ma_balwaitcount_pm2__shift 0x00
425 +#define ma_balwaitcount_pm2__reset 0x14
426 +//----------------------------------------------------------balwaitcount_pm3---
427 +// pm3 balancing period.
428 +#define ma_balwaitcount_pm3__a 25
429 +#define ma_balwaitcount_pm3__len 8
430 +#define ma_balwaitcount_pm3__mask 0xff
431 +#define ma_balwaitcount_pm3__shift 0x00
432 +#define ma_balwaitcount_pm3__reset 0x1a
433 +//-------------------------------------------------------------usespread_pm1---
434 +// pm1 pwm spread-spectrum mode on/off.
435 +#define ma_usespread_pm1__a 26
436 +#define ma_usespread_pm1__len 1
437 +#define ma_usespread_pm1__mask 0x40
438 +#define ma_usespread_pm1__shift 0x06
439 +#define ma_usespread_pm1__reset 0x00
440 +//---------------------------------------------------------------dtsteps_pm1---
441 +// pm1 dead time setting [10ns steps].
442 +#define ma_dtsteps_pm1__a 26
443 +#define ma_dtsteps_pm1__len 3
444 +#define ma_dtsteps_pm1__mask 0x38
445 +#define ma_dtsteps_pm1__shift 0x03
446 +#define ma_dtsteps_pm1__reset 0x04
447 +//---------------------------------------------------------------baltype_pm1---
448 +// pm1 balancing sensor scheme.
449 +#define ma_baltype_pm1__a 26
450 +#define ma_baltype_pm1__len 3
451 +#define ma_baltype_pm1__mask 0x07
452 +#define ma_baltype_pm1__shift 0x00
453 +#define ma_baltype_pm1__reset 0x00
454 +//-------------------------------------------------------------usespread_pm2---
455 +// pm2 pwm spread-spectrum mode on/off.
456 +#define ma_usespread_pm2__a 27
457 +#define ma_usespread_pm2__len 1
458 +#define ma_usespread_pm2__mask 0x40
459 +#define ma_usespread_pm2__shift 0x06
460 +#define ma_usespread_pm2__reset 0x00
461 +//---------------------------------------------------------------dtsteps_pm2---
462 +// pm2 dead time setting [10ns steps].
463 +#define ma_dtsteps_pm2__a 27
464 +#define ma_dtsteps_pm2__len 3
465 +#define ma_dtsteps_pm2__mask 0x38
466 +#define ma_dtsteps_pm2__shift 0x03
467 +#define ma_dtsteps_pm2__reset 0x03
468 +//---------------------------------------------------------------baltype_pm2---
469 +// pm2 balancing sensor scheme.
470 +#define ma_baltype_pm2__a 27
471 +#define ma_baltype_pm2__len 3
472 +#define ma_baltype_pm2__mask 0x07
473 +#define ma_baltype_pm2__shift 0x00
474 +#define ma_baltype_pm2__reset 0x01
475 +//-------------------------------------------------------------usespread_pm3---
476 +// pm3 pwm spread-spectrum mode on/off.
477 +#define ma_usespread_pm3__a 28
478 +#define ma_usespread_pm3__len 1
479 +#define ma_usespread_pm3__mask 0x40
480 +#define ma_usespread_pm3__shift 0x06
481 +#define ma_usespread_pm3__reset 0x00
482 +//---------------------------------------------------------------dtsteps_pm3---
483 +// pm3 dead time setting [10ns steps].
484 +#define ma_dtsteps_pm3__a 28
485 +#define ma_dtsteps_pm3__len 3
486 +#define ma_dtsteps_pm3__mask 0x38
487 +#define ma_dtsteps_pm3__shift 0x03
488 +#define ma_dtsteps_pm3__reset 0x01
489 +//---------------------------------------------------------------baltype_pm3---
490 +// pm3 balancing sensor scheme.
491 +#define ma_baltype_pm3__a 28
492 +#define ma_baltype_pm3__len 3
493 +#define ma_baltype_pm3__mask 0x07
494 +#define ma_baltype_pm3__shift 0x00
495 +#define ma_baltype_pm3__reset 0x03
496 +//-----------------------------------------------------------------pmprofile---
497 +// pm profile select. valid presets: 0-1-2-3-4. 5=> custom profile.
498 +#define ma_pmprofile__a 29
499 +#define ma_pmprofile__len 3
500 +#define ma_pmprofile__mask 0x07
501 +#define ma_pmprofile__shift 0x00
502 +#define ma_pmprofile__reset 0x00
503 +//-------------------------------------------------------------------pm3_man---
504 +// custom profile pm3 contents. 0=>a, 1=>b, 2=>c, 3=>d
505 +#define ma_pm3_man__a 30
506 +#define ma_pm3_man__len 2
507 +#define ma_pm3_man__mask 0x30
508 +#define ma_pm3_man__shift 0x04
509 +#define ma_pm3_man__reset 0x02
510 +//-------------------------------------------------------------------pm2_man---
511 +// custom profile pm2 contents. 0=>a, 1=>b, 2=>c, 3=>d
512 +#define ma_pm2_man__a 30
513 +#define ma_pm2_man__len 2
514 +#define ma_pm2_man__mask 0x0c
515 +#define ma_pm2_man__shift 0x02
516 +#define ma_pm2_man__reset 0x03
517 +//-------------------------------------------------------------------pm1_man---
518 +// custom profile pm1 contents. 0=>a, 1=>b, 2=>c, 3=>d
519 +#define ma_pm1_man__a 30
520 +#define ma_pm1_man__len 2
521 +#define ma_pm1_man__mask 0x03
522 +#define ma_pm1_man__shift 0x00
523 +#define ma_pm1_man__reset 0x03
524 +//-----------------------------------------------------------ocp_latch_clear---
525 +// low-high clears current ocp latched condition.
526 +#define ma_ocp_latch_clear__a 32
527 +#define ma_ocp_latch_clear__len 1
528 +#define ma_ocp_latch_clear__mask 0x80
529 +#define ma_ocp_latch_clear__shift 0x07
530 +#define ma_ocp_latch_clear__reset 0x00
531 +//-------------------------------------------------------------audio_in_mode---
532 +// audio input mode; 0-1-2-3-4-5
533 +#define ma_audio_in_mode__a 37
534 +#define ma_audio_in_mode__len 3
535 +#define ma_audio_in_mode__mask 0xe0
536 +#define ma_audio_in_mode__shift 0x05
537 +#define ma_audio_in_mode__reset 0x00
538 +//-----------------------------------------------------------------eh_dcshdn---
539 +// high to enable dc protection
540 +#define ma_eh_dcshdn__a 38
541 +#define ma_eh_dcshdn__len 1
542 +#define ma_eh_dcshdn__mask 0x04
543 +#define ma_eh_dcshdn__shift 0x02
544 +#define ma_eh_dcshdn__reset 0x01
545 +//---------------------------------------------------------audio_in_mode_ext---
546 +// if set, audio_in_mode is controlled from audio_in_mode register. if not set
547 +//audio_in_mode is set from fuse bank setting
548 +#define ma_audio_in_mode_ext__a 39
549 +#define ma_audio_in_mode_ext__len 1
550 +#define ma_audio_in_mode_ext__mask 0x20
551 +#define ma_audio_in_mode_ext__shift 0x05
552 +#define ma_audio_in_mode_ext__reset 0x00
553 +//------------------------------------------------------------------eh_clear---
554 +// flip to clear error registers
555 +#define ma_eh_clear__a 45
556 +#define ma_eh_clear__len 1
557 +#define ma_eh_clear__mask 0x04
558 +#define ma_eh_clear__shift 0x02
559 +#define ma_eh_clear__reset 0x00
560 +//----------------------------------------------------------thermal_compr_en---
561 +// enable otw-contr. input compression?
562 +#define ma_thermal_compr_en__a 45
563 +#define ma_thermal_compr_en__len 1
564 +#define ma_thermal_compr_en__mask 0x20
565 +#define ma_thermal_compr_en__shift 0x05
566 +#define ma_thermal_compr_en__reset 0x01
567 +//---------------------------------------------------------------system_mute---
568 +// 1 = mute system, 0 = normal operation
569 +#define ma_system_mute__a 45
570 +#define ma_system_mute__len 1
571 +#define ma_system_mute__mask 0x40
572 +#define ma_system_mute__shift 0x06
573 +#define ma_system_mute__reset 0x00
574 +//------------------------------------------------------thermal_compr_max_db---
575 +// audio limiter max thermal reduction
576 +#define ma_thermal_compr_max_db__a 46
577 +#define ma_thermal_compr_max_db__len 3
578 +#define ma_thermal_compr_max_db__mask 0x07
579 +#define ma_thermal_compr_max_db__shift 0x00
580 +#define ma_thermal_compr_max_db__reset 0x04
581 +//---------------------------------------------------------audio_proc_enable---
582 +// enable audio proc, bypass if not enabled
583 +#define ma_audio_proc_enable__a 53
584 +#define ma_audio_proc_enable__len 1
585 +#define ma_audio_proc_enable__mask 0x08
586 +#define ma_audio_proc_enable__shift 0x03
587 +#define ma_audio_proc_enable__reset 0x00
588 +//--------------------------------------------------------audio_proc_release---
589 +// 00:slow, 01:normal, 10:fast
590 +#define ma_audio_proc_release__a 53
591 +#define ma_audio_proc_release__len 2
592 +#define ma_audio_proc_release__mask 0x30
593 +#define ma_audio_proc_release__shift 0x04
594 +#define ma_audio_proc_release__reset 0x00
595 +//---------------------------------------------------------audio_proc_attack---
596 +// 00:slow, 01:normal, 10:fast
597 +#define ma_audio_proc_attack__a 53
598 +#define ma_audio_proc_attack__len 2
599 +#define ma_audio_proc_attack__mask 0xc0
600 +#define ma_audio_proc_attack__shift 0x06
601 +#define ma_audio_proc_attack__reset 0x00
602 +//----------------------------------------------------------------i2s_format---
603 +// i2s basic data format, 000 = std. i2s, 001 = left justified (default)
604 +#define ma_i2s_format__a 53
605 +#define ma_i2s_format__len 3
606 +#define ma_i2s_format__mask 0x07
607 +#define ma_i2s_format__shift 0x00
608 +#define ma_i2s_format__reset 0x01
609 +//--------------------------------------------------audio_proc_limiterenable---
610 +// 1: enable limiter, 0: disable limiter
611 +#define ma_audio_proc_limiterenable__a 54
612 +#define ma_audio_proc_limiterenable__len 1
613 +#define ma_audio_proc_limiterenable__mask 0x40
614 +#define ma_audio_proc_limiterenable__shift 0x06
615 +#define ma_audio_proc_limiterenable__reset 0x00
616 +//-----------------------------------------------------------audio_proc_mute---
617 +// 1: mute, 0: unmute
618 +#define ma_audio_proc_mute__a 54
619 +#define ma_audio_proc_mute__len 1
620 +#define ma_audio_proc_mute__mask 0x80
621 +#define ma_audio_proc_mute__shift 0x07
622 +#define ma_audio_proc_mute__reset 0x00
623 +//---------------------------------------------------------------i2s_sck_pol---
624 +// i2s sck polarity cfg. 0 = rising edge data change
625 +#define ma_i2s_sck_pol__a 54
626 +#define ma_i2s_sck_pol__len 1
627 +#define ma_i2s_sck_pol__mask 0x01
628 +#define ma_i2s_sck_pol__shift 0x00
629 +#define ma_i2s_sck_pol__reset 0x01
630 +//-------------------------------------------------------------i2s_framesize---
631 +// i2s word length. 00 = 32bit, 01 = 24bit
632 +#define ma_i2s_framesize__a 54
633 +#define ma_i2s_framesize__len 2
634 +#define ma_i2s_framesize__mask 0x18
635 +#define ma_i2s_framesize__shift 0x03
636 +#define ma_i2s_framesize__reset 0x00
637 +//----------------------------------------------------------------i2s_ws_pol---
638 +// i2s ws polarity. 0 = low first
639 +#define ma_i2s_ws_pol__a 54
640 +#define ma_i2s_ws_pol__len 1
641 +#define ma_i2s_ws_pol__mask 0x02
642 +#define ma_i2s_ws_pol__shift 0x01
643 +#define ma_i2s_ws_pol__reset 0x00
644 +//-----------------------------------------------------------------i2s_order---
645 +// i2s word bit order. 0 = msb first
646 +#define ma_i2s_order__a 54
647 +#define ma_i2s_order__len 1
648 +#define ma_i2s_order__mask 0x04
649 +#define ma_i2s_order__shift 0x02
650 +#define ma_i2s_order__reset 0x00
651 +//------------------------------------------------------------i2s_rightfirst---
652 +// i2s l/r word order; 0 = left first
653 +#define ma_i2s_rightfirst__a 54
654 +#define ma_i2s_rightfirst__len 1
655 +#define ma_i2s_rightfirst__mask 0x20
656 +#define ma_i2s_rightfirst__shift 0x05
657 +#define ma_i2s_rightfirst__reset 0x00
658 +//-------------------------------------------------------------vol_db_master---
659 +// master volume db
660 +#define ma_vol_db_master__a 64
661 +#define ma_vol_db_master__len 8
662 +#define ma_vol_db_master__mask 0xff
663 +#define ma_vol_db_master__shift 0x00
664 +#define ma_vol_db_master__reset 0x18
665 +//------------------------------------------------------------vol_lsb_master---
666 +// master volume lsb 1/4 steps
667 +#define ma_vol_lsb_master__a 65
668 +#define ma_vol_lsb_master__len 2
669 +#define ma_vol_lsb_master__mask 0x03
670 +#define ma_vol_lsb_master__shift 0x00
671 +#define ma_vol_lsb_master__reset 0x00
672 +//----------------------------------------------------------------vol_db_ch0---
673 +// volume channel 0
674 +#define ma_vol_db_ch0__a 66
675 +#define ma_vol_db_ch0__len 8
676 +#define ma_vol_db_ch0__mask 0xff
677 +#define ma_vol_db_ch0__shift 0x00
678 +#define ma_vol_db_ch0__reset 0x18
679 +//----------------------------------------------------------------vol_db_ch1---
680 +// volume channel 1
681 +#define ma_vol_db_ch1__a 67
682 +#define ma_vol_db_ch1__len 8
683 +#define ma_vol_db_ch1__mask 0xff
684 +#define ma_vol_db_ch1__shift 0x00
685 +#define ma_vol_db_ch1__reset 0x18
686 +//----------------------------------------------------------------vol_db_ch2---
687 +// volume channel 2
688 +#define ma_vol_db_ch2__a 68
689 +#define ma_vol_db_ch2__len 8
690 +#define ma_vol_db_ch2__mask 0xff
691 +#define ma_vol_db_ch2__shift 0x00
692 +#define ma_vol_db_ch2__reset 0x18
693 +//----------------------------------------------------------------vol_db_ch3---
694 +// volume channel 3
695 +#define ma_vol_db_ch3__a 69
696 +#define ma_vol_db_ch3__len 8
697 +#define ma_vol_db_ch3__mask 0xff
698 +#define ma_vol_db_ch3__shift 0x00
699 +#define ma_vol_db_ch3__reset 0x18
700 +//---------------------------------------------------------------vol_lsb_ch0---
701 +// volume channel 1 - 1/4 steps
702 +#define ma_vol_lsb_ch0__a 70
703 +#define ma_vol_lsb_ch0__len 2
704 +#define ma_vol_lsb_ch0__mask 0x03
705 +#define ma_vol_lsb_ch0__shift 0x00
706 +#define ma_vol_lsb_ch0__reset 0x00
707 +//---------------------------------------------------------------vol_lsb_ch1---
708 +// volume channel 3 - 1/4 steps
709 +#define ma_vol_lsb_ch1__a 70
710 +#define ma_vol_lsb_ch1__len 2
711 +#define ma_vol_lsb_ch1__mask 0x0c
712 +#define ma_vol_lsb_ch1__shift 0x02
713 +#define ma_vol_lsb_ch1__reset 0x00
714 +//---------------------------------------------------------------vol_lsb_ch2---
715 +// volume channel 2 - 1/4 steps
716 +#define ma_vol_lsb_ch2__a 70
717 +#define ma_vol_lsb_ch2__len 2
718 +#define ma_vol_lsb_ch2__mask 0x30
719 +#define ma_vol_lsb_ch2__shift 0x04
720 +#define ma_vol_lsb_ch2__reset 0x00
721 +//---------------------------------------------------------------vol_lsb_ch3---
722 +// volume channel 3 - 1/4 steps
723 +#define ma_vol_lsb_ch3__a 70
724 +#define ma_vol_lsb_ch3__len 2
725 +#define ma_vol_lsb_ch3__mask 0xc0
726 +#define ma_vol_lsb_ch3__shift 0x06
727 +#define ma_vol_lsb_ch3__reset 0x00
728 +//----------------------------------------------------------------thr_db_ch0---
729 +// thr_db channel 0
730 +#define ma_thr_db_ch0__a 71
731 +#define ma_thr_db_ch0__len 8
732 +#define ma_thr_db_ch0__mask 0xff
733 +#define ma_thr_db_ch0__shift 0x00
734 +#define ma_thr_db_ch0__reset 0x18
735 +//----------------------------------------------------------------thr_db_ch1---
736 +// thr db ch1
737 +#define ma_thr_db_ch1__a 72
738 +#define ma_thr_db_ch1__len 8
739 +#define ma_thr_db_ch1__mask 0xff
740 +#define ma_thr_db_ch1__shift 0x00
741 +#define ma_thr_db_ch1__reset 0x18
742 +//----------------------------------------------------------------thr_db_ch2---
743 +// thr db ch2
744 +#define ma_thr_db_ch2__a 73
745 +#define ma_thr_db_ch2__len 8
746 +#define ma_thr_db_ch2__mask 0xff
747 +#define ma_thr_db_ch2__shift 0x00
748 +#define ma_thr_db_ch2__reset 0x18
749 +//----------------------------------------------------------------thr_db_ch3---
750 +// threshold db ch3
751 +#define ma_thr_db_ch3__a 74
752 +#define ma_thr_db_ch3__len 8
753 +#define ma_thr_db_ch3__mask 0xff
754 +#define ma_thr_db_ch3__shift 0x00
755 +#define ma_thr_db_ch3__reset 0x18
756 +//---------------------------------------------------------------thr_lsb_ch0---
757 +// thr lsb ch0
758 +#define ma_thr_lsb_ch0__a 75
759 +#define ma_thr_lsb_ch0__len 2
760 +#define ma_thr_lsb_ch0__mask 0x03
761 +#define ma_thr_lsb_ch0__shift 0x00
762 +#define ma_thr_lsb_ch0__reset 0x00
763 +//---------------------------------------------------------------thr_lsb_ch1---
764 +// thr lsb ch1
765 +#define ma_thr_lsb_ch1__a 75
766 +#define ma_thr_lsb_ch1__len 2
767 +#define ma_thr_lsb_ch1__mask 0x0c
768 +#define ma_thr_lsb_ch1__shift 0x02
769 +#define ma_thr_lsb_ch1__reset 0x00
770 +//---------------------------------------------------------------thr_lsb_ch2---
771 +// thr lsb ch2 1/4 db step
772 +#define ma_thr_lsb_ch2__a 75
773 +#define ma_thr_lsb_ch2__len 2
774 +#define ma_thr_lsb_ch2__mask 0x30
775 +#define ma_thr_lsb_ch2__shift 0x04
776 +#define ma_thr_lsb_ch2__reset 0x00
777 +//---------------------------------------------------------------thr_lsb_ch3---
778 +// threshold lsb ch3
779 +#define ma_thr_lsb_ch3__a 75
780 +#define ma_thr_lsb_ch3__len 2
781 +#define ma_thr_lsb_ch3__mask 0xc0
782 +#define ma_thr_lsb_ch3__shift 0x06
783 +#define ma_thr_lsb_ch3__reset 0x00
784 +//-----------------------------------------------------------dcu_mon0.pm_mon---
785 +// power mode monitor channel 0
786 +#define ma_dcu_mon0__pm_mon__a 96
787 +#define ma_dcu_mon0__pm_mon__len 2
788 +#define ma_dcu_mon0__pm_mon__mask 0x03
789 +#define ma_dcu_mon0__pm_mon__shift 0x00
790 +#define ma_dcu_mon0__pm_mon__reset 0x00
791 +//-----------------------------------------------------dcu_mon0.freqmode_mon---
792 +// frequence mode monitor channel 0
793 +#define ma_dcu_mon0__freqmode_mon__a 96
794 +#define ma_dcu_mon0__freqmode_mon__len 3
795 +#define ma_dcu_mon0__freqmode_mon__mask 0x70
796 +#define ma_dcu_mon0__freqmode_mon__shift 0x04
797 +#define ma_dcu_mon0__freqmode_mon__reset 0x00
798 +//-------------------------------------------------------dcu_mon0.pps_passed---
799 +// dcu0 pps completion indicator
800 +#define ma_dcu_mon0__pps_passed__a 96
801 +#define ma_dcu_mon0__pps_passed__len 1
802 +#define ma_dcu_mon0__pps_passed__mask 0x80
803 +#define ma_dcu_mon0__pps_passed__shift 0x07
804 +#define ma_dcu_mon0__pps_passed__reset 0x00
805 +//----------------------------------------------------------dcu_mon0.ocp_mon---
806 +// ocp monitor channel 0
807 +#define ma_dcu_mon0__ocp_mon__a 97
808 +#define ma_dcu_mon0__ocp_mon__len 1
809 +#define ma_dcu_mon0__ocp_mon__mask 0x01
810 +#define ma_dcu_mon0__ocp_mon__shift 0x00
811 +#define ma_dcu_mon0__ocp_mon__reset 0x00
812 +//--------------------------------------------------------dcu_mon0.vcfly1_ok---
813 +// cfly1 protection monitor channel 0.
814 +#define ma_dcu_mon0__vcfly1_ok__a 97
815 +#define ma_dcu_mon0__vcfly1_ok__len 1
816 +#define ma_dcu_mon0__vcfly1_ok__mask 0x02
817 +#define ma_dcu_mon0__vcfly1_ok__shift 0x01
818 +#define ma_dcu_mon0__vcfly1_ok__reset 0x00
819 +//--------------------------------------------------------dcu_mon0.vcfly2_ok---
820 +// cfly2 protection monitor channel 0.
821 +#define ma_dcu_mon0__vcfly2_ok__a 97
822 +#define ma_dcu_mon0__vcfly2_ok__len 1
823 +#define ma_dcu_mon0__vcfly2_ok__mask 0x04
824 +#define ma_dcu_mon0__vcfly2_ok__shift 0x02
825 +#define ma_dcu_mon0__vcfly2_ok__reset 0x00
826 +//----------------------------------------------------------dcu_mon0.pvdd_ok---
827 +// dcu0 pvdd monitor
828 +#define ma_dcu_mon0__pvdd_ok__a 97
829 +#define ma_dcu_mon0__pvdd_ok__len 1
830 +#define ma_dcu_mon0__pvdd_ok__mask 0x08
831 +#define ma_dcu_mon0__pvdd_ok__shift 0x03
832 +#define ma_dcu_mon0__pvdd_ok__reset 0x00
833 +//-----------------------------------------------------------dcu_mon0.vdd_ok---
834 +// dcu0 vdd monitor
835 +#define ma_dcu_mon0__vdd_ok__a 97
836 +#define ma_dcu_mon0__vdd_ok__len 1
837 +#define ma_dcu_mon0__vdd_ok__mask 0x10
838 +#define ma_dcu_mon0__vdd_ok__shift 0x04
839 +#define ma_dcu_mon0__vdd_ok__reset 0x00
840 +//-------------------------------------------------------------dcu_mon0.mute---
841 +// dcu0 mute monitor
842 +#define ma_dcu_mon0__mute__a 97
843 +#define ma_dcu_mon0__mute__len 1
844 +#define ma_dcu_mon0__mute__mask 0x20
845 +#define ma_dcu_mon0__mute__shift 0x05
846 +#define ma_dcu_mon0__mute__reset 0x00
847 +//------------------------------------------------------------dcu_mon0.m_mon---
848 +// m sense monitor channel 0
849 +#define ma_dcu_mon0__m_mon__a 98
850 +#define ma_dcu_mon0__m_mon__len 8
851 +#define ma_dcu_mon0__m_mon__mask 0xff
852 +#define ma_dcu_mon0__m_mon__shift 0x00
853 +#define ma_dcu_mon0__m_mon__reset 0x00
854 +//-----------------------------------------------------------dcu_mon1.pm_mon---
855 +// power mode monitor channel 1
856 +#define ma_dcu_mon1__pm_mon__a 100
857 +#define ma_dcu_mon1__pm_mon__len 2
858 +#define ma_dcu_mon1__pm_mon__mask 0x03
859 +#define ma_dcu_mon1__pm_mon__shift 0x00
860 +#define ma_dcu_mon1__pm_mon__reset 0x00
861 +//-----------------------------------------------------dcu_mon1.freqmode_mon---
862 +// frequence mode monitor channel 1
863 +#define ma_dcu_mon1__freqmode_mon__a 100
864 +#define ma_dcu_mon1__freqmode_mon__len 3
865 +#define ma_dcu_mon1__freqmode_mon__mask 0x70
866 +#define ma_dcu_mon1__freqmode_mon__shift 0x04
867 +#define ma_dcu_mon1__freqmode_mon__reset 0x00
868 +//-------------------------------------------------------dcu_mon1.pps_passed---
869 +// dcu1 pps completion indicator
870 +#define ma_dcu_mon1__pps_passed__a 100
871 +#define ma_dcu_mon1__pps_passed__len 1
872 +#define ma_dcu_mon1__pps_passed__mask 0x80
873 +#define ma_dcu_mon1__pps_passed__shift 0x07
874 +#define ma_dcu_mon1__pps_passed__reset 0x00
875 +//----------------------------------------------------------dcu_mon1.ocp_mon---
876 +// ocp monitor channel 1
877 +#define ma_dcu_mon1__ocp_mon__a 101
878 +#define ma_dcu_mon1__ocp_mon__len 1
879 +#define ma_dcu_mon1__ocp_mon__mask 0x01
880 +#define ma_dcu_mon1__ocp_mon__shift 0x00
881 +#define ma_dcu_mon1__ocp_mon__reset 0x00
882 +//--------------------------------------------------------dcu_mon1.vcfly1_ok---
883 +// cfly1 protcetion monitor channel 1
884 +#define ma_dcu_mon1__vcfly1_ok__a 101
885 +#define ma_dcu_mon1__vcfly1_ok__len 1
886 +#define ma_dcu_mon1__vcfly1_ok__mask 0x02
887 +#define ma_dcu_mon1__vcfly1_ok__shift 0x01
888 +#define ma_dcu_mon1__vcfly1_ok__reset 0x00
889 +//--------------------------------------------------------dcu_mon1.vcfly2_ok---
890 +// cfly2 protection monitor channel 1
891 +#define ma_dcu_mon1__vcfly2_ok__a 101
892 +#define ma_dcu_mon1__vcfly2_ok__len 1
893 +#define ma_dcu_mon1__vcfly2_ok__mask 0x04
894 +#define ma_dcu_mon1__vcfly2_ok__shift 0x02
895 +#define ma_dcu_mon1__vcfly2_ok__reset 0x00
896 +//----------------------------------------------------------dcu_mon1.pvdd_ok---
897 +// dcu1 pvdd monitor
898 +#define ma_dcu_mon1__pvdd_ok__a 101
899 +#define ma_dcu_mon1__pvdd_ok__len 1
900 +#define ma_dcu_mon1__pvdd_ok__mask 0x08
901 +#define ma_dcu_mon1__pvdd_ok__shift 0x03
902 +#define ma_dcu_mon1__pvdd_ok__reset 0x00
903 +//-----------------------------------------------------------dcu_mon1.vdd_ok---
904 +// dcu1 vdd monitor
905 +#define ma_dcu_mon1__vdd_ok__a 101
906 +#define ma_dcu_mon1__vdd_ok__len 1
907 +#define ma_dcu_mon1__vdd_ok__mask 0x10
908 +#define ma_dcu_mon1__vdd_ok__shift 0x04
909 +#define ma_dcu_mon1__vdd_ok__reset 0x00
910 +//-------------------------------------------------------------dcu_mon1.mute---
911 +// dcu1 mute monitor
912 +#define ma_dcu_mon1__mute__a 101
913 +#define ma_dcu_mon1__mute__len 1
914 +#define ma_dcu_mon1__mute__mask 0x20
915 +#define ma_dcu_mon1__mute__shift 0x05
916 +#define ma_dcu_mon1__mute__reset 0x00
917 +//------------------------------------------------------------dcu_mon1.m_mon---
918 +// m sense monitor channel 1
919 +#define ma_dcu_mon1__m_mon__a 102
920 +#define ma_dcu_mon1__m_mon__len 8
921 +#define ma_dcu_mon1__m_mon__mask 0xff
922 +#define ma_dcu_mon1__m_mon__shift 0x00
923 +#define ma_dcu_mon1__m_mon__reset 0x00
924 +//--------------------------------------------------------dcu_mon0.sw_enable---
925 +// dcu0 switch enable monitor
926 +#define ma_dcu_mon0__sw_enable__a 104
927 +#define ma_dcu_mon0__sw_enable__len 1
928 +#define ma_dcu_mon0__sw_enable__mask 0x40
929 +#define ma_dcu_mon0__sw_enable__shift 0x06
930 +#define ma_dcu_mon0__sw_enable__reset 0x00
931 +//--------------------------------------------------------dcu_mon1.sw_enable---
932 +// dcu1 switch enable monitor
933 +#define ma_dcu_mon1__sw_enable__a 104
934 +#define ma_dcu_mon1__sw_enable__len 1
935 +#define ma_dcu_mon1__sw_enable__mask 0x80
936 +#define ma_dcu_mon1__sw_enable__shift 0x07
937 +#define ma_dcu_mon1__sw_enable__reset 0x00
938 +//------------------------------------------------------------hvboot0_ok_mon---
939 +// hvboot0_ok for test/debug
940 +#define ma_hvboot0_ok_mon__a 105
941 +#define ma_hvboot0_ok_mon__len 1
942 +#define ma_hvboot0_ok_mon__mask 0x40
943 +#define ma_hvboot0_ok_mon__shift 0x06
944 +#define ma_hvboot0_ok_mon__reset 0x00
945 +//------------------------------------------------------------hvboot1_ok_mon---
946 +// hvboot1_ok for test/debug
947 +#define ma_hvboot1_ok_mon__a 105
948 +#define ma_hvboot1_ok_mon__len 1
949 +#define ma_hvboot1_ok_mon__mask 0x80
950 +#define ma_hvboot1_ok_mon__shift 0x07
951 +#define ma_hvboot1_ok_mon__reset 0x00
952 +//-----------------------------------------------------------------error_acc---
953 +// accumulated errors, at and after triggering
954 +#define ma_error_acc__a 109
955 +#define ma_error_acc__len 8
956 +#define ma_error_acc__mask 0xff
957 +#define ma_error_acc__shift 0x00
958 +#define ma_error_acc__reset 0x00
959 +//-------------------------------------------------------------i2s_data_rate---
960 +// detected i2s data rate: 00/01/10 = x1/x2/x4
961 +#define ma_i2s_data_rate__a 116
962 +#define ma_i2s_data_rate__len 2
963 +#define ma_i2s_data_rate__mask 0x03
964 +#define ma_i2s_data_rate__shift 0x00
965 +#define ma_i2s_data_rate__reset 0x00
966 +//---------------------------------------------------------audio_in_mode_mon---
967 +// audio input mode monitor
968 +#define ma_audio_in_mode_mon__a 116
969 +#define ma_audio_in_mode_mon__len 3
970 +#define ma_audio_in_mode_mon__mask 0x1c
971 +#define ma_audio_in_mode_mon__shift 0x02
972 +#define ma_audio_in_mode_mon__reset 0x00
973 +//------------------------------------------------------------------msel_mon---
974 +// msel[2:0] monitor register
975 +#define ma_msel_mon__a 117
976 +#define ma_msel_mon__len 3
977 +#define ma_msel_mon__mask 0x07
978 +#define ma_msel_mon__shift 0x00
979 +#define ma_msel_mon__reset 0x00
980 +//---------------------------------------------------------------------error---
981 +// current error flag monitor reg - for app. ctrl.
982 +#define ma_error__a 124
983 +#define ma_error__len 8
984 +#define ma_error__mask 0xff
985 +#define ma_error__shift 0x00
986 +#define ma_error__reset 0x00
987 +//----------------------------------------------------audio_proc_limiter_mon---
988 +// b7-b4: channel 3-0 limiter active
989 +#define ma_audio_proc_limiter_mon__a 126
990 +#define ma_audio_proc_limiter_mon__len 4
991 +#define ma_audio_proc_limiter_mon__mask 0xf0
992 +#define ma_audio_proc_limiter_mon__shift 0x04
993 +#define ma_audio_proc_limiter_mon__reset 0x00
994 +//-------------------------------------------------------audio_proc_clip_mon---
995 +// b3-b0: channel 3-0 clipping monitor
996 +#define ma_audio_proc_clip_mon__a 126
997 +#define ma_audio_proc_clip_mon__len 4
998 +#define ma_audio_proc_clip_mon__mask 0x0f
999 +#define ma_audio_proc_clip_mon__shift 0x00
1000 +#define ma_audio_proc_clip_mon__reset 0x00
1001 +#endif
1002 +
1003 +#define SOC_ENUM_ERR(xname, xenum)\
1004 +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
1005 + .access = SNDRV_CTL_ELEM_ACCESS_READ,\
1006 + .info = snd_soc_info_enum_double,\
1007 + .get = snd_soc_get_enum_double, .put = snd_soc_put_enum_double,\
1008 + .private_value = (unsigned long)&(xenum) }
1009 +
1010 +static struct i2c_client *i2c;
1011 +
1012 +struct ma120x0p_priv {
1013 + struct regmap *regmap;
1014 + int mclk_div;
1015 + struct snd_soc_component *component;
1016 + struct gpio_desc *enable_gpio;
1017 + struct gpio_desc *mute_gpio;
1018 + struct gpio_desc *booster_gpio;
1019 + struct gpio_desc *error_gpio;
1020 +};
1021 +
1022 +static struct ma120x0p_priv *priv_data;
1023 +
1024 +//Used to share the IRQ number within this file
1025 +static unsigned int irqNumber;
1026 +
1027 +// Function prototype for the custom IRQ handler function
1028 +static irqreturn_t ma120x0p_irq_handler(int irq, void *data);
1029 +
1030 +//Alsa Controls
1031 +static const char * const limenable_text[] = {"Bypassed", "Enabled"};
1032 +static const char * const limatack_text[] = {"Slow", "Normal", "Fast"};
1033 +static const char * const limrelease_text[] = {"Slow", "Normal", "Fast"};
1034 +
1035 +static const char * const err_flycap_text[] = {"Ok", "Error"};
1036 +static const char * const err_overcurr_text[] = {"Ok", "Error"};
1037 +static const char * const err_pllerr_text[] = {"Ok", "Error"};
1038 +static const char * const err_pvddunder_text[] = {"Ok", "Error"};
1039 +static const char * const err_overtempw_text[] = {"Ok", "Error"};
1040 +static const char * const err_overtempe_text[] = {"Ok", "Error"};
1041 +static const char * const err_pinlowimp_text[] = {"Ok", "Error"};
1042 +static const char * const err_dcprot_text[] = {"Ok", "Error"};
1043 +
1044 +static const char * const pwr_mode_prof_text[] = {"PMF0", "PMF1", "PMF2",
1045 +"PMF3", "PMF4"};
1046 +
1047 +static const struct soc_enum lim_enable_ctrl =
1048 + SOC_ENUM_SINGLE(ma_audio_proc_limiterenable__a,
1049 + ma_audio_proc_limiterenable__shift,
1050 + ma_audio_proc_limiterenable__len + 1,
1051 + limenable_text);
1052 +static const struct soc_enum limatack_ctrl =
1053 + SOC_ENUM_SINGLE(ma_audio_proc_attack__a,
1054 + ma_audio_proc_attack__shift,
1055 + ma_audio_proc_attack__len + 1,
1056 + limatack_text);
1057 +static const struct soc_enum limrelease_ctrl =
1058 + SOC_ENUM_SINGLE(ma_audio_proc_release__a,
1059 + ma_audio_proc_release__shift,
1060 + ma_audio_proc_release__len + 1,
1061 + limrelease_text);
1062 +static const struct soc_enum err_flycap_ctrl =
1063 + SOC_ENUM_SINGLE(ma_error__a, 0, 3, err_flycap_text);
1064 +static const struct soc_enum err_overcurr_ctrl =
1065 + SOC_ENUM_SINGLE(ma_error__a, 1, 3, err_overcurr_text);
1066 +static const struct soc_enum err_pllerr_ctrl =
1067 + SOC_ENUM_SINGLE(ma_error__a, 2, 3, err_pllerr_text);
1068 +static const struct soc_enum err_pvddunder_ctrl =
1069 + SOC_ENUM_SINGLE(ma_error__a, 3, 3, err_pvddunder_text);
1070 +static const struct soc_enum err_overtempw_ctrl =
1071 + SOC_ENUM_SINGLE(ma_error__a, 4, 3, err_overtempw_text);
1072 +static const struct soc_enum err_overtempe_ctrl =
1073 + SOC_ENUM_SINGLE(ma_error__a, 5, 3, err_overtempe_text);
1074 +static const struct soc_enum err_pinlowimp_ctrl =
1075 + SOC_ENUM_SINGLE(ma_error__a, 6, 3, err_pinlowimp_text);
1076 +static const struct soc_enum err_dcprot_ctrl =
1077 + SOC_ENUM_SINGLE(ma_error__a, 7, 3, err_dcprot_text);
1078 +static const struct soc_enum pwr_mode_prof_ctrl =
1079 + SOC_ENUM_SINGLE(ma_pmprofile__a, ma_pmprofile__shift, 5,
1080 + pwr_mode_prof_text);
1081 +
1082 +static const char * const pwr_mode_texts[] = {
1083 + "Dynamic power mode",
1084 + "Power mode 1",
1085 + "Power mode 2",
1086 + "Power mode 3",
1087 + };
1088 +
1089 +static const int pwr_mode_values[] = {
1090 + 0x10,
1091 + 0x50,
1092 + 0x60,
1093 + 0x70,
1094 + };
1095 +
1096 +static const SOC_VALUE_ENUM_SINGLE_DECL(pwr_mode_ctrl,
1097 + ma_pm_man__a, 0, 0x70,
1098 + pwr_mode_texts,
1099 + pwr_mode_values);
1100 +
1101 +static const DECLARE_TLV_DB_SCALE(ma120x0p_vol_tlv, -5000, 100, 0);
1102 +static const DECLARE_TLV_DB_SCALE(ma120x0p_lim_tlv, -5000, 100, 0);
1103 +static const DECLARE_TLV_DB_SCALE(ma120x0p_lr_tlv, -5000, 100, 0);
1104 +
1105 +static const struct snd_kcontrol_new ma120x0p_snd_controls[] = {
1106 + //Master Volume
1107 + SOC_SINGLE_RANGE_TLV("A.Mstr Vol Volume",
1108 + ma_vol_db_master__a, 0, 0x18, 0x4a, 1, ma120x0p_vol_tlv),
1109 +
1110 + //L-R Volume ch0
1111 + SOC_SINGLE_RANGE_TLV("B.L Vol Volume",
1112 + ma_vol_db_ch0__a, 0, 0x18, 0x4a, 1, ma120x0p_lr_tlv),
1113 + SOC_SINGLE_RANGE_TLV("C.R Vol Volume",
1114 + ma_vol_db_ch1__a, 0, 0x18, 0x4a, 1, ma120x0p_lr_tlv),
1115 +
1116 + //L-R Limiter Threshold ch0-ch1
1117 + SOC_DOUBLE_R_RANGE_TLV("D.Lim thresh Volume",
1118 + ma_thr_db_ch0__a, ma_thr_db_ch1__a, 0, 0x0e, 0x4a, 1,
1119 + ma120x0p_lim_tlv),
1120 +
1121 + //Enum Switches/Selectors
1122 + //SOC_ENUM("E.AudioProc Mute", audioproc_mute_ctrl),
1123 + SOC_ENUM("F.Limiter Enable", lim_enable_ctrl),
1124 + SOC_ENUM("G.Limiter Attck", limatack_ctrl),
1125 + SOC_ENUM("H.Limiter Rls", limrelease_ctrl),
1126 +
1127 + //Enum Error Monitor (read-only)
1128 + SOC_ENUM_ERR("I.Err flycap", err_flycap_ctrl),
1129 + SOC_ENUM_ERR("J.Err overcurr", err_overcurr_ctrl),
1130 + SOC_ENUM_ERR("K.Err pllerr", err_pllerr_ctrl),
1131 + SOC_ENUM_ERR("L.Err pvddunder", err_pvddunder_ctrl),
1132 + SOC_ENUM_ERR("M.Err overtempw", err_overtempw_ctrl),
1133 + SOC_ENUM_ERR("N.Err overtempe", err_overtempe_ctrl),
1134 + SOC_ENUM_ERR("O.Err pinlowimp", err_pinlowimp_ctrl),
1135 + SOC_ENUM_ERR("P.Err dcprot", err_dcprot_ctrl),
1136 +
1137 + //Power modes profiles
1138 + SOC_ENUM("Q.PM Prof", pwr_mode_prof_ctrl),
1139 +
1140 + // Power mode selection (Dynamic,1,2,3)
1141 + SOC_ENUM("R.Power Mode", pwr_mode_ctrl),
1142 +};
1143 +
1144 +//Machine Driver
1145 +static int ma120x0p_hw_params(struct snd_pcm_substream *substream,
1146 + struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1147 +{
1148 + u16 blen = 0x00;
1149 +
1150 + struct snd_soc_component *component = dai->component;
1151 +
1152 + priv_data->component = component;
1153 +
1154 + switch (params_format(params)) {
1155 + case SNDRV_PCM_FORMAT_S16_LE:
1156 + blen = 0x10;
1157 + break;
1158 + case SNDRV_PCM_FORMAT_S24_LE:
1159 + blen = 0x00;
1160 + break;
1161 + case SNDRV_PCM_FORMAT_S32_LE:
1162 + blen = 0x00;
1163 + break;
1164 + default:
1165 + dev_err(dai->dev, "Unsupported word length: %u\n",
1166 + params_format(params));
1167 + return -EINVAL;
1168 + }
1169 +
1170 + // set word length
1171 + snd_soc_component_update_bits(component, ma_i2s_framesize__a,
1172 + ma_i2s_framesize__mask, blen);
1173 +
1174 + return 0;
1175 +}
1176 +
1177 +static int ma120x0p_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
1178 +{
1179 + int val = 0;
1180 +
1181 + struct ma120x0p_priv *ma120x0p;
1182 +
1183 + struct snd_soc_component *component = dai->component;
1184 +
1185 + ma120x0p = snd_soc_component_get_drvdata(component);
1186 +
1187 + if (mute)
1188 + val = 0;
1189 + else
1190 + val = 1;
1191 +
1192 + gpiod_set_value_cansleep(priv_data->mute_gpio, val);
1193 +
1194 + return 0;
1195 +}
1196 +
1197 +static const struct snd_soc_dai_ops ma120x0p_dai_ops = {
1198 + .hw_params = ma120x0p_hw_params,
1199 + .mute_stream = ma120x0p_mute_stream,
1200 +};
1201 +
1202 +static struct snd_soc_dai_driver ma120x0p_dai = {
1203 + .name = "ma120x0p-amp",
1204 + .playback = {
1205 + .stream_name = "Playback",
1206 + .channels_min = 2,
1207 + .channels_max = 2,
1208 + .rates = SNDRV_PCM_RATE_CONTINUOUS,
1209 + .rate_min = 44100,
1210 + .rate_max = 48000,
1211 + .formats = SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE
1212 + },
1213 + .ops = &ma120x0p_dai_ops,
1214 +};
1215 +
1216 +//Codec Driver
1217 +static int ma120x0p_clear_err(struct snd_soc_component *component)
1218 +{
1219 + int ret = 0;
1220 +
1221 + struct ma120x0p_priv *ma120x0p;
1222 +
1223 + ma120x0p = snd_soc_component_get_drvdata(component);
1224 +
1225 + ret = snd_soc_component_update_bits(component,
1226 + ma_eh_clear__a, ma_eh_clear__mask, 0x00);
1227 + if (ret < 0)
1228 + return ret;
1229 +
1230 + ret = snd_soc_component_update_bits(component,
1231 + ma_eh_clear__a, ma_eh_clear__mask, 0x04);
1232 + if (ret < 0)
1233 + return ret;
1234 +
1235 + ret = snd_soc_component_update_bits(component,
1236 + ma_eh_clear__a, ma_eh_clear__mask, 0x00);
1237 + if (ret < 0)
1238 + return ret;
1239 +
1240 + return 0;
1241 +}
1242 +
1243 +static void ma120x0p_remove(struct snd_soc_component *component)
1244 +{
1245 + struct ma120x0p_priv *ma120x0p;
1246 +
1247 + ma120x0p = snd_soc_component_get_drvdata(component);
1248 +}
1249 +
1250 +static int ma120x0p_probe(struct snd_soc_component *component)
1251 +{
1252 + struct ma120x0p_priv *ma120x0p;
1253 +
1254 + int ret = 0;
1255 +
1256 + i2c = container_of(component->dev, struct i2c_client, dev);
1257 +
1258 + ma120x0p = snd_soc_component_get_drvdata(component);
1259 +
1260 + //Reset error
1261 + ma120x0p_clear_err(component);
1262 + if (ret < 0)
1263 + return ret;
1264 +
1265 + // set serial audio format I2S and enable audio processor
1266 + ret = snd_soc_component_write(component, ma_i2s_format__a, 0x08);
1267 + if (ret < 0)
1268 + return ret;
1269 +
1270 + // Enable audio limiter
1271 + ret = snd_soc_component_update_bits(component,
1272 + ma_audio_proc_limiterenable__a,
1273 + ma_audio_proc_limiterenable__mask, 0x40);
1274 + if (ret < 0)
1275 + return ret;
1276 +
1277 + // Set lim attack to fast
1278 + ret = snd_soc_component_update_bits(component,
1279 + ma_audio_proc_attack__a, ma_audio_proc_attack__mask, 0x80);
1280 + if (ret < 0)
1281 + return ret;
1282 +
1283 + // Set lim attack to low
1284 + ret = snd_soc_component_update_bits(component,
1285 + ma_audio_proc_release__a, ma_audio_proc_release__mask, 0x00);
1286 + if (ret < 0)
1287 + return ret;
1288 +
1289 + // set volume to 0dB
1290 + ret = snd_soc_component_write(component, ma_vol_db_master__a, 0x18);
1291 + if (ret < 0)
1292 + return ret;
1293 +
1294 + // set ch0 lim thresh to -15dB
1295 + ret = snd_soc_component_write(component, ma_thr_db_ch0__a, 0x27);
1296 + if (ret < 0)
1297 + return ret;
1298 +
1299 + // set ch1 lim thresh to -15dB
1300 + ret = snd_soc_component_write(component, ma_thr_db_ch1__a, 0x27);
1301 + if (ret < 0)
1302 + return ret;
1303 +
1304 + //Check for errors
1305 + ret = snd_soc_component_test_bits(component, ma_error_acc__a, 0x00, 0);
1306 + if (ret < 0)
1307 + return ret;
1308 + ret = snd_soc_component_test_bits(component, ma_error_acc__a, 0x01, 0);
1309 + if (ret < 0)
1310 + return ret;
1311 + ret = snd_soc_component_test_bits(component, ma_error_acc__a, 0x02, 0);
1312 + if (ret < 0)
1313 + return ret;
1314 + ret = snd_soc_component_test_bits(component, ma_error_acc__a, 0x08, 0);
1315 + if (ret < 0)
1316 + return ret;
1317 + ret = snd_soc_component_test_bits(component, ma_error_acc__a, 0x10, 0);
1318 + if (ret < 0)
1319 + return ret;
1320 + ret = snd_soc_component_test_bits(component, ma_error_acc__a, 0x20, 0);
1321 + if (ret < 0)
1322 + return ret;
1323 + ret = snd_soc_component_test_bits(component, ma_error_acc__a, 0x40, 0);
1324 + if (ret < 0)
1325 + return ret;
1326 + ret = snd_soc_component_test_bits(component, ma_error_acc__a, 0x80, 0);
1327 + if (ret < 0)
1328 + return ret;
1329 +
1330 + return 0;
1331 +}
1332 +
1333 +static int ma120x0p_set_bias_level(struct snd_soc_component *component,
1334 + enum snd_soc_bias_level level)
1335 +{
1336 + int ret = 0;
1337 +
1338 + struct ma120x0p_priv *ma120x0p;
1339 +
1340 + ma120x0p = snd_soc_component_get_drvdata(component);
1341 +
1342 + switch (level) {
1343 + case SND_SOC_BIAS_ON:
1344 + break;
1345 +
1346 + case SND_SOC_BIAS_PREPARE:
1347 + break;
1348 +
1349 + case SND_SOC_BIAS_STANDBY:
1350 + ret = gpiod_get_value_cansleep(priv_data->enable_gpio);
1351 + if (ret != 0) {
1352 + dev_err(component->dev, "Device ma120x0p disabled in STANDBY BIAS: %d\n",
1353 + ret);
1354 + return ret;
1355 + }
1356 + break;
1357 +
1358 + case SND_SOC_BIAS_OFF:
1359 + break;
1360 + }
1361 +
1362 + return 0;
1363 +}
1364 +
1365 +static const struct snd_soc_dapm_widget ma120x0p_dapm_widgets[] = {
1366 + SND_SOC_DAPM_OUTPUT("OUT_A"),
1367 + SND_SOC_DAPM_OUTPUT("OUT_B"),
1368 +};
1369 +
1370 +static const struct snd_soc_dapm_route ma120x0p_dapm_routes[] = {
1371 + { "OUT_B", NULL, "Playback" },
1372 + { "OUT_A", NULL, "Playback" },
1373 +};
1374 +
1375 +static const struct snd_soc_component_driver ma120x0p_component_driver = {
1376 + .probe = ma120x0p_probe,
1377 + .remove = ma120x0p_remove,
1378 + .set_bias_level = ma120x0p_set_bias_level,
1379 + .dapm_widgets = ma120x0p_dapm_widgets,
1380 + .num_dapm_widgets = ARRAY_SIZE(ma120x0p_dapm_widgets),
1381 + .dapm_routes = ma120x0p_dapm_routes,
1382 + .num_dapm_routes = ARRAY_SIZE(ma120x0p_dapm_routes),
1383 + .controls = ma120x0p_snd_controls,
1384 + .num_controls = ARRAY_SIZE(ma120x0p_snd_controls),
1385 + .use_pmdown_time = 1,
1386 + .endianness = 1,
1387 + .non_legacy_dai_naming = 1,
1388 +};
1389 +
1390 +//I2C Driver
1391 +static const struct reg_default ma120x0p_reg_defaults[] = {
1392 + { 0x01, 0x3c },
1393 +};
1394 +
1395 +static bool ma120x0p_reg_volatile(struct device *dev, unsigned int reg)
1396 +{
1397 + switch (reg) {
1398 + case ma_error__a:
1399 + return true;
1400 + default:
1401 + return false;
1402 + }
1403 +}
1404 +
1405 +static const struct of_device_id ma120x0p_of_match[] = {
1406 + { .compatible = "ma,ma120x0p", },
1407 + { }
1408 +};
1409 +
1410 +MODULE_DEVICE_TABLE(of, ma120x0p_of_match);
1411 +
1412 +static struct regmap_config ma120x0p_regmap_config = {
1413 + .reg_bits = 8,
1414 + .val_bits = 8,
1415 +
1416 + .max_register = 255,
1417 + .volatile_reg = ma120x0p_reg_volatile,
1418 +
1419 + .cache_type = REGCACHE_RBTREE,
1420 + .reg_defaults = ma120x0p_reg_defaults,
1421 + .num_reg_defaults = ARRAY_SIZE(ma120x0p_reg_defaults),
1422 +};
1423 +
1424 +static int ma120x0p_i2c_probe(struct i2c_client *i2c,
1425 + const struct i2c_device_id *id)
1426 +{
1427 + int ret;
1428 +
1429 + priv_data = devm_kzalloc(&i2c->dev, sizeof(*priv_data), GFP_KERNEL);
1430 + if (!priv_data)
1431 + return -ENOMEM;
1432 + i2c_set_clientdata(i2c, priv_data);
1433 +
1434 + priv_data->regmap = devm_regmap_init_i2c(i2c, &ma120x0p_regmap_config);
1435 + if (IS_ERR(priv_data->regmap)) {
1436 + ret = PTR_ERR(priv_data->regmap);
1437 + return ret;
1438 + }
1439 +
1440 + //Startup sequence
1441 +
1442 + //Make sure the device is muted
1443 + priv_data->mute_gpio = devm_gpiod_get(&i2c->dev, "mute_gp",
1444 + GPIOD_OUT_LOW);
1445 + if (IS_ERR(priv_data->mute_gpio)) {
1446 + ret = PTR_ERR(priv_data->mute_gpio);
1447 + dev_err(&i2c->dev, "Failed to get mute gpio line: %d\n", ret);
1448 + return ret;
1449 + }
1450 + msleep(50);
1451 +
1452 +// MA120xx0P devices are usually powered by an integrated boost converter.
1453 +// An option GPIO control line is provided to enable the booster properly and
1454 +// in sync with the enable and mute GPIO lines.
1455 + priv_data->booster_gpio = devm_gpiod_get_optional(&i2c->dev,
1456 + "booster_gp", GPIOD_OUT_LOW);
1457 + if (IS_ERR(priv_data->booster_gpio)) {
1458 + ret = PTR_ERR(priv_data->booster_gpio);
1459 + dev_err(&i2c->dev,
1460 + "Failed to get booster enable gpio line: %d\n", ret);
1461 + return ret;
1462 + }
1463 + msleep(50);
1464 +
1465 + //Enable booster and wait 200ms until stable PVDD
1466 + gpiod_set_value_cansleep(priv_data->booster_gpio, 1);
1467 + msleep(200);
1468 +
1469 + //Enable ma120x0pp
1470 + priv_data->enable_gpio = devm_gpiod_get(&i2c->dev,
1471 + "enable_gp", GPIOD_OUT_LOW);
1472 + if (IS_ERR(priv_data->enable_gpio)) {
1473 + ret = PTR_ERR(priv_data->enable_gpio);
1474 + dev_err(&i2c->dev,
1475 + "Failed to get ma120x0p enable gpio line: %d\n", ret);
1476 + return ret;
1477 + }
1478 + msleep(50);
1479 +
1480 + //Optional use of ma120x0pp error line as an interrupt trigger to
1481 + //platform GPIO.
1482 + //Get error input gpio ma120x0p
1483 + priv_data->error_gpio = devm_gpiod_get_optional(&i2c->dev,
1484 + "error_gp", GPIOD_IN);
1485 + if (IS_ERR(priv_data->error_gpio)) {
1486 + ret = PTR_ERR(priv_data->error_gpio);
1487 + dev_err(&i2c->dev,
1488 + "Failed to get ma120x0p error gpio line: %d\n", ret);
1489 + return ret;
1490 + }
1491 +
1492 + if (priv_data->error_gpio != NULL) {
1493 + irqNumber = gpiod_to_irq(priv_data->error_gpio);
1494 +
1495 + ret = devm_request_threaded_irq(&i2c->dev,
1496 + irqNumber, ma120x0p_irq_handler,
1497 + NULL, IRQF_TRIGGER_FALLING,
1498 + "ma120x0p", priv_data);
1499 + if (ret != 0)
1500 + dev_warn(&i2c->dev, "Failed to request IRQ: %d\n",
1501 + ret);
1502 + }
1503 +
1504 + ret = devm_snd_soc_register_component(&i2c->dev,
1505 + &ma120x0p_component_driver, &ma120x0p_dai, 1);
1506 +
1507 + return ret;
1508 +}
1509 +
1510 +static irqreturn_t ma120x0p_irq_handler(int irq, void *data)
1511 +{
1512 + gpiod_set_value_cansleep(priv_data->mute_gpio, 0);
1513 + gpiod_set_value_cansleep(priv_data->enable_gpio, 1);
1514 + return IRQ_HANDLED;
1515 +}
1516 +
1517 +static int ma120x0p_i2c_remove(struct i2c_client *i2c)
1518 +{
1519 + snd_soc_unregister_component(&i2c->dev);
1520 + i2c_set_clientdata(i2c, NULL);
1521 +
1522 + gpiod_set_value_cansleep(priv_data->mute_gpio, 0);
1523 + msleep(30);
1524 + gpiod_set_value_cansleep(priv_data->enable_gpio, 1);
1525 + msleep(200);
1526 + gpiod_set_value_cansleep(priv_data->booster_gpio, 0);
1527 + msleep(200);
1528 +
1529 + kfree(priv_data);
1530 +
1531 + return 0;
1532 +}
1533 +
1534 +static void ma120x0p_i2c_shutdown(struct i2c_client *i2c)
1535 +{
1536 + snd_soc_unregister_component(&i2c->dev);
1537 + i2c_set_clientdata(i2c, NULL);
1538 +
1539 + gpiod_set_value_cansleep(priv_data->mute_gpio, 0);
1540 + msleep(30);
1541 + gpiod_set_value_cansleep(priv_data->enable_gpio, 1);
1542 + msleep(200);
1543 + gpiod_set_value_cansleep(priv_data->booster_gpio, 0);
1544 + msleep(200);
1545 +
1546 + kfree(priv_data);
1547 +}
1548 +
1549 +static const struct i2c_device_id ma120x0p_i2c_id[] = {
1550 + { "ma120x0p", 0 },
1551 + { }
1552 +};
1553 +
1554 +MODULE_DEVICE_TABLE(i2c, ma120x0p_i2c_id);
1555 +
1556 +static struct i2c_driver ma120x0p_i2c_driver = {
1557 + .driver = {
1558 + .name = "ma120x0p",
1559 + .owner = THIS_MODULE,
1560 + .of_match_table = ma120x0p_of_match,
1561 + },
1562 + .probe = ma120x0p_i2c_probe,
1563 + .remove = ma120x0p_i2c_remove,
1564 + .shutdown = ma120x0p_i2c_shutdown,
1565 + .id_table = ma120x0p_i2c_id
1566 +};
1567 +
1568 +static int __init ma120x0p_modinit(void)
1569 +{
1570 + int ret = 0;
1571 +
1572 + ret = i2c_add_driver(&ma120x0p_i2c_driver);
1573 + if (ret != 0) {
1574 + pr_err("Failed to register MA120X0P I2C driver: %d\n", ret);
1575 + return ret;
1576 + }
1577 + return ret;
1578 +}
1579 +module_init(ma120x0p_modinit);
1580 +
1581 +static void __exit ma120x0p_exit(void)
1582 +{
1583 + i2c_del_driver(&ma120x0p_i2c_driver);
1584 +}
1585 +module_exit(ma120x0p_exit);
1586 +
1587 +MODULE_AUTHOR("Ariel Muszkat ariel.muszkat@gmail.com>");
1588 +MODULE_DESCRIPTION("ASoC driver for ma120x0p");
1589 +MODULE_LICENSE("GPL v2");
OpenWrt Source Repository