target/linux/bcm27xx/patches-5.4/950-0713-vc4_hdmi_regs-Make-interrupt-mask-variant-specific.patch

   1 From 9a9f4303c95f18cc062569c9c5d5240d06ddd69b Mon Sep 17 00:00:00 2001
   2 From: Dom Cobley <popcornmix@gmail.com>
   3 Date: Thu, 7 May 2020 18:16:08 +0100
   4 Subject: [PATCH] vc4_hdmi_regs: Make interrupt mask variant specific
   5
   6 Signed-off-by: Dom Cobley <popcornmix@gmail.com>
   7 ---
   8  drivers/gpu/drm/vc4/vc4_hdmi.c | 14 ++++++++++----
   9  drivers/gpu/drm/vc4/vc4_hdmi.h |  3 +++
  10  drivers/gpu/drm/vc4/vc4_regs.h |  9 +++++++++
  11  3 files changed, 22 insertions(+), 4 deletions(-)
  12
  13 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c
  14 +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
  15 @@ -1286,7 +1286,7 @@ static irqreturn_t vc4_cec_irq_handler(i
  16         u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
  17         u32 cntrl1, cntrl5;
  18
  19 -       if (!(stat & VC4_HDMI_CPU_CEC))
  20 +       if (!(stat & vc4_hdmi->variant->cec_mask))
  21                 return IRQ_NONE;
  22         vc4_hdmi->cec_rx_msg.len = 0;
  23         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
  24 @@ -1302,7 +1302,7 @@ static irqreturn_t vc4_cec_irq_handler(i
  25                 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
  26         }
  27         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
  28 -       HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
  29 +       HDMI_WRITE(HDMI_CEC_CPU_CLEAR, vc4_hdmi->variant->cec_mask);
  30
  31         return IRQ_WAKE_THREAD;
  32  }
  33 @@ -1341,9 +1341,9 @@ static int vc4_hdmi_cec_adap_enable(stru
  34                          ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
  35                          ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
  36
  37 -               HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
  38 +               HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, vc4_hdmi->variant->cec_mask);
  39         } else {
  40 -               HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
  41 +               HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, vc4_hdmi->variant->cec_mask);
  42                 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
  43                            VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
  44         }
  45 @@ -1785,6 +1785,8 @@ static const struct vc4_hdmi_variant bcm
  46         .get_hsm_clock          = vc4_hdmi_get_hsm_clock,
  47         .calc_hsm_clock         = vc4_hdmi_calc_hsm_clock,
  48         .channel_map            = vc4_hdmi_channel_map,
  49 +
  50 +       .cec_mask = VC4_HDMI_CPU_CEC,
  51  };
  52
  53  static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
  54 @@ -1810,6 +1812,8 @@ static const struct vc4_hdmi_variant bcm
  55         .get_hsm_clock          = vc5_hdmi_get_hsm_clock,
  56         .calc_hsm_clock         = vc5_hdmi_calc_hsm_clock,
  57         .channel_map            = vc5_hdmi_channel_map,
  58 +
  59 +       .cec_mask = VC5_HDMI0_CPU_CEC_RX | VC5_HDMI0_CPU_CEC_TX,
  60  };
  61
  62  static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
  63 @@ -1835,6 +1839,8 @@ static const struct vc4_hdmi_variant bcm
  64         .get_hsm_clock          = vc5_hdmi_get_hsm_clock,
  65         .calc_hsm_clock         = vc5_hdmi_calc_hsm_clock,
  66         .channel_map            = vc5_hdmi_channel_map,
  67 +
  68 +       .cec_mask = VC5_HDMI1_CPU_CEC_RX | VC5_HDMI1_CPU_CEC_TX,
  69  };
  70
  71  static const struct of_device_id vc4_hdmi_dt_match[] = {
  72 --- a/drivers/gpu/drm/vc4/vc4_hdmi.h
  73 +++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
  74 @@ -97,6 +97,9 @@ struct vc4_hdmi_variant {
  75
  76         /* Callback to get channel map */
  77         u32 (*channel_map)(struct vc4_hdmi *vc4_hdmi, u32 channel_mask);
  78 +
  79 +       /* Bitmask for CEC events */
  80 +       u32 cec_mask;
  81  };
  82
  83  /* HDMI audio information */
  84 --- a/drivers/gpu/drm/vc4/vc4_regs.h
  85 +++ b/drivers/gpu/drm/vc4/vc4_regs.h
  86 @@ -668,6 +668,15 @@
  87  # define VC4_HDMI_CPU_CEC                      BIT(6)
  88  # define VC4_HDMI_CPU_HOTPLUG                  BIT(0)
  89
  90 +# define VC5_HDMI0_CPU_CEC_RX                  BIT(1)
  91 +# define VC5_HDMI0_CPU_CEC_TX                  BIT(0)
  92 +# define VC5_HDMI0_CPU_HOTPLUG_CONN            BIT(4)
  93 +# define VC5_HDMI0_CPU_HOTPLUG_REM             BIT(5)
  94 +# define VC5_HDMI1_CPU_CEC_RX                  BIT(7)
  95 +# define VC5_HDMI1_CPU_CEC_TX                  BIT(6)
  96 +# define VC5_HDMI1_CPU_HOTPLUG_CONN            BIT(10)
  97 +# define VC5_HDMI1_CPU_HOTPLUG_REM             BIT(11)
  98 +
  99  /* Debug: Current receive value on the CEC pad. */
 100  # define VC4_HD_CECRXD                         BIT(9)
 101  /* Debug: Override CEC output to 0. */