target/linux/bcm4908/patches-5.4/075-v5.13-0002-net-dsa-bcm_sf2-setup-BCM4908-internal-crossbar.patch

   1 From a9349f08ec6c1251d41ef167d27a15cc39bc5b97 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
   3 Date: Fri, 12 Mar 2021 11:41:08 +0100
   4 Subject: [PATCH] net: dsa: bcm_sf2: setup BCM4908 internal crossbar
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 On some SoCs (e.g. BCM4908, BCM631[345]8) SF2 has an integrated
  10 crossbar. It allows connecting its selected external ports to internal
  11 ports. It's used by vendors to handle custom Ethernet setups.
  12
  13 BCM4908 has following 3x2 crossbar. On Asus GT-AC5300 rgmii is used for
  14 connecting external BCM53134S switch. GPHY4 is usually used for WAN
  15 port. More fancy devices use SerDes for 2.5 Gbps Ethernet.
  16
  17               ┌──────────┐
  18 SerDes ─── 0 ─┤          │
  19               │   3x2    ├─ 0 ─── switch port 7
  20  GPHY4 ─── 1 ─┤          │
  21               │ crossbar ├─ 1 ─── runner (accelerator)
  22  rgmii ─── 2 ─┤          │
  23               └──────────┘
  24
  25 Use setup data based on DT info to configure BCM4908's switch port 7.
  26 Right now only GPHY and rgmii variants are supported. Handling SerDes
  27 can be implemented later.
  28
  29 Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
  30 Acked-by: Florian Fainelli <f.fainelli@gmail.com>
  31 Signed-off-by: David S. Miller <davem@davemloft.net>
  32 ---
  33  drivers/net/dsa/bcm_sf2.c      | 45 ++++++++++++++++++++++++++++++++++
  34  drivers/net/dsa/bcm_sf2.h      |  1 +
  35  drivers/net/dsa/bcm_sf2_regs.h |  7 ++++++
  36  3 files changed, 53 insertions(+)
  37
  38 --- a/drivers/net/dsa/bcm_sf2.c
  39 +++ b/drivers/net/dsa/bcm_sf2.c
  40 @@ -369,6 +369,44 @@ static int bcm_sf2_sw_rst(struct bcm_sf2
  41         return 0;
  42  }
  43
  44 +static void bcm_sf2_crossbar_setup(struct bcm_sf2_priv *priv)
  45 +{
  46 +       struct device *dev = priv->dev->ds->dev;
  47 +       int shift;
  48 +       u32 mask;
  49 +       u32 reg;
  50 +       int i;
  51 +
  52 +       mask = BIT(priv->num_crossbar_int_ports) - 1;
  53 +
  54 +       reg = reg_readl(priv, REG_CROSSBAR);
  55 +       switch (priv->type) {
  56 +       case BCM4908_DEVICE_ID:
  57 +               shift = CROSSBAR_BCM4908_INT_P7 * priv->num_crossbar_int_ports;
  58 +               reg &= ~(mask << shift);
  59 +               if (0) /* FIXME */
  60 +                       reg |= CROSSBAR_BCM4908_EXT_SERDES << shift;
  61 +               else if (priv->int_phy_mask & BIT(7))
  62 +                       reg |= CROSSBAR_BCM4908_EXT_GPHY4 << shift;
  63 +               else if (phy_interface_mode_is_rgmii(priv->port_sts[7].mode))
  64 +                       reg |= CROSSBAR_BCM4908_EXT_RGMII << shift;
  65 +               else if (WARN(1, "Invalid port mode\n"))
  66 +                       return;
  67 +               break;
  68 +       default:
  69 +               return;
  70 +       }
  71 +       reg_writel(priv, reg, REG_CROSSBAR);
  72 +
  73 +       reg = reg_readl(priv, REG_CROSSBAR);
  74 +       for (i = 0; i < priv->num_crossbar_int_ports; i++) {
  75 +               shift = i * priv->num_crossbar_int_ports;
  76 +
  77 +               dev_dbg(dev, "crossbar int port #%d - ext port #%d\n", i,
  78 +                       (reg >> shift) & mask);
  79 +       }
  80 +}
  81 +
  82  static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
  83  {
  84         intrl2_0_mask_set(priv, 0xffffffff);
  85 @@ -734,6 +772,8 @@ static int bcm_sf2_sw_resume(struct dsa_
  86                 return ret;
  87         }
  88
  89 +       bcm_sf2_crossbar_setup(priv);
  90 +
  91         ret = bcm_sf2_cfp_resume(ds);
  92         if (ret)
  93                 return ret;
  94 @@ -996,6 +1036,7 @@ struct bcm_sf2_of_data {
  95         const u16 *reg_offsets;
  96         unsigned int core_reg_align;
  97         unsigned int num_cfp_rules;
  98 +       unsigned int num_crossbar_int_ports;
  99  };
 100
 101  static const u16 bcm_sf2_4908_reg_offsets[] = {
 102 @@ -1020,6 +1061,7 @@ static const struct bcm_sf2_of_data bcm_
 103         .core_reg_align = 0,
 104         .reg_offsets    = bcm_sf2_4908_reg_offsets,
 105         .num_cfp_rules  = 0, /* FIXME */
 106 +       .num_crossbar_int_ports = 2,
 107  };
 108
 109  /* Register offsets for the SWITCH_REG_* block */
 110 @@ -1130,6 +1172,7 @@ static int bcm_sf2_sw_probe(struct platf
 111         priv->reg_offsets = data->reg_offsets;
 112         priv->core_reg_align = data->core_reg_align;
 113         priv->num_cfp_rules = data->num_cfp_rules;
 114 +       priv->num_crossbar_int_ports = data->num_crossbar_int_ports;
 115
 116         /* Auto-detection using standard registers will not work, so
 117          * provide an indication of what kind of device we are for
 118 @@ -1184,6 +1227,8 @@ static int bcm_sf2_sw_probe(struct platf
 119                 return ret;
 120         }
 121
 122 +       bcm_sf2_crossbar_setup(priv);
 123 +
 124         bcm_sf2_gphy_enable_set(priv->dev->ds, true);
 125
 126         ret = bcm_sf2_mdio_register(ds);
 127 --- a/drivers/net/dsa/bcm_sf2.h
 128 +++ b/drivers/net/dsa/bcm_sf2.h
 129 @@ -70,6 +70,7 @@ struct bcm_sf2_priv {
 130         const u16                       *reg_offsets;
 131         unsigned int                    core_reg_align;
 132         unsigned int                    num_cfp_rules;
 133 +       unsigned int                    num_crossbar_int_ports;
 134
 135         /* spinlock protecting access to the indirect registers */
 136         spinlock_t                      indir_lock;
 137 --- a/drivers/net/dsa/bcm_sf2_regs.h
 138 +++ b/drivers/net/dsa/bcm_sf2_regs.h
 139 @@ -48,6 +48,13 @@ enum bcm_sf2_reg_offs {
 140  #define  PHY_PHYAD_SHIFT               8
 141  #define  PHY_PHYAD_MASK                        0x1F
 142
 143 +/* Relative to REG_CROSSBAR */
 144 +#define CROSSBAR_BCM4908_INT_P7                0
 145 +#define CROSSBAR_BCM4908_INT_RUNNER    1
 146 +#define CROSSBAR_BCM4908_EXT_SERDES    0
 147 +#define CROSSBAR_BCM4908_EXT_GPHY4     1
 148 +#define CROSSBAR_BCM4908_EXT_RGMII     2
 149 +
 150  #define REG_RGMII_CNTRL_P(x)           (REG_RGMII_0_CNTRL + (x))
 151
 152  /* Relative to REG_RGMII_CNTRL */