target/linux/bcm53xx/files/arch/arm/boot/compressed/cache-v7-min.S

   1 /*
   2  * This is a part of mm/cache-v7.S with extracted entry flushing D-cache. We
   3  * need it for Broadcom devices with broken bootloader leaving cache enabled.
   4  *
   5  * Copyright (C) 2001 Deep Blue Solutions Ltd.
   6  * Copyright (C) 2005 ARM Ltd.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/linkage.h>
  14 #include <linux/init.h>
  15
  16         __INIT
  17
  18 /*
  19  *      v7_flush_dcache_all()
  20  *
  21  *      Flush the whole D-cache.
  22  *
  23  *      Corrupted registers: r0-r5, r7, r9-r11
  24  *
  25  *      - mm    - mm_struct describing address space
  26  */
  27 ENTRY(v7_flush_dcache_all)
  28         mrc     p15, 1, r0, c0, c0, 1           @ read clidr
  29         ands    r3, r0, #0x7000000              @ extract loc from clidr
  30         mov     r3, r3, lsr #23                 @ left align loc bit field
  31         beq     finished                        @ if loc is 0, then no need to clean
  32         mov     r10, #0                         @ start clean at cache level 0
  33 loop1:
  34         add     r2, r10, r10, lsr #1            @ work out 3x current cache level
  35         mov     r1, r0, lsr r2                  @ extract cache type bits from clidr
  36         and     r1, r1, #7                      @ mask of the bits for current cache only
  37         cmp     r1, #2                          @ see what cache we have at this level
  38         blt     skip                            @ skip if no cache, or just i-cache
  39         mcr     p15, 2, r10, c0, c0, 0          @ select current cache level in cssr
  40         isb                                     @ isb to sych the new cssr&csidr
  41         mrc     p15, 1, r1, c0, c0, 0           @ read the new csidr
  42         and     r2, r1, #7                      @ extract the length of the cache lines
  43         add     r2, r2, #4                      @ add 4 (line length offset)
  44         ldr     r4, =0x3ff
  45         ands    r4, r4, r1, lsr #3              @ find maximum number on the way size
  46         clz     r5, r4                          @ find bit position of way size increment
  47         ldr     r7, =0x7fff
  48         ands    r7, r7, r1, lsr #13             @ extract max number of the index size
  49 loop2:
  50         mov     r9, r4                          @ create working copy of max way size
  51 loop3:
  52         orr     r11, r10, r9, lsl r5            @ factor way and cache number into r11
  53         orr     r11, r11, r7, lsl r2            @ factor index number into r11
  54         mcr     p15, 0, r11, c7, c14, 2         @ clean & invalidate by set/way
  55         subs    r9, r9, #1                      @ decrement the way
  56         bge     loop3
  57         subs    r7, r7, #1                      @ decrement the index
  58         bge     loop2
  59 skip:
  60         add     r10, r10, #2                    @ increment cache number
  61         cmp     r3, r10
  62         bgt     loop1
  63 finished:
  64         mov     r10, #0                         @ swith back to cache level 0
  65         mcr     p15, 2, r10, c0, c0, 0          @ select current cache level in cssr
  66         isb
  67         mov     pc, lr