bcm53xx: revert SPI controller commit breaking flash reads
[openwrt/openwrt.git] / target / linux / bcm53xx / patches-4.14 / 800-Revert-spi-bcm-qspi-Fix-bcm_qspi_bspi_read-performan.patch
1 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
2 Subject: [PATCH] Revert "spi: bcm-qspi: Fix bcm_qspi_bspi_read() performance"
3 MIME-Version: 1.0
4 Content-Type: text/plain; charset=UTF-8
5 Content-Transfer-Encoding: 8bit
6
7 This reverts commit 345309fa7c0c9206a5344d379b174499952d79d9.
8
9 BSPI reads became unstable starting with above commit. There are BSPI
10 timeouts like this:
11 [ 15.637809] bcm_iproc 18029200.spi: timeout waiting for BSPI
12 (...)
13 [ 15.997809] bcm_iproc 18029200.spi: timeout waiting for BSPI
14 which cause filesystem stability problems.
15
16 Before above commit every time that bcm_qspi_bspi_lr_l2_isr() called
17 bcm_qspi_bspi_lr_l2_isr() it was resulting in bspi_rf_msg_len becoming
18 0.
19 With that change it's not the case anymore which suggests there may be
20 some bug around that code.
21
22 It has changed and the new behavior seems to be causing problems.
23
24 Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
25 ---
26
27 --- a/drivers/spi/spi-bcm-qspi.c
28 +++ b/drivers/spi/spi-bcm-qspi.c
29 @@ -88,7 +88,7 @@
30 #define BSPI_BPP_MODE_SELECT_MASK BIT(8)
31 #define BSPI_BPP_ADDR_SELECT_MASK BIT(16)
32
33 -#define BSPI_READ_LENGTH 512
34 +#define BSPI_READ_LENGTH 256
35
36 /* MSPI register offsets */
37 #define MSPI_SPCR0_LSB 0x000
38 @@ -806,7 +806,7 @@ static int bcm_qspi_bspi_flash_read(stru
39 struct spi_flash_read_message *msg)
40 {
41 struct bcm_qspi *qspi = spi_master_get_devdata(spi->master);
42 - u32 addr = 0, len, rdlen, len_words;
43 + u32 addr = 0, len, len_words;
44 int ret = 0;
45 unsigned long timeo = msecs_to_jiffies(100);
46 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
47 @@ -819,7 +819,7 @@ static int bcm_qspi_bspi_flash_read(stru
48 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0);
49
50 /*
51 - * when using flex mode we need to send
52 + * when using flex mode mode we need to send
53 * the upper address byte to bspi
54 */
55 if (bcm_qspi_bspi_ver_three(qspi) == false) {
56 @@ -833,56 +833,47 @@ static int bcm_qspi_bspi_flash_read(stru
57 else
58 addr = msg->from & 0x00ffffff;
59
60 + /* set BSPI RAF buffer max read length */
61 + len = msg->len;
62 + if (len > BSPI_READ_LENGTH)
63 + len = BSPI_READ_LENGTH;
64 +
65 if (bcm_qspi_bspi_ver_three(qspi) == true)
66 addr = (addr + 0xc00000) & 0xffffff;
67
68 - /*
69 - * read into the entire buffer by breaking the reads
70 - * into RAF buffer read lengths
71 - */
72 - len = msg->len;
73 + reinit_completion(&qspi->bspi_done);
74 + bcm_qspi_enable_bspi(qspi);
75 + len_words = (len + 3) >> 2;
76 + qspi->bspi_rf_msg = msg;
77 + qspi->bspi_rf_msg_status = 0;
78 qspi->bspi_rf_msg_idx = 0;
79 + qspi->bspi_rf_msg_len = len;
80 + dev_dbg(&qspi->pdev->dev, "bspi xfr addr 0x%x len 0x%x", addr, len);
81
82 - do {
83 - if (len > BSPI_READ_LENGTH)
84 - rdlen = BSPI_READ_LENGTH;
85 - else
86 - rdlen = len;
87 -
88 - reinit_completion(&qspi->bspi_done);
89 - bcm_qspi_enable_bspi(qspi);
90 - len_words = (rdlen + 3) >> 2;
91 - qspi->bspi_rf_msg = msg;
92 - qspi->bspi_rf_msg_status = 0;
93 - qspi->bspi_rf_msg_len = rdlen;
94 - dev_dbg(&qspi->pdev->dev,
95 - "bspi xfr addr 0x%x len 0x%x", addr, rdlen);
96 - bcm_qspi_write(qspi, BSPI, BSPI_RAF_START_ADDR, addr);
97 - bcm_qspi_write(qspi, BSPI, BSPI_RAF_NUM_WORDS, len_words);
98 - bcm_qspi_write(qspi, BSPI, BSPI_RAF_WATERMARK, 0);
99 - if (qspi->soc_intc) {
100 - /*
101 - * clear soc MSPI and BSPI interrupts and enable
102 - * BSPI interrupts.
103 - */
104 - soc_intc->bcm_qspi_int_ack(soc_intc, MSPI_BSPI_DONE);
105 - soc_intc->bcm_qspi_int_set(soc_intc, BSPI_DONE, true);
106 - }
107 + bcm_qspi_write(qspi, BSPI, BSPI_RAF_START_ADDR, addr);
108 + bcm_qspi_write(qspi, BSPI, BSPI_RAF_NUM_WORDS, len_words);
109 + bcm_qspi_write(qspi, BSPI, BSPI_RAF_WATERMARK, 0);
110 +
111 + if (qspi->soc_intc) {
112 + /*
113 + * clear soc MSPI and BSPI interrupts and enable
114 + * BSPI interrupts.
115 + */
116 + soc_intc->bcm_qspi_int_ack(soc_intc, MSPI_BSPI_DONE);
117 + soc_intc->bcm_qspi_int_set(soc_intc, BSPI_DONE, true);
118 + }
119
120 - /* Must flush previous writes before starting BSPI operation */
121 - mb();
122 - bcm_qspi_bspi_lr_start(qspi);
123 - if (!wait_for_completion_timeout(&qspi->bspi_done, timeo)) {
124 - dev_err(&qspi->pdev->dev, "timeout waiting for BSPI\n");
125 - ret = -ETIMEDOUT;
126 - break;
127 - }
128 + /* Must flush previous writes before starting BSPI operation */
129 + mb();
130
131 - /* set msg return length */
132 - msg->retlen += rdlen;
133 - addr += rdlen;
134 - len -= rdlen;
135 - } while (len);
136 + bcm_qspi_bspi_lr_start(qspi);
137 + if (!wait_for_completion_timeout(&qspi->bspi_done, timeo)) {
138 + dev_err(&qspi->pdev->dev, "timeout waiting for BSPI\n");
139 + ret = -ETIMEDOUT;
140 + } else {
141 + /* set the return length for the caller */
142 + msg->retlen = len;
143 + }
144
145 return ret;
146 }