target/linux/bcm53xx/patches-4.4/087-0003-PCI-iproc-Add-iProc-PCIe-MSI-device-tree-binding.patch

   1 From c7bd48195377435ecaf38869b936be8e7abe3489 Mon Sep 17 00:00:00 2001
   2 From: Ray Jui <rjui@broadcom.com>
   3 Date: Fri, 4 Dec 2015 09:35:00 -0800
   4 Subject: [PATCH 3/5] PCI: iproc: Add iProc PCIe MSI device tree binding
   5
   6 Update the iProc PCIe device tree bindings with added binding information
   7 for MSI.
   8
   9 Signed-off-by: Ray Jui <rjui@broadcom.com>
  10 Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  11 Reviewed-by: Anup Patel <anup.patel@broadcom.com>
  12 Reviewed-by: Vikram Prakash <vikramp@broadcom.com>
  13 Reviewed-by: Scott Branden <sbranden@broadcom.com>
  14 ---
  15  .../devicetree/bindings/pci/brcm,iproc-pcie.txt    | 35 ++++++++++++++++++++++
  16  1 file changed, 35 insertions(+)
  17
  18 --- a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt
  19 +++ b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt
  20 @@ -35,6 +35,28 @@ Optional:
  21  - brcm,pcie-ob-oarr-size: Some iProc SoCs need the OARR size bit to be set to
  22  increase the outbound window size
  23
  24 +MSI support (optional):
  25 +
  26 +For older platforms without MSI integrated in the GIC, iProc PCIe core provides
  27 +an event queue based MSI support.  The iProc MSI uses host memories to store
  28 +MSI posted writes in the event queues
  29 +
  30 +- msi-parent: Link to the device node of the MSI controller.  On newer iProc
  31 +platforms, the MSI controller may be gicv2m or gicv3-its.  On older iProc
  32 +platforms without MSI support in its interrupt controller, one may use the
  33 +event queue based MSI support integrated within the iProc PCIe core.
  34 +
  35 +When the iProc event queue based MSI is used, one needs to define the
  36 +following properties in the MSI device node:
  37 +- compatible: Must be "brcm,iproc-msi"
  38 +- msi-controller: claims itself as an MSI controller
  39 +- interrupt-parent: Link to its parent interrupt device
  40 +- interrupts: List of interrupt IDs from its parent interrupt device
  41 +
  42 +Optional properties:
  43 +- brcm,pcie-msi-inten: Needs to be present for some older iProc platforms that
  44 +require the interrupt enable registers to be set explicitly to enable MSI
  45 +
  46  Example:
  47         pcie0: pcie@18012000 {
  48                 compatible = "brcm,iproc-pcie";
  49 @@ -61,6 +83,19 @@ Example:
  50                 brcm,pcie-ob-oarr-size;
  51                 brcm,pcie-ob-axi-offset = <0x00000000>;
  52                 brcm,pcie-ob-window-size = <256>;
  53 +
  54 +               msi-parent = <&msi0>;
  55 +
  56 +               /* iProc event queue based MSI */
  57 +               msi0: msi@18012000 {
  58 +                       compatible = "brcm,iproc-msi";
  59 +                       msi-controller;
  60 +                       interrupt-parent = <&gic>;
  61 +                       interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>,
  62 +                                    <GIC_SPI 97 IRQ_TYPE_NONE>,
  63 +                                    <GIC_SPI 98 IRQ_TYPE_NONE>,
  64 +                                    <GIC_SPI 99 IRQ_TYPE_NONE>,
  65 +               };
  66         };
  67
  68         pcie1: pcie@18013000 {